Commit 5c130f659b20d53667e07957ebaa3e656f72b276
1 parent
d397abbd
Yet more phys_ram_base elimination.
Signed-off-by: Paul Brook <paul@cofdesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7067 c046a42c-6fe2-441c-8c8c-71466251a162
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12 changed files
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103 additions
and
108 deletions
hw/nseries.c
... | ... | @@ -1342,6 +1342,7 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device, |
1342 | 1342 | |
1343 | 1343 | if (option_rom[0] && (boot_device[0] == 'n' || !kernel_filename)) { |
1344 | 1344 | int rom_size; |
1345 | + uint8_t nolo_tags[0x10000]; | |
1345 | 1346 | /* No, wait, better start at the ROM. */ |
1346 | 1347 | s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000; |
1347 | 1348 | |
... | ... | @@ -1359,7 +1360,8 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device, |
1359 | 1360 | sdram_size - 0x400000); |
1360 | 1361 | printf("%i bytes of image loaded\n", rom_size); |
1361 | 1362 | |
1362 | - n800_setup_nolo_tags(phys_ram_base + sdram_size); | |
1363 | + n800_setup_nolo_tags(nolo_tags); | |
1364 | + cpu_physical_memory_write(OMAP2_SRAM_BASE, nolo_tags, 0x10000); | |
1363 | 1365 | } |
1364 | 1366 | /* FIXME: We shouldn't really be doing this here. The LCD controller |
1365 | 1367 | will set the size once configured, so this just sets an initial |
... | ... | @@ -1412,7 +1414,7 @@ QEMUMachine n800_machine = { |
1412 | 1414 | .name = "n800", |
1413 | 1415 | .desc = "Nokia N800 tablet aka. RX-34 (OMAP2420)", |
1414 | 1416 | .init = n800_init, |
1415 | - .ram_require = (0x08000000 + 0x00010000 + OMAP242X_SRAM_SIZE) | | |
1417 | + .ram_require = (0x08000000 + 0x00018000 + OMAP242X_SRAM_SIZE) | | |
1416 | 1418 | RAMSIZE_FIXED, |
1417 | 1419 | }; |
1418 | 1420 | |
... | ... | @@ -1420,6 +1422,6 @@ QEMUMachine n810_machine = { |
1420 | 1422 | .name = "n810", |
1421 | 1423 | .desc = "Nokia N810 tablet aka. RX-44 (OMAP2420)", |
1422 | 1424 | .init = n810_init, |
1423 | - .ram_require = (0x08000000 + 0x00010000 + OMAP242X_SRAM_SIZE) | | |
1425 | + .ram_require = (0x08000000 + 0x00018000 + OMAP242X_SRAM_SIZE) | | |
1424 | 1426 | RAMSIZE_FIXED, |
1425 | 1427 | }; | ... | ... |
hw/omap_dss.c
... | ... | @@ -582,25 +582,6 @@ static CPUWriteMemoryFunc *omap_disc1_writefn[] = { |
582 | 582 | omap_disc_write, |
583 | 583 | }; |
584 | 584 | |
585 | -static void *omap_rfbi_get_buffer(struct omap_dss_s *s) | |
586 | -{ | |
587 | - target_phys_addr_t fb; | |
588 | - uint32_t pd; | |
589 | - | |
590 | - /* TODO */ | |
591 | - fb = s->dispc.l[0].addr[0]; | |
592 | - | |
593 | - pd = cpu_get_physical_page_desc(fb); | |
594 | - if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) | |
595 | - /* TODO */ | |
596 | - cpu_abort(cpu_single_env, "%s: framebuffer outside RAM!\n", | |
597 | - __FUNCTION__); | |
598 | - else | |
599 | - return phys_ram_base + | |
600 | - (pd & TARGET_PAGE_MASK) + | |
601 | - (fb & ~TARGET_PAGE_MASK); | |
602 | -} | |
603 | - | |
604 | 585 | static void omap_rfbi_transfer_stop(struct omap_dss_s *s) |
605 | 586 | { |
606 | 587 | if (!s->rfbi.busy) |
... | ... | @@ -614,8 +595,11 @@ static void omap_rfbi_transfer_stop(struct omap_dss_s *s) |
614 | 595 | static void omap_rfbi_transfer_start(struct omap_dss_s *s) |
615 | 596 | { |
616 | 597 | void *data; |
617 | - size_t len; | |
598 | + target_phys_addr_t len; | |
599 | + target_phys_addr_t data_addr; | |
618 | 600 | int pitch; |
601 | + static void *bounce_buffer; | |
602 | + static target_phys_addr_t bounce_len; | |
619 | 603 | |
620 | 604 | if (!s->rfbi.enable || s->rfbi.busy) |
621 | 605 | return; |
... | ... | @@ -633,10 +617,24 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s) |
633 | 617 | |
634 | 618 | s->rfbi.busy = 1; |
635 | 619 | |
636 | - data = omap_rfbi_get_buffer(s); | |
620 | + len = s->rfbi.pixels * 2; | |
621 | + | |
622 | + data_addr = s->dispc.l[0].addr[0]; | |
623 | + data = cpu_physical_memory_map(data_addr, &len, 0); | |
624 | + if (data && len != s->rfbi.pixels * 2) { | |
625 | + cpu_physical_memory_unmap(data, len, 0, 0); | |
626 | + data = NULL; | |
627 | + len = s->rfbi.pixels * 2; | |
628 | + } | |
629 | + if (!data) { | |
630 | + if (len > bounce_len) { | |
631 | + bounce_buffer = qemu_realloc(bounce_buffer, len); | |
632 | + } | |
633 | + data = bounce_buffer; | |
634 | + cpu_physical_memory_read(data_addr, data, len); | |
635 | + } | |
637 | 636 | |
638 | 637 | /* TODO bpp */ |
639 | - len = s->rfbi.pixels * 2; | |
640 | 638 | s->rfbi.pixels = 0; |
641 | 639 | |
642 | 640 | /* TODO: negative values */ |
... | ... | @@ -647,6 +645,10 @@ static void omap_rfbi_transfer_start(struct omap_dss_s *s) |
647 | 645 | if ((s->rfbi.control & (1 << 3)) && s->rfbi.chip[1]) |
648 | 646 | s->rfbi.chip[1]->block(s->rfbi.chip[1]->opaque, 1, data, len, pitch); |
649 | 647 | |
648 | + if (data != bounce_buffer) { | |
649 | + cpu_physical_memory_unmap(data, len, 0, len); | |
650 | + } | |
651 | + | |
650 | 652 | omap_rfbi_transfer_stop(s); |
651 | 653 | |
652 | 654 | /* TODO */ | ... | ... |
hw/onenand.c
... | ... | @@ -642,7 +642,7 @@ void *onenand_init(uint32_t id, int regshift, qemu_irq irq) |
642 | 642 | s->otp = memset(qemu_malloc((64 + 2) << PAGE_SHIFT), |
643 | 643 | 0xff, (64 + 2) << PAGE_SHIFT); |
644 | 644 | s->ram = qemu_ram_alloc(0xc000 << s->shift); |
645 | - ram = phys_ram_base + s->ram; | |
645 | + ram = qemu_get_ram_ptr(s->ram); | |
646 | 646 | s->boot[0] = ram + (0x0000 << s->shift); |
647 | 647 | s->boot[1] = ram + (0x8000 << s->shift); |
648 | 648 | s->data[0][0] = ram + ((0x0200 + (0 << (PAGE_SHIFT - 1))) << s->shift); | ... | ... |
hw/pflash_cfi01.c
... | ... | @@ -519,7 +519,8 @@ pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off, |
519 | 519 | |
520 | 520 | pfl = qemu_mallocz(sizeof(pflash_t)); |
521 | 521 | |
522 | - pfl->storage = phys_ram_base + off; | |
522 | + /* FIXME: Allocate ram ourselves. */ | |
523 | + pfl->storage = qemu_get_ram_ptr(off); | |
523 | 524 | pfl->fl_mem = cpu_register_io_memory(0, |
524 | 525 | pflash_read_ops, pflash_write_ops, pfl); |
525 | 526 | pfl->off = off; | ... | ... |
hw/pflash_cfi02.c
... | ... | @@ -557,7 +557,8 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, |
557 | 557 | return NULL; |
558 | 558 | #endif |
559 | 559 | pfl = qemu_mallocz(sizeof(pflash_t)); |
560 | - pfl->storage = phys_ram_base + off; | |
560 | + /* FIXME: Allocate ram ourselves. */ | |
561 | + pfl->storage = qemu_get_ram_ptr(off); | |
561 | 562 | pfl->fl_mem = cpu_register_io_memory(0, pflash_read_ops, pflash_write_ops, |
562 | 563 | pfl); |
563 | 564 | pfl->off = off; | ... | ... |
hw/ppc.c
... | ... | @@ -1257,7 +1257,7 @@ int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size, |
1257 | 1257 | NVRAM_set_lword(nvram, 0x3C, kernel_size); |
1258 | 1258 | if (cmdline) { |
1259 | 1259 | /* XXX: put the cmdline in NVRAM too ? */ |
1260 | - strcpy((char *)(phys_ram_base + CMDLINE_ADDR), cmdline); | |
1260 | + pstrcpy_targphys(CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, cmdline); | |
1261 | 1261 | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR); |
1262 | 1262 | NVRAM_set_lword(nvram, 0x44, strlen(cmdline)); |
1263 | 1263 | } else { | ... | ... |
hw/ppc405.h
... | ... | @@ -78,7 +78,7 @@ void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio, |
78 | 78 | target_phys_addr_t offset, qemu_irq irq, |
79 | 79 | CharDriverState *chr); |
80 | 80 | /* On Chip Memory */ |
81 | -void ppc405_ocm_init (CPUState *env, unsigned long offset); | |
81 | +void ppc405_ocm_init (CPUState *env); | |
82 | 82 | /* I2C controller */ |
83 | 83 | void ppc405_i2c_init (CPUState *env, ppc4xx_mmio_t *mmio, |
84 | 84 | target_phys_addr_t offset, qemu_irq irq); |
... | ... | @@ -91,11 +91,11 @@ void ppc405_mal_init (CPUState *env, qemu_irq irqs[4]); |
91 | 91 | CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], |
92 | 92 | target_phys_addr_t ram_sizes[4], |
93 | 93 | uint32_t sysclk, qemu_irq **picp, |
94 | - ram_addr_t *offsetp, int do_init); | |
94 | + int do_init); | |
95 | 95 | CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], |
96 | 96 | target_phys_addr_t ram_sizes[2], |
97 | 97 | uint32_t sysclk, qemu_irq **picp, |
98 | - ram_addr_t *offsetp, int do_init); | |
98 | + int do_init); | |
99 | 99 | /* IBM STBxxx microcontrollers */ |
100 | 100 | CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2], |
101 | 101 | target_phys_addr_t ram_sizes[2], | ... | ... |
hw/ppc405_boards.c
... | ... | @@ -192,7 +192,7 @@ static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size, |
192 | 192 | int index; |
193 | 193 | |
194 | 194 | /* XXX: fix this */ |
195 | - ram_bases[0] = 0x00000000; | |
195 | + ram_bases[0] = qemu_ram_alloc(0x08000000); | |
196 | 196 | ram_sizes[0] = 0x08000000; |
197 | 197 | ram_bases[1] = 0x00000000; |
198 | 198 | ram_sizes[1] = 0x00000000; |
... | ... | @@ -200,25 +200,26 @@ static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size, |
200 | 200 | #ifdef DEBUG_BOARD_INIT |
201 | 201 | printf("%s: register cpu\n", __func__); |
202 | 202 | #endif |
203 | - env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &sram_offset, | |
203 | + env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, | |
204 | 204 | kernel_filename == NULL ? 0 : 1); |
205 | 205 | /* allocate SRAM */ |
206 | + sram_size = 512 * 1024; | |
207 | + sram_offset = qemu_ram_alloc(sram_size); | |
206 | 208 | #ifdef DEBUG_BOARD_INIT |
207 | 209 | printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset); |
208 | 210 | #endif |
209 | - sram_size = 512 * 1024; | |
210 | 211 | cpu_register_physical_memory(0xFFF00000, sram_size, |
211 | 212 | sram_offset | IO_MEM_RAM); |
212 | 213 | /* allocate and load BIOS */ |
213 | 214 | #ifdef DEBUG_BOARD_INIT |
214 | 215 | printf("%s: register BIOS\n", __func__); |
215 | 216 | #endif |
216 | - bios_offset = sram_offset + sram_size; | |
217 | 217 | fl_idx = 0; |
218 | 218 | #ifdef USE_FLASH_BIOS |
219 | 219 | index = drive_get_index(IF_PFLASH, 0, fl_idx); |
220 | 220 | if (index != -1) { |
221 | 221 | bios_size = bdrv_getlength(drives_table[index].bdrv); |
222 | + bios_offset = qemu_ram_alloc(bios_size); | |
222 | 223 | fl_sectors = (bios_size + 65535) >> 16; |
223 | 224 | #ifdef DEBUG_BOARD_INIT |
224 | 225 | printf("Register parallel flash %d size " ADDRX " at offset %08lx " |
... | ... | @@ -239,7 +240,8 @@ static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size, |
239 | 240 | if (bios_name == NULL) |
240 | 241 | bios_name = BIOS_FILENAME; |
241 | 242 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
242 | - bios_size = load_image(buf, phys_ram_base + bios_offset); | |
243 | + bios_offset = qemu_ram_alloc(BIOS_SIZE); | |
244 | + bios_size = load_image(buf, qemu_get_ram_ptr(bios_offset)); | |
243 | 245 | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
244 | 246 | fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf); |
245 | 247 | exit(1); |
... | ... | @@ -248,7 +250,6 @@ static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size, |
248 | 250 | cpu_register_physical_memory((uint32_t)(-bios_size), |
249 | 251 | bios_size, bios_offset | IO_MEM_ROM); |
250 | 252 | } |
251 | - bios_offset += bios_size; | |
252 | 253 | /* Register FPGA */ |
253 | 254 | #ifdef DEBUG_BOARD_INIT |
254 | 255 | printf("%s: register FPGA\n", __func__); |
... | ... | @@ -294,23 +295,20 @@ static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size, |
294 | 295 | env->gpr[3] = bdloc; |
295 | 296 | kernel_base = KERNEL_LOAD_ADDR; |
296 | 297 | /* now we can load the kernel */ |
297 | - kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); | |
298 | + kernel_size = load_image_targphys(kernel_filename, kernel_base, | |
299 | + ram_size - kernel_base); | |
298 | 300 | if (kernel_size < 0) { |
299 | 301 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
300 | 302 | kernel_filename); |
301 | 303 | exit(1); |
302 | 304 | } |
303 | - printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx | |
304 | - " %02x %02x %02x %02x\n", kernel_size, kernel_base, | |
305 | - *(char *)(phys_ram_base + kernel_base), | |
306 | - *(char *)(phys_ram_base + kernel_base + 1), | |
307 | - *(char *)(phys_ram_base + kernel_base + 2), | |
308 | - *(char *)(phys_ram_base + kernel_base + 3)); | |
305 | + printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx, | |
306 | + kernel_size, kernel_base); | |
309 | 307 | /* load initrd */ |
310 | 308 | if (initrd_filename) { |
311 | 309 | initrd_base = INITRD_LOAD_ADDR; |
312 | - initrd_size = load_image(initrd_filename, | |
313 | - phys_ram_base + initrd_base); | |
310 | + initrd_size = load_image_targphys(initrd_filename, initrd_base, | |
311 | + ram_size - initrd_base); | |
314 | 312 | if (initrd_size < 0) { |
315 | 313 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", |
316 | 314 | initrd_filename); |
... | ... | @@ -326,7 +324,7 @@ static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size, |
326 | 324 | if (kernel_cmdline != NULL) { |
327 | 325 | len = strlen(kernel_cmdline); |
328 | 326 | bdloc -= ((len + 255) & ~255); |
329 | - memcpy(phys_ram_base + bdloc, kernel_cmdline, len + 1); | |
327 | + cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1); | |
330 | 328 | env->gpr[6] = bdloc; |
331 | 329 | env->gpr[7] = bdloc + len; |
332 | 330 | } else { |
... | ... | @@ -344,8 +342,7 @@ static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size, |
344 | 342 | #ifdef DEBUG_BOARD_INIT |
345 | 343 | printf("%s: Done\n", __func__); |
346 | 344 | #endif |
347 | - printf("bdloc %016lx %s\n", | |
348 | - (unsigned long)bdloc, (char *)(phys_ram_base + bdloc)); | |
345 | + printf("bdloc %016lx\n", (unsigned long)bdloc); | |
349 | 346 | } |
350 | 347 | |
351 | 348 | QEMUMachine ref405ep_machine = { |
... | ... | @@ -511,14 +508,14 @@ static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size, |
511 | 508 | int index; |
512 | 509 | |
513 | 510 | /* RAM is soldered to the board so the size cannot be changed */ |
514 | - ram_bases[0] = 0x00000000; | |
511 | + ram_bases[0] = qemu_ram_alloc(0x04000000); | |
515 | 512 | ram_sizes[0] = 0x04000000; |
516 | - ram_bases[1] = 0x04000000; | |
513 | + ram_bases[1] = qemu_ram_alloc(0x04000000); | |
517 | 514 | ram_sizes[1] = 0x04000000; |
518 | 515 | #ifdef DEBUG_BOARD_INIT |
519 | 516 | printf("%s: register cpu\n", __func__); |
520 | 517 | #endif |
521 | - env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, &bios_offset, | |
518 | + env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic, | |
522 | 519 | kernel_filename == NULL ? 0 : 1); |
523 | 520 | /* allocate and load BIOS */ |
524 | 521 | #ifdef DEBUG_BOARD_INIT |
... | ... | @@ -532,6 +529,7 @@ static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size, |
532 | 529 | /* XXX: should check that size is 2MB */ |
533 | 530 | // bios_size = 2 * 1024 * 1024; |
534 | 531 | fl_sectors = (bios_size + 65535) >> 16; |
532 | + bios_offset = qemu_ram_alloc(bios_size); | |
535 | 533 | #ifdef DEBUG_BOARD_INIT |
536 | 534 | printf("Register parallel flash %d size " ADDRX " at offset %08lx " |
537 | 535 | " addr " ADDRX " '%s' %d\n", |
... | ... | @@ -550,8 +548,9 @@ static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size, |
550 | 548 | #endif |
551 | 549 | if (bios_name == NULL) |
552 | 550 | bios_name = BIOS_FILENAME; |
551 | + bios_offset = qemu_ram_alloc(BIOS_SIZE); | |
553 | 552 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
554 | - bios_size = load_image(buf, phys_ram_base + bios_offset); | |
553 | + bios_size = load_image(buf, qemu_get_ram_ptr(bios_offset)); | |
555 | 554 | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
556 | 555 | fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf); |
557 | 556 | exit(1); |
... | ... | @@ -560,7 +559,6 @@ static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size, |
560 | 559 | cpu_register_physical_memory((uint32_t)(-bios_size), |
561 | 560 | bios_size, bios_offset | IO_MEM_ROM); |
562 | 561 | } |
563 | - bios_offset += bios_size; | |
564 | 562 | /* Register Linux flash */ |
565 | 563 | index = drive_get_index(IF_PFLASH, 0, fl_idx); |
566 | 564 | if (index != -1) { |
... | ... | @@ -574,6 +572,7 @@ static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size, |
574 | 572 | fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000, |
575 | 573 | bdrv_get_device_name(drives_table[index].bdrv)); |
576 | 574 | #endif |
575 | + bios_offset = qemu_ram_alloc(bios_size); | |
577 | 576 | pflash_cfi02_register(0xfc000000, bios_offset, |
578 | 577 | drives_table[index].bdrv, 65536, fl_sectors, 1, |
579 | 578 | 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA); |
... | ... | @@ -592,7 +591,8 @@ static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size, |
592 | 591 | #endif |
593 | 592 | kernel_base = KERNEL_LOAD_ADDR; |
594 | 593 | /* now we can load the kernel */ |
595 | - kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); | |
594 | + kernel_size = load_image_targphys(kernel_filename, kernel_base, | |
595 | + ram_size - kernel_base); | |
596 | 596 | if (kernel_size < 0) { |
597 | 597 | fprintf(stderr, "qemu: could not load kernel '%s'\n", |
598 | 598 | kernel_filename); |
... | ... | @@ -601,8 +601,8 @@ static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size, |
601 | 601 | /* load initrd */ |
602 | 602 | if (initrd_filename) { |
603 | 603 | initrd_base = INITRD_LOAD_ADDR; |
604 | - initrd_size = load_image(initrd_filename, | |
605 | - phys_ram_base + initrd_base); | |
604 | + initrd_size = load_image_targphys(initrd_filename, initrd_base, | |
605 | + ram_size - initrd_base); | |
606 | 606 | if (initrd_size < 0) { |
607 | 607 | fprintf(stderr, |
608 | 608 | "qemu: could not load initial ram disk '%s'\n", | ... | ... |
hw/ppc405_uc.c
... | ... | @@ -51,38 +51,38 @@ ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd, |
51 | 51 | bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t); |
52 | 52 | else |
53 | 53 | bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t); |
54 | - stl_raw(phys_ram_base + bdloc + 0x00, bd->bi_memstart); | |
55 | - stl_raw(phys_ram_base + bdloc + 0x04, bd->bi_memsize); | |
56 | - stl_raw(phys_ram_base + bdloc + 0x08, bd->bi_flashstart); | |
57 | - stl_raw(phys_ram_base + bdloc + 0x0C, bd->bi_flashsize); | |
58 | - stl_raw(phys_ram_base + bdloc + 0x10, bd->bi_flashoffset); | |
59 | - stl_raw(phys_ram_base + bdloc + 0x14, bd->bi_sramstart); | |
60 | - stl_raw(phys_ram_base + bdloc + 0x18, bd->bi_sramsize); | |
61 | - stl_raw(phys_ram_base + bdloc + 0x1C, bd->bi_bootflags); | |
62 | - stl_raw(phys_ram_base + bdloc + 0x20, bd->bi_ipaddr); | |
54 | + stl_phys(bdloc + 0x00, bd->bi_memstart); | |
55 | + stl_phys(bdloc + 0x04, bd->bi_memsize); | |
56 | + stl_phys(bdloc + 0x08, bd->bi_flashstart); | |
57 | + stl_phys(bdloc + 0x0C, bd->bi_flashsize); | |
58 | + stl_phys(bdloc + 0x10, bd->bi_flashoffset); | |
59 | + stl_phys(bdloc + 0x14, bd->bi_sramstart); | |
60 | + stl_phys(bdloc + 0x18, bd->bi_sramsize); | |
61 | + stl_phys(bdloc + 0x1C, bd->bi_bootflags); | |
62 | + stl_phys(bdloc + 0x20, bd->bi_ipaddr); | |
63 | 63 | for (i = 0; i < 6; i++) |
64 | - stb_raw(phys_ram_base + bdloc + 0x24 + i, bd->bi_enetaddr[i]); | |
65 | - stw_raw(phys_ram_base + bdloc + 0x2A, bd->bi_ethspeed); | |
66 | - stl_raw(phys_ram_base + bdloc + 0x2C, bd->bi_intfreq); | |
67 | - stl_raw(phys_ram_base + bdloc + 0x30, bd->bi_busfreq); | |
68 | - stl_raw(phys_ram_base + bdloc + 0x34, bd->bi_baudrate); | |
64 | + stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]); | |
65 | + stw_phys(bdloc + 0x2A, bd->bi_ethspeed); | |
66 | + stl_phys(bdloc + 0x2C, bd->bi_intfreq); | |
67 | + stl_phys(bdloc + 0x30, bd->bi_busfreq); | |
68 | + stl_phys(bdloc + 0x34, bd->bi_baudrate); | |
69 | 69 | for (i = 0; i < 4; i++) |
70 | - stb_raw(phys_ram_base + bdloc + 0x38 + i, bd->bi_s_version[i]); | |
70 | + stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]); | |
71 | 71 | for (i = 0; i < 32; i++) |
72 | - stb_raw(phys_ram_base + bdloc + 0x3C + i, bd->bi_s_version[i]); | |
73 | - stl_raw(phys_ram_base + bdloc + 0x5C, bd->bi_plb_busfreq); | |
74 | - stl_raw(phys_ram_base + bdloc + 0x60, bd->bi_pci_busfreq); | |
72 | + stb_phys(bdloc + 0x3C + i, bd->bi_s_version[i]); | |
73 | + stl_phys(bdloc + 0x5C, bd->bi_plb_busfreq); | |
74 | + stl_phys(bdloc + 0x60, bd->bi_pci_busfreq); | |
75 | 75 | for (i = 0; i < 6; i++) |
76 | - stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); | |
76 | + stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]); | |
77 | 77 | n = 0x6A; |
78 | 78 | if (flags & 0x00000001) { |
79 | 79 | for (i = 0; i < 6; i++) |
80 | - stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]); | |
80 | + stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]); | |
81 | 81 | } |
82 | - stl_raw(phys_ram_base + bdloc + n, bd->bi_opbfreq); | |
82 | + stl_phys(bdloc + n, bd->bi_opbfreq); | |
83 | 83 | n += 4; |
84 | 84 | for (i = 0; i < 2; i++) { |
85 | - stl_raw(phys_ram_base + bdloc + n, bd->bi_iic_fast[i]); | |
85 | + stl_phys(bdloc + n, bd->bi_iic_fast[i]); | |
86 | 86 | n += 4; |
87 | 87 | } |
88 | 88 | |
... | ... | @@ -1021,12 +1021,12 @@ static void ocm_reset (void *opaque) |
1021 | 1021 | ocm->dsacntl = dsacntl; |
1022 | 1022 | } |
1023 | 1023 | |
1024 | -void ppc405_ocm_init (CPUState *env, unsigned long offset) | |
1024 | +void ppc405_ocm_init (CPUState *env) | |
1025 | 1025 | { |
1026 | 1026 | ppc405_ocm_t *ocm; |
1027 | 1027 | |
1028 | 1028 | ocm = qemu_mallocz(sizeof(ppc405_ocm_t)); |
1029 | - ocm->offset = offset; | |
1029 | + ocm->offset = qemu_ram_alloc(4096); | |
1030 | 1030 | ocm_reset(ocm); |
1031 | 1031 | qemu_register_reset(&ocm_reset, ocm); |
1032 | 1032 | ppc_dcr_register(env, OCM0_ISARC, |
... | ... | @@ -2178,15 +2178,13 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], |
2178 | 2178 | CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], |
2179 | 2179 | target_phys_addr_t ram_sizes[4], |
2180 | 2180 | uint32_t sysclk, qemu_irq **picp, |
2181 | - ram_addr_t *offsetp, int do_init) | |
2181 | + int do_init) | |
2182 | 2182 | { |
2183 | 2183 | clk_setup_t clk_setup[PPC405CR_CLK_NB]; |
2184 | 2184 | qemu_irq dma_irqs[4]; |
2185 | 2185 | CPUState *env; |
2186 | 2186 | ppc4xx_mmio_t *mmio; |
2187 | 2187 | qemu_irq *pic, *irqs; |
2188 | - ram_addr_t offset; | |
2189 | - int i; | |
2190 | 2188 | |
2191 | 2189 | memset(clk_setup, 0, sizeof(clk_setup)); |
2192 | 2190 | env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK], |
... | ... | @@ -2209,9 +2207,6 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], |
2209 | 2207 | *picp = pic; |
2210 | 2208 | /* SDRAM controller */ |
2211 | 2209 | ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); |
2212 | - offset = 0; | |
2213 | - for (i = 0; i < 4; i++) | |
2214 | - offset += ram_sizes[i]; | |
2215 | 2210 | /* External bus controller */ |
2216 | 2211 | ppc405_ebc_init(env); |
2217 | 2212 | /* DMA controller */ |
... | ... | @@ -2233,7 +2228,6 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], |
2233 | 2228 | ppc405_gpio_init(env, mmio, 0x700); |
2234 | 2229 | /* CPU control */ |
2235 | 2230 | ppc405cr_cpc_init(env, clk_setup, sysclk); |
2236 | - *offsetp = offset; | |
2237 | 2231 | |
2238 | 2232 | return env; |
2239 | 2233 | } |
... | ... | @@ -2529,15 +2523,13 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], |
2529 | 2523 | CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], |
2530 | 2524 | target_phys_addr_t ram_sizes[2], |
2531 | 2525 | uint32_t sysclk, qemu_irq **picp, |
2532 | - ram_addr_t *offsetp, int do_init) | |
2526 | + int do_init) | |
2533 | 2527 | { |
2534 | 2528 | clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup; |
2535 | 2529 | qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4]; |
2536 | 2530 | CPUState *env; |
2537 | 2531 | ppc4xx_mmio_t *mmio; |
2538 | 2532 | qemu_irq *pic, *irqs; |
2539 | - ram_addr_t offset; | |
2540 | - int i; | |
2541 | 2533 | |
2542 | 2534 | memset(clk_setup, 0, sizeof(clk_setup)); |
2543 | 2535 | /* init CPUs */ |
... | ... | @@ -2565,9 +2557,6 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], |
2565 | 2557 | /* SDRAM controller */ |
2566 | 2558 | /* XXX 405EP has no ECC interrupt */ |
2567 | 2559 | ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); |
2568 | - offset = 0; | |
2569 | - for (i = 0; i < 2; i++) | |
2570 | - offset += ram_sizes[i]; | |
2571 | 2560 | /* External bus controller */ |
2572 | 2561 | ppc405_ebc_init(env); |
2573 | 2562 | /* DMA controller */ |
... | ... | @@ -2588,8 +2577,7 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], |
2588 | 2577 | ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]); |
2589 | 2578 | } |
2590 | 2579 | /* OCM */ |
2591 | - ppc405_ocm_init(env, ram_sizes[0] + ram_sizes[1]); | |
2592 | - offset += 4096; | |
2580 | + ppc405_ocm_init(env); | |
2593 | 2581 | /* GPT */ |
2594 | 2582 | gpt_irqs[0] = pic[19]; |
2595 | 2583 | gpt_irqs[1] = pic[20]; |
... | ... | @@ -2609,7 +2597,6 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], |
2609 | 2597 | /* Uses pic[9], pic[15], pic[17] */ |
2610 | 2598 | /* CPU control */ |
2611 | 2599 | ppc405ep_cpc_init(env, clk_setup, sysclk); |
2612 | - *offsetp = offset; | |
2613 | 2600 | |
2614 | 2601 | return env; |
2615 | 2602 | } | ... | ... |
hw/ppc4xx_devs.c
... | ... | @@ -855,7 +855,7 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, |
855 | 855 | target_phys_addr_t ram_sizes[], |
856 | 856 | const unsigned int sdram_bank_sizes[]) |
857 | 857 | { |
858 | - ram_addr_t ram_end = 0; | |
858 | + ram_addr_t size_left = ram_size; | |
859 | 859 | int i; |
860 | 860 | int j; |
861 | 861 | |
... | ... | @@ -863,24 +863,24 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, |
863 | 863 | for (j = 0; sdram_bank_sizes[j] != 0; j++) { |
864 | 864 | unsigned int bank_size = sdram_bank_sizes[j]; |
865 | 865 | |
866 | - if (bank_size <= ram_size) { | |
867 | - ram_bases[i] = ram_end; | |
866 | + if (bank_size <= size_left) { | |
867 | + ram_bases[i] = qemu_ram_alloc(bank_size); | |
868 | 868 | ram_sizes[i] = bank_size; |
869 | - ram_end += bank_size; | |
870 | - ram_size -= bank_size; | |
869 | + size_left -= bank_size; | |
871 | 870 | break; |
872 | 871 | } |
873 | 872 | } |
874 | 873 | |
875 | - if (!ram_size) { | |
874 | + if (!size_left) { | |
876 | 875 | /* No need to use the remaining banks. */ |
877 | 876 | break; |
878 | 877 | } |
879 | 878 | } |
880 | 879 | |
880 | + ram_size -= size_left; | |
881 | 881 | if (ram_size) |
882 | 882 | printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n", |
883 | - (int)(ram_end >> 20)); | |
883 | + (int)(ram_size >> 20)); | |
884 | 884 | |
885 | - return ram_end; | |
885 | + return ram_size; | |
886 | 886 | } | ... | ... |
hw/soc_dma.h
... | ... | @@ -110,5 +110,5 @@ static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma, |
110 | 110 | static inline void soc_dma_port_add_mem_ram(struct soc_dma_s *dma, |
111 | 111 | ram_addr_t offset, target_phys_addr_t virt_base, size_t size) |
112 | 112 | { |
113 | - return soc_dma_port_add_mem(dma, phys_ram_base + offset, virt_base, size); | |
113 | + return soc_dma_port_add_mem(dma, qemu_get_ram_ptr(offset), virt_base, size); | |
114 | 114 | } | ... | ... |
hw/virtio-balloon.c
... | ... | @@ -94,7 +94,9 @@ static void virtio_balloon_handle_output(VirtIODevice *vdev, VirtQueue *vq) |
94 | 94 | if ((addr & ~TARGET_PAGE_MASK) != IO_MEM_RAM) |
95 | 95 | continue; |
96 | 96 | |
97 | - balloon_page(phys_ram_base + addr, !!(vq == s->dvq)); | |
97 | + /* Using qemu_get_ram_ptr is bending the rules a bit, but | |
98 | + should be OK because we only want a single page. */ | |
99 | + balloon_page(qemu_get_ram_ptr(addr), !!(vq == s->dvq)); | |
98 | 100 | } |
99 | 101 | |
100 | 102 | virtqueue_push(vq, &elem, offset); | ... | ... |