• This reverts commit 8217606e (and
    updates later added users of qemu_register_reset), we solved the
    problem it originally addressed less invasively.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Jan Kiszka authored
     
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  • During startup and after reset we have to synchronize user space to the
    in-kernel KVM state. Namely, we need to transfer the VCPU registers when
    they change due to VCPU as well as APIC reset.
    
    This patch refactors the required hooks so that kvm_init_vcpu registers
    its own per-VCPU reset handler and adds a cpu_synchronize_state to the
    APIC reset. That way we no longer depend on the new reset order (and can
    drop this disliked interface again) and we can even drop a KVM hook in
    main().
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Jan Kiszka authored
     
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  • Implement MSI support in APIC. Note that MSI and MMIO APIC registers
    are at the same memory location, but actually not on the global bus: MSI
    is on PCI bus, APIC is connected directly to the CPU. We map them on the
    global bus at the same address which happens to work because MSI
    registers are reserved in APIC MMIO and vice versa.
    
    Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Michael S. Tsirkin authored
     
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  • This should fix compilation problem in case of CONFIG_USER_ONLY.
    
    Currently INIT/SIPI is handled in the context of CPU that sends IPI.
    This patch changes this to handle them like all other events in a main
    cpu exec loop. When KVM will gain thread per vcpu capability it will
    be much more clear to handle those event by cpu thread itself and not
    modify one cpu's state from the context of the other.
    
    Signed-off-by: Gleb Natapov <gleb@redhat.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Gleb Natapov authored
     
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  • (patch is on top of "Apic creation should not depend on pci" series)
    
    Currently cpu_index is used as cpu apic id on x86.  This is incorrect
    since apic ids not have to be continuous (they can also encode cpu
    hierarchy information). This patch uses cpuid_apic_id for initial apic id
    value. For now cpuid_apic_id is set to be equal to cpu_index so behaviour
    is fully backward compatible, but it allows us to add qemu option to
    provide other values for cpu apic id.
    
    Signed-off-by: Gleb Natapov <gleb@redhat.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Gleb Natapov authored
     
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  • Add the parameter 'order' to qemu_register_reset and sort callbacks on
    registration. On system reset, callbacks with lower order will be
    invoked before those with higher order. Update all existing users to the
    standard order 0.
    
    Note: At least for x86, the existing users seem to assume that handlers
    are called in their registration order. Therefore, the patch preserves
    this property. If someone feels bored, (s)he could try to identify this
    dependency and express it properly on callback registration.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Jan Kiszka authored
     
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  • From: Xiantao Zhang <xiantao.zhang@intel.com>
    Date: Tue, 3 Mar 2009 13:33:13 +0800
    Subject: [PATCH] Split ioapic logic from the current apic.
    
    Add a new ioapic.c to hold ioapic's logic, and also
    make it work for ia64.
    
    Signed-off-by: Xiantao Zhang <xiantao.zhang@intel.com>
    ---
     Makefile.target |    2 +-
     hw/apic.c       |  237 +++----------------------------------------------
     hw/ioapic.c     |  263 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
     hw/pc.h         |    5 +-
     4 files changed, 281 insertions(+), 226 deletions(-)
     create mode 100644 hw/ioapic.c
    
    
    git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6827 c046a42c-6fe2-441c-8c8c-71466251a162
    aliguori authored
     
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  • After my last patch to fix interrupt coalescing was rejected
    on the basis that it is too intrusive we decided to make the
    fix much more localized and only fix the problem for RTC time
    source. Unfortunately it is impossible to fix the problem entirely
    inside RTC code like Andrzej proposed since Windows reads RTC
    register C more then once on each time interrupt so it is impossible
    to count reliably how many interrupt windows actually handled.
    Proposed solution is localized to I386 target and is disabled by
    default. To enable it "-rtc-td-hack" flag should be used.
    
    Signed-off-by: Gleb Natapov <gleb@redhat.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    
    
    
    git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6320 c046a42c-6fe2-441c-8c8c-71466251a162
    aliguori authored
     
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  • [ Taking latest isapc changes into account. ]
    
    Ensure that PIC-delivered IRQs are properly de-asserted in case the APIC
    is in EXTINT or FIXED mode (with level-triggering selected) on LINT0.
    Fixes EFI-BIOS boot issues.
    
    This patch also cleans up a bit the interface between PIC and APIC,
    making apic_local_deliver private again.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
    Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
    
    git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5041 c046a42c-6fe2-441c-8c8c-71466251a162
    aurel32 authored
     
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