gwj / at91sam9263 · Commits

Commit 16b29ae1807b024bd5052301550f5d47dae958a2

Authored by aliguori
1 parent 0bacd130

Add HPET emulation to qemu (Beth Kon) 

This patch adds HPET emulation.  It can be disabled with -disable-hpet.  An hpet
provides a more finely granular clocksource than otherwise available on PC.
This means that latency-dependent applications (e.g. multimedia) will generally
be smoother when using the HPET.

Signed-off-by: Beth Kon <eak@us.ibm.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6081 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 13 changed files with 938 additions and 6 deletions
Makefile.target
  View file @16b29ae
... ... @@ -635,7 +635,7 @@ ifeq ($(TARGET_BASE_ARCH), i386)
635 635 OBJS+= ide.o pckbd.o ps2.o vga.o $(SOUND_HW) dma.o
636 636 OBJS+= fdc.o mc146818rtc.o serial.o i8259.o i8254.o pcspk.o pc.o
637 637 OBJS+= cirrus_vga.o apic.o parallel.o acpi.o piix_pci.o
638   -OBJS+= usb-uhci.o vmmouse.o vmport.o vmware_vga.o
  638 +OBJS+= usb-uhci.o vmmouse.o vmport.o vmware_vga.o hpet.o
639 639 # virtio support
640 640 OBJS+= virtio.o virtio-blk.o virtio-balloon.o virtio-net.o
641 641 CPPFLAGS += -DHAS_AUDIO -DHAS_AUDIO_CHOICE
... ...
hw/apic.c
  View file @16b29ae
... ... @@ -945,6 +945,13 @@ void ioapic_set_irq(void *opaque, int vector, int level)
945 945 {
946 946 IOAPICState *s = opaque;
947 947  
  948 + /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
  949 + * to GSI 2. GSI maps to ioapic 1-1. This is not
  950 + * the cleanest way of doing it but it should work. */
  951 +
  952 + if (vector == 0)
  953 + vector = 2;
  954 +
948 955 if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
949 956 uint32_t mask = 1 << vector;
950 957 uint64_t entry = s->ioredtbl[vector];
... ...
hw/hpet.c 0 → 100644
  View file @16b29ae
  1 +/*
  2 + * High Precisition Event Timer emulation
  3 + *
  4 + * Copyright (c) 2007 Alexander Graf
  5 + * Copyright (c) 2008 IBM Corporation
  6 + *
  7 + * Authors: Beth Kon <bkon@us.ibm.com>
  8 + *
  9 + * This library is free software; you can redistribute it and/or
  10 + * modify it under the terms of the GNU Lesser General Public
  11 + * License as published by the Free Software Foundation; either
  12 + * version 2 of the License, or (at your option) any later version.
  13 + *
  14 + * This library is distributed in the hope that it will be useful,
  15 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17 + * Lesser General Public License for more details.
  18 + *
  19 + * You should have received a copy of the GNU Lesser General Public
  20 + * License along with this library; if not, write to the Free Software
  21 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22 + *
  23 + * *****************************************************************
  24 + *
  25 + * This driver attempts to emulate an HPET device in software.
  26 + */
  27 +
  28 +#include "hw.h"
  29 +#include "console.h"
  30 +#include "qemu-timer.h"
  31 +#include "hpet_emul.h"
  32 +
  33 +extern void hpet_pit_disable(void);
  34 +extern void hpet_pit_enable(void);
  35 +
  36 +//#define HPET_DEBUG
  37 +#ifdef HPET_DEBUG
  38 +#define dprintf printf
  39 +#else
  40 +#define dprintf(...)
  41 +#endif
  42 +
  43 +static HPETState *hpet_statep;
  44 +
  45 +uint32_t hpet_in_legacy_mode(void)
  46 +{
  47 + if (hpet_statep)
  48 + return hpet_statep->config & HPET_CFG_LEGACY;
  49 + else
  50 + return 0;
  51 +}
  52 +
  53 +static uint32_t timer_int_route(struct HPETTimer *timer)
  54 +{
  55 + uint32_t route;
  56 + route = (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
  57 + return route;
  58 +}
  59 +
  60 +static uint32_t hpet_enabled(void)
  61 +{
  62 + return hpet_statep->config & HPET_CFG_ENABLE;
  63 +}
  64 +
  65 +static uint32_t timer_is_periodic(HPETTimer *t)
  66 +{
  67 + return t->config & HPET_TN_PERIODIC;
  68 +}
  69 +
  70 +static uint32_t timer_enabled(HPETTimer *t)
  71 +{
  72 + return t->config & HPET_TN_ENABLE;
  73 +}
  74 +
  75 +static uint32_t hpet_time_after(uint64_t a, uint64_t b)
  76 +{
  77 + return ((int32_t)(b) - (int32_t)(a) < 0);
  78 +}
  79 +
  80 +static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
  81 +{
  82 + return ((int64_t)(b) - (int64_t)(a) < 0);
  83 +}
  84 +
  85 +static uint64_t ticks_to_ns(uint64_t value)
  86 +{
  87 + return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
  88 +}
  89 +
  90 +static uint64_t ns_to_ticks(uint64_t value)
  91 +{
  92 + return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
  93 +}
  94 +
  95 +static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
  96 +{
  97 + new &= mask;
  98 + new |= old & ~mask;
  99 + return new;
  100 +}
  101 +
  102 +static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
  103 +{
  104 + return (!(old & mask) && (new & mask));
  105 +}
  106 +
  107 +static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
  108 +{
  109 + return ((old & mask) && !(new & mask));
  110 +}
  111 +
  112 +static uint64_t hpet_get_ticks(void)
  113 +{
  114 + uint64_t ticks;
  115 + ticks = ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset);
  116 + return ticks;
  117 +}
  118 +
  119 +/*
  120 + * calculate diff between comparator value and current ticks
  121 + */
  122 +static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
  123 +{
  124 +
  125 + if (t->config & HPET_TN_32BIT) {
  126 + uint32_t diff, cmp;
  127 + cmp = (uint32_t)t->cmp;
  128 + diff = cmp - (uint32_t)current;
  129 + diff = (int32_t)diff > 0 ? diff : (uint32_t)0;
  130 + return (uint64_t)diff;
  131 + } else {
  132 + uint64_t diff, cmp;
  133 + cmp = t->cmp;
  134 + diff = cmp - current;
  135 + diff = (int64_t)diff > 0 ? diff : (uint64_t)0;
  136 + return diff;
  137 + }
  138 +}
  139 +
  140 +static void update_irq(struct HPETTimer *timer)
  141 +{
  142 + qemu_irq irq;
  143 + int route;
  144 +
  145 + if (timer->tn <= 1 && hpet_in_legacy_mode()) {
  146 + /* if LegacyReplacementRoute bit is set, HPET specification requires
  147 + * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
  148 + * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
  149 + */
  150 + if (timer->tn == 0) {
  151 + irq=timer->state->irqs[0];
  152 + } else
  153 + irq=timer->state->irqs[8];
  154 + } else {
  155 + route=timer_int_route(timer);
  156 + irq=timer->state->irqs[route];
  157 + }
  158 + if (timer_enabled(timer) && hpet_enabled()) {
  159 + qemu_irq_pulse(irq);
  160 + }
  161 +}
  162 +
  163 +static void hpet_save(QEMUFile *f, void *opaque)
  164 +{
  165 + HPETState *s = opaque;
  166 + int i;
  167 + qemu_put_be64s(f, &s->config);
  168 + qemu_put_be64s(f, &s->isr);
  169 + /* save current counter value */
  170 + s->hpet_counter = hpet_get_ticks();
  171 + qemu_put_be64s(f, &s->hpet_counter);
  172 +
  173 + for (i = 0; i < HPET_NUM_TIMERS; i++) {
  174 + qemu_put_8s(f, &s->timer[i].tn);
  175 + qemu_put_be64s(f, &s->timer[i].config);
  176 + qemu_put_be64s(f, &s->timer[i].cmp);
  177 + qemu_put_be64s(f, &s->timer[i].fsb);
  178 + qemu_put_be64s(f, &s->timer[i].period);
  179 + qemu_put_8s(f, &s->timer[i].wrap_flag);
  180 + if (s->timer[i].qemu_timer) {
  181 + qemu_put_timer(f, s->timer[i].qemu_timer);
  182 + }
  183 + }
  184 +}
  185 +
  186 +static int hpet_load(QEMUFile *f, void *opaque, int version_id)
  187 +{
  188 + HPETState *s = opaque;
  189 + int i;
  190 +
  191 + if (version_id != 1)
  192 + return -EINVAL;
  193 +
  194 + qemu_get_be64s(f, &s->config);
  195 + qemu_get_be64s(f, &s->isr);
  196 + qemu_get_be64s(f, &s->hpet_counter);
  197 + /* Recalculate the offset between the main counter and guest time */
  198 + s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_get_clock(vm_clock);
  199 +
  200 + for (i = 0; i < HPET_NUM_TIMERS; i++) {
  201 + qemu_get_8s(f, &s->timer[i].tn);
  202 + qemu_get_be64s(f, &s->timer[i].config);
  203 + qemu_get_be64s(f, &s->timer[i].cmp);
  204 + qemu_get_be64s(f, &s->timer[i].fsb);
  205 + qemu_get_be64s(f, &s->timer[i].period);
  206 + qemu_get_8s(f, &s->timer[i].wrap_flag);
  207 + if (s->timer[i].qemu_timer) {
  208 + qemu_get_timer(f, s->timer[i].qemu_timer);
  209 + }
  210 + }
  211 + return 0;
  212 +}
  213 +
  214 +/*
  215 + * timer expiration callback
  216 + */
  217 +static void hpet_timer(void *opaque)
  218 +{
  219 + HPETTimer *t = (HPETTimer*)opaque;
  220 + uint64_t diff;
  221 +
  222 + uint64_t period = t->period;
  223 + uint64_t cur_tick = hpet_get_ticks();
  224 +
  225 + if (timer_is_periodic(t) && period != 0) {
  226 + if (t->config & HPET_TN_32BIT) {
  227 + while (hpet_time_after(cur_tick, t->cmp))
  228 + t->cmp = (uint32_t)(t->cmp + t->period);
  229 + } else
  230 + while (hpet_time_after64(cur_tick, t->cmp))
  231 + t->cmp += period;
  232 +
  233 + diff = hpet_calculate_diff(t, cur_tick);
  234 + qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
  235 + + (int64_t)ticks_to_ns(diff));
  236 + } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
  237 + if (t->wrap_flag) {
  238 + diff = hpet_calculate_diff(t, cur_tick);
  239 + qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
  240 + + (int64_t)ticks_to_ns(diff));
  241 + t->wrap_flag = 0;
  242 + }
  243 + }
  244 + update_irq(t);
  245 +}
  246 +
  247 +static void hpet_set_timer(HPETTimer *t)
  248 +{
  249 + uint64_t diff;
  250 + uint32_t wrap_diff; /* how many ticks until we wrap? */
  251 + uint64_t cur_tick = hpet_get_ticks();
  252 +
  253 + /* whenever new timer is being set up, make sure wrap_flag is 0 */
  254 + t->wrap_flag = 0;
  255 + diff = hpet_calculate_diff(t, cur_tick);
  256 +
  257 + /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
  258 + * counter wraps in addition to an interrupt with comparator match.
  259 + */
  260 + if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
  261 + wrap_diff = 0xffffffff - (uint32_t)cur_tick;
  262 + if (wrap_diff < (uint32_t)diff) {
  263 + diff = wrap_diff;
  264 + t->wrap_flag = 1;
  265 + }
  266 + }
  267 + qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
  268 + + (int64_t)ticks_to_ns(diff));
  269 +}
  270 +
  271 +static void hpet_del_timer(HPETTimer *t)
  272 +{
  273 + qemu_del_timer(t->qemu_timer);
  274 +}
  275 +
  276 +#ifdef HPET_DEBUG
  277 +static uint32_t hpet_ram_readb(void *opaque, target_phys_addr_t addr)
  278 +{
  279 + printf("qemu: hpet_read b at %" PRIx64 "\n", addr);
  280 + return 0;
  281 +}
  282 +
  283 +static uint32_t hpet_ram_readw(void *opaque, target_phys_addr_t addr)
  284 +{
  285 + printf("qemu: hpet_read w at %" PRIx64 "\n", addr);
  286 + return 0;
  287 +}
  288 +#endif
  289 +
  290 +static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
  291 +{
  292 + HPETState *s = (HPETState *)opaque;
  293 + uint64_t cur_tick, index;
  294 +
  295 + dprintf("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr);
  296 + index = addr;
  297 + /*address range of all TN regs*/
  298 + if (index >= 0x100 && index <= 0x3ff) {
  299 + uint8_t timer_id = (addr - 0x100) / 0x20;
  300 + if (timer_id > HPET_NUM_TIMERS - 1) {
  301 + printf("qemu: timer id out of range\n");
  302 + return 0;
  303 + }
  304 + HPETTimer *timer = &s->timer[timer_id];
  305 +
  306 + switch ((addr - 0x100) % 0x20) {
  307 + case HPET_TN_CFG:
  308 + return timer->config;
  309 + case HPET_TN_CFG + 4: // Interrupt capabilities
  310 + return timer->config >> 32;
  311 + case HPET_TN_CMP: // comparator register
  312 + return timer->cmp;
  313 + case HPET_TN_CMP + 4:
  314 + return timer->cmp >> 32;
  315 + case HPET_TN_ROUTE:
  316 + return timer->fsb >> 32;
  317 + default:
  318 + dprintf("qemu: invalid hpet_ram_readl\n");
  319 + break;
  320 + }
  321 + } else {
  322 + switch (index) {
  323 + case HPET_ID:
  324 + return s->capability;
  325 + case HPET_PERIOD:
  326 + return s->capability >> 32;
  327 + case HPET_CFG:
  328 + return s->config;
  329 + case HPET_CFG + 4:
  330 + dprintf("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
  331 + return 0;
  332 + case HPET_COUNTER:
  333 + if (hpet_enabled())
  334 + cur_tick = hpet_get_ticks();
  335 + else
  336 + cur_tick = s->hpet_counter;
  337 + dprintf("qemu: reading counter = %" PRIx64 "\n", cur_tick);
  338 + return cur_tick;
  339 + case HPET_COUNTER + 4:
  340 + if (hpet_enabled())
  341 + cur_tick = hpet_get_ticks();
  342 + else
  343 + cur_tick = s->hpet_counter;
  344 + dprintf("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick);
  345 + return cur_tick >> 32;
  346 + case HPET_STATUS:
  347 + return s->isr;
  348 + default:
  349 + dprintf("qemu: invalid hpet_ram_readl\n");
  350 + break;
  351 + }
  352 + }
  353 + return 0;
  354 +}
  355 +
  356 +#ifdef HPET_DEBUG
  357 +static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
  358 + uint32_t value)
  359 +{
  360 + printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
  361 + addr, value);
  362 +}
  363 +
  364 +static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
  365 + uint32_t value)
  366 +{
  367 + printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
  368 + addr, value);
  369 +}
  370 +#endif
  371 +
  372 +static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
  373 + uint32_t value)
  374 +{
  375 + int i;
  376 + HPETState *s = (HPETState *)opaque;
  377 + uint64_t old_val, new_val, index;
  378 +
  379 + dprintf("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value);
  380 + index = addr;
  381 + old_val = hpet_ram_readl(opaque, addr);
  382 + new_val = value;
  383 +
  384 + /*address range of all TN regs*/
  385 + if (index >= 0x100 && index <= 0x3ff) {
  386 + uint8_t timer_id = (addr - 0x100) / 0x20;
  387 + dprintf("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
  388 + HPETTimer *timer = &s->timer[timer_id];
  389 +
  390 + switch ((addr - 0x100) % 0x20) {
  391 + case HPET_TN_CFG:
  392 + dprintf("qemu: hpet_ram_writel HPET_TN_CFG\n");
  393 + timer->config = hpet_fixup_reg(new_val, old_val, 0x3e4e);
  394 + if (new_val & HPET_TN_32BIT) {
  395 + timer->cmp = (uint32_t)timer->cmp;
  396 + timer->period = (uint32_t)timer->period;
  397 + }
  398 + if (new_val & HPET_TIMER_TYPE_LEVEL) {
  399 + printf("qemu: level-triggered hpet not supported\n");
  400 + exit (-1);
  401 + }
  402 +
  403 + break;
  404 + case HPET_TN_CFG + 4: // Interrupt capabilities
  405 + dprintf("qemu: invalid HPET_TN_CFG+4 write\n");
  406 + break;
  407 + case HPET_TN_CMP: // comparator register
  408 + dprintf("qemu: hpet_ram_writel HPET_TN_CMP \n");
  409 + if (timer->config & HPET_TN_32BIT)
  410 + new_val = (uint32_t)new_val;
  411 + if (!timer_is_periodic(timer) ||
  412 + (timer->config & HPET_TN_SETVAL))
  413 + timer->cmp = (timer->cmp & 0xffffffff00000000ULL)
  414 + | new_val;
  415 + else {
  416 + /*
  417 + * FIXME: Clamp period to reasonable min value?
  418 + * Clamp period to reasonable max value
  419 + */
  420 + new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
  421 + timer->period = (timer->period & 0xffffffff00000000ULL)
  422 + | new_val;
  423 + }
  424 + timer->config &= ~HPET_TN_SETVAL;
  425 + if (hpet_enabled())
  426 + hpet_set_timer(timer);
  427 + break;
  428 + case HPET_TN_CMP + 4: // comparator register high order
  429 + dprintf("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
  430 + if (!timer_is_periodic(timer) ||
  431 + (timer->config & HPET_TN_SETVAL))
  432 + timer->cmp = (timer->cmp & 0xffffffffULL)
  433 + | new_val << 32;
  434 + else {
  435 + /*
  436 + * FIXME: Clamp period to reasonable min value?
  437 + * Clamp period to reasonable max value
  438 + */
  439 + new_val &= (timer->config
  440 + & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
  441 + timer->period = (timer->period & 0xffffffffULL)
  442 + | new_val << 32;
  443 + }
  444 + timer->config &= ~HPET_TN_SETVAL;
  445 + if (hpet_enabled())
  446 + hpet_set_timer(timer);
  447 + break;
  448 + case HPET_TN_ROUTE + 4:
  449 + dprintf("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
  450 + break;
  451 + default:
  452 + dprintf("qemu: invalid hpet_ram_writel\n");
  453 + break;
  454 + }
  455 + return;
  456 + } else {
  457 + switch (index) {
  458 + case HPET_ID:
  459 + return;
  460 + case HPET_CFG:
  461 + s->config = hpet_fixup_reg(new_val, old_val, 0x3);
  462 + if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
  463 + /* Enable main counter and interrupt generation. */
  464 + s->hpet_offset = ticks_to_ns(s->hpet_counter)
  465 + - qemu_get_clock(vm_clock);
  466 + for (i = 0; i < HPET_NUM_TIMERS; i++)
  467 + if ((&s->timer[i])->cmp != ~0ULL)
  468 + hpet_set_timer(&s->timer[i]);
  469 + }
  470 + else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
  471 + /* Halt main counter and disable interrupt generation. */
  472 + s->hpet_counter = hpet_get_ticks();
  473 + for (i = 0; i < HPET_NUM_TIMERS; i++)
  474 + hpet_del_timer(&s->timer[i]);
  475 + }
  476 + /* i8254 and RTC are disabled when HPET is in legacy mode */
  477 + if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
  478 + hpet_pit_disable();
  479 + } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) {
  480 + hpet_pit_enable();
  481 + }
  482 + break;
  483 + case HPET_CFG + 4:
  484 + dprintf("qemu: invalid HPET_CFG+4 write \n");
  485 + break;
  486 + case HPET_STATUS:
  487 + /* FIXME: need to handle level-triggered interrupts */
  488 + break;
  489 + case HPET_COUNTER:
  490 + if (hpet_enabled())
  491 + printf("qemu: Writing counter while HPET enabled!\n");
  492 + s->hpet_counter = (s->hpet_counter & 0xffffffff00000000ULL)
  493 + | value;
  494 + dprintf("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
  495 + value, s->hpet_counter);
  496 + break;
  497 + case HPET_COUNTER + 4:
  498 + if (hpet_enabled())
  499 + printf("qemu: Writing counter while HPET enabled!\n");
  500 + s->hpet_counter = (s->hpet_counter & 0xffffffffULL)
  501 + | (((uint64_t)value) << 32);
  502 + dprintf("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
  503 + value, s->hpet_counter);
  504 + break;
  505 + default:
  506 + dprintf("qemu: invalid hpet_ram_writel\n");
  507 + break;
  508 + }
  509 + }
  510 +}
  511 +
  512 +static CPUReadMemoryFunc *hpet_ram_read[] = {
  513 +#ifdef HPET_DEBUG
  514 + hpet_ram_readb,
  515 + hpet_ram_readw,
  516 +#else
  517 + NULL,
  518 + NULL,
  519 +#endif
  520 + hpet_ram_readl,
  521 +};
  522 +
  523 +static CPUWriteMemoryFunc *hpet_ram_write[] = {
  524 +#ifdef HPET_DEBUG
  525 + hpet_ram_writeb,
  526 + hpet_ram_writew,
  527 +#else
  528 + NULL,
  529 + NULL,
  530 +#endif
  531 + hpet_ram_writel,
  532 +};
  533 +
  534 +static void hpet_reset(void *opaque) {
  535 + HPETState *s = opaque;
  536 + int i;
  537 + static int count = 0;
  538 +
  539 + for (i=0; i<HPET_NUM_TIMERS; i++) {
  540 + HPETTimer *timer = &s->timer[i];
  541 + hpet_del_timer(timer);
  542 + timer->tn = i;
  543 + timer->cmp = ~0ULL;
  544 + timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP;
  545 + /* advertise availability of irqs 5,10,11 */
  546 + timer->config |= 0x00000c20ULL << 32;
  547 + timer->state = s;
  548 + timer->period = 0ULL;
  549 + timer->wrap_flag = 0;
  550 + }
  551 +
  552 + s->hpet_counter = 0ULL;
  553 + s->hpet_offset = 0ULL;
  554 + /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
  555 + s->capability = 0x8086a201ULL;
  556 + s->capability |= ((HPET_CLK_PERIOD) << 32);
  557 + if (count > 0)
  558 + /* we don't enable pit when hpet_reset is first called (by hpet_init)
  559 + * because hpet is taking over for pit here. On subsequent invocations,
  560 + * hpet_reset is called due to system reset. At this point control must
  561 + * be returned to pit until SW reenables hpet.
  562 + */
  563 + hpet_pit_enable();
  564 + count = 1;
  565 +}
  566 +
  567 +
  568 +void hpet_init(qemu_irq *irq) {
  569 + int i, iomemtype;
  570 + HPETState *s;
  571 +
  572 + dprintf ("hpet_init\n");
  573 +
  574 + s = qemu_mallocz(sizeof(HPETState));
  575 + hpet_statep = s;
  576 + s->irqs = irq;
  577 + for (i=0; i<HPET_NUM_TIMERS; i++) {
  578 + HPETTimer *timer = &s->timer[i];
  579 + timer->qemu_timer = qemu_new_timer(vm_clock, hpet_timer, timer);
  580 + }
  581 + hpet_reset(s);
  582 + register_savevm("hpet", -1, 1, hpet_save, hpet_load, s);
  583 + qemu_register_reset(hpet_reset, s);
  584 + /* HPET Area */
  585 + iomemtype = cpu_register_io_memory(0, hpet_ram_read,
  586 + hpet_ram_write, s);
  587 + cpu_register_physical_memory(HPET_BASE, 0x400, iomemtype);
  588 +}
... ...
hw/hpet_emul.h 0 → 100644
  View file @16b29ae
  1 +/*
  2 + * QEMU Emulated HPET support
  3 + *
  4 + * Copyright IBM, Corp. 2008
  5 + *
  6 + * Authors:
  7 + * Beth Kon <bkon@us.ibm.com>
  8 + *
  9 + * This work is licensed under the terms of the GNU GPL, version 2. See
  10 + * the COPYING file in the top-level directory.
  11 + *
  12 + */
  13 +#ifndef QEMU_HPET_EMUL_H
  14 +#define QEMU_HPET_EMUL_H
  15 +
  16 +#define HPET_BASE 0xfed00000
  17 +#define HPET_CLK_PERIOD 10000000ULL /* 10000000 femtoseconds == 10ns*/
  18 +
  19 +#define FS_PER_NS 1000000
  20 +#define HPET_NUM_TIMERS 3
  21 +#define HPET_TIMER_TYPE_LEVEL 1
  22 +#define HPET_TIMER_TYPE_EDGE 0
  23 +#define HPET_TIMER_DELIVERY_APIC 0
  24 +#define HPET_TIMER_DELIVERY_FSB 1
  25 +#define HPET_TIMER_CAP_FSB_INT_DEL (1 << 15)
  26 +#define HPET_TIMER_CAP_PER_INT (1 << 4)
  27 +
  28 +#define HPET_CFG_ENABLE 0x001
  29 +#define HPET_CFG_LEGACY 0x002
  30 +
  31 +#define HPET_ID 0x000
  32 +#define HPET_PERIOD 0x004
  33 +#define HPET_CFG 0x010
  34 +#define HPET_STATUS 0x020
  35 +#define HPET_COUNTER 0x0f0
  36 +#define HPET_TN_CFG 0x000
  37 +#define HPET_TN_CMP 0x008
  38 +#define HPET_TN_ROUTE 0x010
  39 +
  40 +
  41 +#define HPET_TN_ENABLE 0x004
  42 +#define HPET_TN_PERIODIC 0x008
  43 +#define HPET_TN_PERIODIC_CAP 0x010
  44 +#define HPET_TN_SIZE_CAP 0x020
  45 +#define HPET_TN_SETVAL 0x040
  46 +#define HPET_TN_32BIT 0x100
  47 +#define HPET_TN_INT_ROUTE_MASK 0x3e00
  48 +#define HPET_TN_INT_ROUTE_SHIFT 9
  49 +#define HPET_TN_INT_ROUTE_CAP_SHIFT 32
  50 +#define HPET_TN_CFG_BITS_READONLY_OR_RESERVED 0xffff80b1U
  51 +
  52 +struct HPETState;
  53 +typedef struct HPETTimer { /* timers */
  54 + uint8_t tn; /*timer number*/
  55 + QEMUTimer *qemu_timer;
  56 + struct HPETState *state;
  57 + /* Memory-mapped, software visible timer registers */
  58 + uint64_t config; /* configuration/cap */
  59 + uint64_t cmp; /* comparator */
  60 + uint64_t fsb; /* FSB route, not supported now */
  61 + /* Hidden register state */
  62 + uint64_t period; /* Last value written to comparator */
  63 + uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit
  64 + * mode. Next pop will be actual timer expiration.
  65 + */
  66 +} HPETTimer;
  67 +
  68 +typedef struct HPETState {
  69 + uint64_t hpet_offset;
  70 + qemu_irq *irqs;
  71 + HPETTimer timer[HPET_NUM_TIMERS];
  72 +
  73 + /* Memory-mapped, software visible registers */
  74 + uint64_t capability; /* capabilities */
  75 + uint64_t config; /* configuration */
  76 + uint64_t isr; /* interrupt status reg */
  77 + uint64_t hpet_counter; /* main counter */
  78 +} HPETState;
  79 +
  80 +#if defined TARGET_I386 || defined TARGET_X86_64
  81 +extern uint32_t hpet_in_legacy_mode(void);
  82 +extern void hpet_init(qemu_irq *irq);
  83 +#endif
  84 +
  85 +#endif
... ...
hw/i8254.c
  View file @16b29ae
... ... @@ -463,6 +463,27 @@ static void pit_reset(void *opaque)
463 463 }
464 464 }
465 465  
  466 +/* When HPET is operating in legacy mode, i8254 timer0 is disabled */
  467 +void hpet_pit_disable(void) {
  468 + PITChannelState *s;
  469 + s = &pit_state.channels[0];
  470 + qemu_del_timer(s->irq_timer);
  471 +}
  472 +
  473 +/* When HPET is reset or leaving legacy mode, it must reenable i8254
  474 + * timer 0
  475 + */
  476 +
  477 +void hpet_pit_enable(void)
  478 +{
  479 + PITState *pit = &pit_state;
  480 + PITChannelState *s;
  481 + s = &pit->channels[0];
  482 + s->mode = 3;
  483 + s->gate = 1;
  484 + pit_load_count(s, 0);
  485 +}
  486 +
466 487 PITState *pit_init(int base, qemu_irq irq)
467 488 {
468 489 PITState *pit = &pit_state;
... ...
hw/mc146818rtc.c
  View file @16b29ae
... ... @@ -26,6 +26,7 @@
26 26 #include "sysemu.h"
27 27 #include "pc.h"
28 28 #include "isa.h"
  29 +#include "hpet_emul.h"
29 30  
30 31 //#define DEBUG_CMOS
31 32  
... ... @@ -69,6 +70,18 @@ struct RTCState {
69 70 QEMUTimer *second_timer2;
70 71 };
71 72  
  73 +static void rtc_irq_raise(qemu_irq irq) {
  74 + /* When HPET is operating in legacy mode, RTC interrupts are disabled
  75 + * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
  76 + * mode is established while interrupt is raised. We want it to
  77 + * be lowered in any case
  78 + */
  79 +#if defined TARGET_I386 || defined TARGET_X86_64
  80 + if (!hpet_in_legacy_mode())
  81 +#endif
  82 + qemu_irq_raise(irq);
  83 +}
  84 +
72 85 static void rtc_set_time(RTCState *s);
73 86 static void rtc_copy_date(RTCState *s);
74 87  
... ... @@ -78,8 +91,14 @@ static void rtc_timer_update(RTCState *s, int64_t current_time)
78 91 int64_t cur_clock, next_irq_clock;
79 92  
80 93 period_code = s->cmos_data[RTC_REG_A] & 0x0f;
81   - if (period_code != 0 &&
82   - (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
  94 +#if defined TARGET_I386 || defined TARGET_X86_64
  95 + /* disable periodic timer if hpet is in legacy mode, since interrupts are
  96 + * disabled anyway.
  97 + */
  98 + if (period_code != 0 && (s->cmos_data[RTC_REG_B] & REG_B_PIE) && !hpet_in_legacy_mode()) {
  99 +#else
  100 + if (period_code != 0 && (s->cmos_data[RTC_REG_B] & REG_B_PIE)) {
  101 +#endif
83 102 if (period_code <= 2)
84 103 period_code += 7;
85 104 /* period in 32 Khz cycles */
... ... @@ -100,7 +119,7 @@ static void rtc_periodic_timer(void *opaque)
100 119  
101 120 rtc_timer_update(s, s->next_periodic_time);
102 121 s->cmos_data[RTC_REG_C] |= 0xc0;
103   - qemu_irq_raise(s->irq);
  122 + rtc_irq_raise(s->irq);
104 123 }
105 124  
106 125 static void cmos_ioport_write(void *opaque, uint32_t addr, uint32_t data)
... ... @@ -319,14 +338,14 @@ static void rtc_update_second2(void *opaque)
319 338 s->cmos_data[RTC_HOURS_ALARM] == s->current_tm.tm_hour)) {
320 339  
321 340 s->cmos_data[RTC_REG_C] |= 0xa0;
322   - qemu_irq_raise(s->irq);
  341 + rtc_irq_raise(s->irq);
323 342 }
324 343 }
325 344  
326 345 /* update ended interrupt */
327 346 if (s->cmos_data[RTC_REG_B] & REG_B_UIE) {
328 347 s->cmos_data[RTC_REG_C] |= 0x90;
329   - qemu_irq_raise(s->irq);
  348 + rtc_irq_raise(s->irq);
330 349 }
331 350  
332 351 /* clear update in progress bit */
... ...
... ... @@ -35,6 +35,7 @@
35 35 #include "fw_cfg.h"
36 36 #include "virtio-blk.h"
37 37 #include "virtio-balloon.h"
  38 +#include "hpet_emul.h"
38 39  
39 40 /* output Bochs bios info messages */
40 41 //#define DEBUG_BIOS
... ... @@ -977,6 +978,9 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
977 978 }
978 979 pit = pit_init(0x40, i8259[0]);
979 980 pcspk_init(pit);
  981 + if (!no_hpet) {
  982 + hpet_init(i8259);
  983 + }
980 984 if (pci_enabled) {
981 985 pic_set_alt_irq_func(isa_pic, ioapic_set_irq, ioapic);
982 986 }
... ...
... ... @@ -97,6 +97,9 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
97 97 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
98 98 void acpi_bios_init(void);
99 99  
  100 +/* hpet.c */
  101 +extern int no_hpet;
  102 +
100 103 /* pcspk.c */
101 104 void pcspk_init(PITState *);
102 105 int pcspk_audio_init(AudioState *, qemu_irq *pic);
... ...
monitor.c
  View file @16b29ae
... ... @@ -252,6 +252,11 @@ static void do_info_name(void)
252 252 term_printf("%s\n", qemu_name);
253 253 }
254 254  
  255 +static void do_info_hpet(void)
  256 +{
  257 + term_printf("HPET is %s by QEMU\n", (no_hpet) ? "disabled" : "enabled");
  258 +}
  259 +
255 260 static void do_info_uuid(void)
256 261 {
257 262 term_printf(UUID_FMT "\n", qemu_uuid[0], qemu_uuid[1], qemu_uuid[2],
... ... @@ -1531,6 +1536,8 @@ static const term_cmd_t info_cmds[] = {
1531 1536 "", "show virtual to physical memory mappings", },
1532 1537 { "mem", "", mem_info,
1533 1538 "", "show the active virtual memory mappings", },
  1539 + { "hpet", "", do_info_hpet,
  1540 + "", "show state of HPET", },
1534 1541 #endif
1535 1542 { "jit", "", do_info_jit,
1536 1543 "", "show dynamic compiler info", },
... ...
pc-bios/bios-pq/0005_hpet.patch 0 → 100644
  View file @16b29ae
  1 +BOCHS BIOS changes to support HPET in QEMU.
  2 +
  3 +Signed-off-by Beth Kon <eak@us.ibm.com>
  4 +
  5 +Index: bochs-2.3.7/bios/acpi-dsdt.dsl
  6 +===================================================================
  7 +--- bochs-2.3.7.orig/bios/acpi-dsdt.dsl 2008-10-15 12:39:14.000000000 -0500
  8 ++++ bochs-2.3.7/bios/acpi-dsdt.dsl 2008-10-28 07:58:40.000000000 -0500
  9 +@@ -159,6 +159,26 @@
  10 + Return (MEMP)
  11 + }
  12 + }
  13 ++#ifdef BX_QEMU
  14 ++ Device(HPET) {
  15 ++ Name(_HID, EISAID("PNP0103"))
  16 ++ Name(_UID, 0)
  17 ++ Method (_STA, 0, NotSerialized) {
  18 ++ Return(0x0F)
  19 ++ }
  20 ++ Name(_CRS, ResourceTemplate() {
  21 ++ DWordMemory(
  22 ++ ResourceConsumer, PosDecode, MinFixed, MaxFixed,
  23 ++ NonCacheable, ReadWrite,
  24 ++ 0x00000000,
  25 ++ 0xFED00000,
  26 ++ 0xFED003FF,
  27 ++ 0x00000000,
  28 ++ 0x00000400 /* 1K memory: FED00000 - FED003FF */
  29 ++ )
  30 ++ })
  31 ++ }
  32 ++#endif
  33 + }
  34 +
  35 + Scope(\_SB.PCI0) {
  36 +Index: bochs-2.3.7/bios/rombios32.c
  37 +===================================================================
  38 +--- bochs-2.3.7.orig/bios/rombios32.c 2008-10-15 12:39:36.000000000 -0500
  39 ++++ bochs-2.3.7/bios/rombios32.c 2008-11-12 14:41:41.000000000 -0600
  40 +@@ -1087,7 +1087,11 @@
  41 + struct rsdt_descriptor_rev1
  42 + {
  43 + ACPI_TABLE_HEADER_DEF /* ACPI common table header */
  44 ++#ifdef BX_QEMU
  45 ++ uint32_t table_offset_entry [4]; /* Array of pointers to other */
  46 ++#else
  47 + uint32_t table_offset_entry [3]; /* Array of pointers to other */
  48 ++#endif
  49 + /* ACPI tables */
  50 + };
  51 +
  52 +@@ -1227,6 +1231,32 @@
  53 + #endif
  54 + };
  55 +
  56 ++#ifdef BX_QEMU
  57 ++/*
  58 ++ * * ACPI 2.0 Generic Address Space definition.
  59 ++ * */
  60 ++struct acpi_20_generic_address {
  61 ++ uint8_t address_space_id;
  62 ++ uint8_t register_bit_width;
  63 ++ uint8_t register_bit_offset;
  64 ++ uint8_t reserved;
  65 ++ uint64_t address;
  66 ++};
  67 ++
  68 ++/*
  69 ++ * * HPET Description Table
  70 ++ * */
  71 ++struct acpi_20_hpet {
  72 ++ ACPI_TABLE_HEADER_DEF /* ACPI common table header */
  73 ++ uint32_t timer_block_id;
  74 ++ struct acpi_20_generic_address addr;
  75 ++ uint8_t hpet_number;
  76 ++ uint16_t min_tick;
  77 ++ uint8_t page_protect;
  78 ++};
  79 ++#define ACPI_HPET_ADDRESS 0xFED00000UL
  80 ++#endif
  81 ++
  82 + struct madt_io_apic
  83 + {
  84 + APIC_HEADER_DEF
  85 +@@ -1237,6 +1267,17 @@
  86 + * lines start */
  87 + };
  88 +
  89 ++#ifdef BX_QEMU
  90 ++struct madt_int_override
  91 ++{
  92 ++ APIC_HEADER_DEF
  93 ++ uint8_t bus; /* Identifies ISA Bus */
  94 ++ uint8_t source; /* Bus-relative interrupt source */
  95 ++ uint32_t gsi; /* GSI that source will signal */
  96 ++ uint16_t flags; /* MPS INTI flags */
  97 ++};
  98 ++#endif
  99 ++
  100 + #include "acpi-dsdt.hex"
  101 +
  102 + static inline uint16_t cpu_to_le16(uint16_t x)
  103 +@@ -1342,6 +1383,10 @@
  104 + struct facs_descriptor_rev1 *facs;
  105 + struct multiple_apic_table *madt;
  106 + uint8_t *dsdt, *ssdt;
  107 ++#ifdef BX_QEMU
  108 ++ struct acpi_20_hpet *hpet;
  109 ++ uint32_t hpet_addr;
  110 ++#endif
  111 + uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr, ssdt_addr;
  112 + uint32_t acpi_tables_size, madt_addr, madt_size;
  113 + int i;
  114 +@@ -1384,10 +1429,21 @@
  115 + madt_addr = addr;
  116 + madt_size = sizeof(*madt) +
  117 + sizeof(struct madt_processor_apic) * smp_cpus +
  118 ++#ifdef BX_QEMU
  119 ++ sizeof(struct madt_io_apic) + sizeof(struct madt_int_override);
  120 ++#else
  121 + sizeof(struct madt_io_apic);
  122 ++#endif
  123 + madt = (void *)(addr);
  124 + addr += madt_size;
  125 +
  126 ++#ifdef BX_QEMU
  127 ++ addr = (addr + 7) & ~7;
  128 ++ hpet_addr = addr;
  129 ++ hpet = (void *)(addr);
  130 ++ addr += sizeof(*hpet);
  131 ++#endif
  132 ++
  133 + acpi_tables_size = addr - base_addr;
  134 +
  135 + BX_INFO("ACPI tables: RSDP addr=0x%08lx ACPI DATA addr=0x%08lx size=0x%x\n",
  136 +@@ -1410,6 +1466,9 @@
  137 + rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
  138 + rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
  139 + rsdt->table_offset_entry[2] = cpu_to_le32(ssdt_addr);
  140 ++#ifdef BX_QEMU
  141 ++ rsdt->table_offset_entry[3] = cpu_to_le32(hpet_addr);
  142 ++#endif
  143 + acpi_build_table_header((struct acpi_table_header *)rsdt,
  144 + "RSDT", sizeof(*rsdt), 1);
  145 +
  146 +@@ -1448,6 +1507,9 @@
  147 + {
  148 + struct madt_processor_apic *apic;
  149 + struct madt_io_apic *io_apic;
  150 ++#ifdef BX_QEMU
  151 ++ struct madt_int_override *int_override;
  152 ++#endif
  153 +
  154 + memset(madt, 0, madt_size);
  155 + madt->local_apic_address = cpu_to_le32(0xfee00000);
  156 +@@ -1467,10 +1529,34 @@
  157 + io_apic->io_apic_id = smp_cpus;
  158 + io_apic->address = cpu_to_le32(0xfec00000);
  159 + io_apic->interrupt = cpu_to_le32(0);
  160 ++#ifdef BX_QEMU
  161 ++ io_apic++;
  162 ++
  163 ++ int_override = (void *)io_apic;
  164 ++ int_override->type = APIC_XRUPT_OVERRIDE;
  165 ++ int_override->length = sizeof(*int_override);
  166 ++ int_override->bus = cpu_to_le32(0);
  167 ++ int_override->source = cpu_to_le32(0);
  168 ++ int_override->gsi = cpu_to_le32(2);
  169 ++ int_override->flags = cpu_to_le32(0);
  170 ++#endif
  171 +
  172 + acpi_build_table_header((struct acpi_table_header *)madt,
  173 + "APIC", madt_size, 1);
  174 + }
  175 ++
  176 ++#ifdef BX_QEMU
  177 ++ /* HPET */
  178 ++ memset(hpet, 0, sizeof(*hpet));
  179 ++ /* Note timer_block_id value must be kept in sync with value advertised by
  180 ++ * emulated hpet
  181 ++ */
  182 ++ hpet->timer_block_id = cpu_to_le32(0x8086a201);
  183 ++ hpet->addr.address = cpu_to_le32(ACPI_HPET_ADDRESS);
  184 ++ acpi_build_table_header((struct acpi_table_header *)hpet,
  185 ++ "HPET", sizeof(*hpet), 1);
  186 ++#endif
  187 ++
  188 + }
  189 +
  190 + /* SMBIOS entry point -- must be written to a 16-bit aligned address
... ...
pc-bios/bios-pq/series
  View file @16b29ae
... ... @@ -2,3 +2,4 @@
2 2 0002_e820-high-mem.patch
3 3 0003_smp-startup-poll.patch
4 4 0004_no-stack-protector.patch
  5 +0005_hpet.patch
... ...
pc-bios/bios.bin
View file @16b29ae
No preview for this file type
... ... @@ -224,6 +224,7 @@ int usb_enabled = 0;
224 224 int smp_cpus = 1;
225 225 const char *vnc_display;
226 226 int acpi_enabled = 1;
  227 +int no_hpet = 0;
227 228 int fd_bootchk = 1;
228 229 int no_reboot = 0;
229 230 int no_shutdown = 0;
... ... @@ -3956,6 +3957,7 @@ static void help(int exitcode)
3956 3957 #endif
3957 3958 #ifdef TARGET_I386
3958 3959 "-no-acpi disable ACPI\n"
  3960 + "-no-hpet disable HPET\n"
3959 3961 #endif
3960 3962 #ifdef CONFIG_CURSES
3961 3963 "-curses use a curses/ncurses interface instead of SDL\n"
... ... @@ -4067,6 +4069,7 @@ enum {
4067 4069 QEMU_OPTION_smp,
4068 4070 QEMU_OPTION_vnc,
4069 4071 QEMU_OPTION_no_acpi,
  4072 + QEMU_OPTION_no_hpet,
4070 4073 QEMU_OPTION_curses,
4071 4074 QEMU_OPTION_no_reboot,
4072 4075 QEMU_OPTION_no_shutdown,
... ... @@ -4180,6 +4183,7 @@ static const QEMUOption qemu_options[] = {
4180 4183 /* temporary options */
4181 4184 { "usb", 0, QEMU_OPTION_usb },
4182 4185 { "no-acpi", 0, QEMU_OPTION_no_acpi },
  4186 + { "no-hpet", 0, QEMU_OPTION_no_hpet },
4183 4187 { "no-reboot", 0, QEMU_OPTION_no_reboot },
4184 4188 { "no-shutdown", 0, QEMU_OPTION_no_shutdown },
4185 4189 { "show-cursor", 0, QEMU_OPTION_show_cursor },
... ... @@ -5017,6 +5021,9 @@ int main(int argc, char **argv, char **envp)
5017 5021 case QEMU_OPTION_no_acpi:
5018 5022 acpi_enabled = 0;
5019 5023 break;
  5024 + case QEMU_OPTION_no_hpet:
  5025 + no_hpet = 1;
  5026 + break;
5020 5027 case QEMU_OPTION_no_reboot:
5021 5028 no_reboot = 1;
5022 5029 break;
... ...