1
2
/*
* ACPI implementation
ths
authored
18 years ago
3
*
4
* Copyright ( c ) 2006 Fabrice Bellard
ths
authored
18 years ago
5
*
6
7
8
9
10
11
12
13
14
15
* This library is free software ; you can redistribute it and / or
* modify it under the terms of the GNU Lesser General Public
* License version 2 as published by the Free Software Foundation .
*
* This library is distributed in the hope that it will be useful ,
* but WITHOUT ANY WARRANTY ; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE . See the GNU
* Lesser General Public License for more details .
*
* You should have received a copy of the GNU Lesser General Public
16
* License along with this library ; if not , see < http :// www . gnu . org / licenses />
17
*/
18
19
20
21
22
23
24
# include "hw.h"
# include "pc.h"
# include "pci.h"
# include "qemu-timer.h"
# include "sysemu.h"
# include "i2c.h"
# include "smbus.h"
25
# include "kvm.h"
26
27
28
29
30
31
32
33
34
35
36
37
38
// # define DEBUG
/* i82731AB (PIIX4) compatible power management function */
# define PM_FREQ 3579545
# define ACPI_DBG_IO_ADDR 0xb044
typedef struct PIIX4PMState {
PCIDevice dev ;
uint16_t pmsts ;
uint16_t pmen ;
uint16_t pmcntrl ;
39
40
uint8_t apmc ;
uint8_t apms ;
41
42
QEMUTimer * tmr_timer ;
int64_t tmr_overflow_time ;
43
i2c_bus * smbus ;
ths
authored
18 years ago
44
45
46
47
48
49
50
51
uint8_t smb_stat ;
uint8_t smb_ctl ;
uint8_t smb_cmd ;
uint8_t smb_addr ;
uint8_t smb_data0 ;
uint8_t smb_data1 ;
uint8_t smb_data [ 32 ];
uint8_t smb_index ;
52
qemu_irq irq ;
53
54
} PIIX4PMState ;
55
56
# define RSM_STS ( 1 << 15 )
# define PWRBTN_STS ( 1 << 8 )
57
58
59
60
61
62
63
64
65
# define RTC_EN ( 1 << 10 )
# define PWRBTN_EN ( 1 << 8 )
# define GBL_EN ( 1 << 5 )
# define TMROF_EN ( 1 << 0 )
# define SCI_EN ( 1 << 0 )
# define SUS_EN ( 1 << 13 )
ths
authored
18 years ago
66
67
68
# define ACPI_ENABLE 0xf1
# define ACPI_DISABLE 0xf0
ths
authored
18 years ago
69
70
71
72
73
74
75
76
# define SMBHSTSTS 0x00
# define SMBHSTCNT 0x02
# define SMBHSTCMD 0x03
# define SMBHSTADD 0x04
# define SMBHSTDAT0 0x05
# define SMBHSTDAT1 0x06
# define SMBBLKDAT 0x07
77
static PIIX4PMState * pm_state ;
78
79
80
static uint32_t get_pmtmr ( PIIX4PMState * s )
{
81
82
83
uint32_t d ;
d = muldiv64 ( qemu_get_clock ( vm_clock ), PM_FREQ , ticks_per_sec );
return d & 0xffffff ;
84
85
86
87
}
static int get_pmsts ( PIIX4PMState * s )
{
88
89
90
91
92
93
int64_t d ;
int pmsts ;
pmsts = s -> pmsts ;
d = muldiv64 ( qemu_get_clock ( vm_clock ), PM_FREQ , ticks_per_sec );
if ( d >= s -> tmr_overflow_time )
s -> pmsts |= TMROF_EN ;
94
return s -> pmsts ;
95
96
97
98
}
static void pm_update_sci ( PIIX4PMState * s )
{
99
100
101
102
103
104
105
106
107
108
109
110
111
112
int sci_level , pmsts ;
int64_t expire_time ;
pmsts = get_pmsts ( s );
sci_level = ((( pmsts & s -> pmen ) &
( RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN )) != 0 );
qemu_set_irq ( s -> irq , sci_level );
/* schedule a timer interruption if needed */
if (( s -> pmen & TMROF_EN ) && ! ( pmsts & TMROF_EN )) {
expire_time = muldiv64 ( s -> tmr_overflow_time , ticks_per_sec , PM_FREQ );
qemu_mod_timer ( s -> tmr_timer , expire_time );
} else {
qemu_del_timer ( s -> tmr_timer );
}
113
114
115
116
117
}
static void pm_tmr_timer ( void * opaque )
{
PIIX4PMState * s = opaque ;
118
pm_update_sci ( s );
119
120
121
122
123
124
125
126
}
static void pm_ioport_writew ( void * opaque , uint32_t addr , uint32_t val )
{
PIIX4PMState * s = opaque ;
addr &= 0x3f ;
switch ( addr ) {
case 0x00 :
127
128
129
130
131
132
133
134
135
136
137
138
{
int64_t d ;
int pmsts ;
pmsts = get_pmsts ( s );
if ( pmsts & val & TMROF_EN ) {
/* if TMRSTS is reset, then compute the new overflow time */
d = muldiv64 ( qemu_get_clock ( vm_clock ), PM_FREQ , ticks_per_sec );
s -> tmr_overflow_time = ( d + 0x800000LL ) & ~ 0x7fffffLL ;
}
s -> pmsts &= ~ val ;
pm_update_sci ( s );
}
139
140
141
142
143
144
145
146
147
148
149
break ;
case 0x02 :
s -> pmen = val ;
pm_update_sci ( s );
break ;
case 0x04 :
{
int sus_typ ;
s -> pmcntrl = val & ~ ( SUS_EN );
if ( val & SUS_EN ) {
/* change suspend type */
150
sus_typ = ( val >> 10 ) & 7 ;
151
152
153
154
switch ( sus_typ ) {
case 0 : /* soft power off */
qemu_system_shutdown_request ();
break ;
155
156
157
158
159
160
161
162
case 1 :
/* RSM_STS should be set on resume . Pretend that resume
was caused by power button */
s -> pmsts |= ( RSM_STS | PWRBTN_STS );
qemu_system_reset_request ();
# if defined ( TARGET_I386 )
cmos_set_s3_resume ();
# endif
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
default :
break ;
}
}
}
break ;
default :
break ;
}
# ifdef DEBUG
printf ( "PM writew port=0x%04x val=0x%04x \n " , addr , val );
# endif
}
static uint32_t pm_ioport_readw ( void * opaque , uint32_t addr )
{
PIIX4PMState * s = opaque ;
uint32_t val ;
addr &= 0x3f ;
switch ( addr ) {
case 0x00 :
val = get_pmsts ( s );
break ;
case 0x02 :
val = s -> pmen ;
break ;
case 0x04 :
val = s -> pmcntrl ;
break ;
default :
val = 0 ;
break ;
}
# ifdef DEBUG
printf ( "PM readw port=0x%04x val=0x%04x \n " , addr , val );
# endif
return val ;
}
static void pm_ioport_writel ( void * opaque , uint32_t addr , uint32_t val )
{
// PIIX4PMState * s = opaque ;
addr &= 0x3f ;
# ifdef DEBUG
printf ( "PM writel port=0x%04x val=0x%08x \n " , addr , val );
# endif
}
static uint32_t pm_ioport_readl ( void * opaque , uint32_t addr )
{
PIIX4PMState * s = opaque ;
uint32_t val ;
addr &= 0x3f ;
switch ( addr ) {
case 0x08 :
val = get_pmtmr ( s );
break ;
default :
val = 0 ;
break ;
}
# ifdef DEBUG
printf ( "PM readl port=0x%04x val=0x%08x \n " , addr , val );
# endif
return val ;
}
232
static void pm_smi_writeb ( void * opaque , uint32_t addr , uint32_t val )
233
234
{
PIIX4PMState * s = opaque ;
235
addr &= 1 ;
236
# ifdef DEBUG
237
printf ( "pm_smi_writeb addr=0x%x val=0x%02x \n " , addr , val );
238
# endif
239
240
if ( addr == 0 ) {
s -> apmc = val ;
ths
authored
18 years ago
241
242
243
244
245
246
247
248
/* ACPI specs 3.0, 4.7.2.5 */
if ( val == ACPI_ENABLE ) {
s -> pmcntrl |= SCI_EN ;
} else if ( val == ACPI_DISABLE ) {
s -> pmcntrl &= ~ SCI_EN ;
}
249
250
if ( s -> dev . config [ 0x5b ] & ( 1 << 1 )) {
cpu_interrupt ( first_cpu , CPU_INTERRUPT_SMI );
251
252
253
}
} else {
s -> apms = val ;
254
255
256
}
}
257
258
259
260
static uint32_t pm_smi_readb ( void * opaque , uint32_t addr )
{
PIIX4PMState * s = opaque ;
uint32_t val ;
ths
authored
18 years ago
261
262
263
264
265
266
267
268
269
270
271
272
273
addr &= 1 ;
if ( addr == 0 ) {
val = s -> apmc ;
} else {
val = s -> apms ;
}
# ifdef DEBUG
printf ( "pm_smi_readb addr=0x%x val=0x%02x \n " , addr , val );
# endif
return val ;
}
274
275
276
277
278
279
280
static void acpi_dbg_writel ( void * opaque , uint32_t addr , uint32_t val )
{
# if defined ( DEBUG )
printf ( "ACPI: DBG: 0x%08x \n " , val );
# endif
}
ths
authored
18 years ago
281
282
283
284
285
286
static void smb_transaction ( PIIX4PMState * s )
{
uint8_t prot = ( s -> smb_ctl >> 2 ) & 0x07 ;
uint8_t read = s -> smb_addr & 0x01 ;
uint8_t cmd = s -> smb_cmd ;
uint8_t addr = s -> smb_addr >> 1 ;
287
i2c_bus * bus = s -> smbus ;
ths
authored
18 years ago
288
289
290
291
292
293
# ifdef DEBUG
printf ( "SMBus trans addr=0x%02x prot=0x%02x \n " , addr , prot );
# endif
switch ( prot ) {
case 0x0 :
294
smbus_quick_command ( bus , addr , read );
ths
authored
18 years ago
295
296
297
break ;
case 0x1 :
if ( read ) {
298
299
300
s -> smb_data0 = smbus_receive_byte ( bus , addr );
} else {
smbus_send_byte ( bus , addr , cmd );
ths
authored
18 years ago
301
302
303
304
}
break ;
case 0x2 :
if ( read ) {
305
306
307
s -> smb_data0 = smbus_read_byte ( bus , addr , cmd );
} else {
smbus_write_byte ( bus , addr , cmd , s -> smb_data0 );
ths
authored
18 years ago
308
309
310
311
312
}
break ;
case 0x3 :
if ( read ) {
uint16_t val ;
313
val = smbus_read_word ( bus , addr , cmd );
ths
authored
18 years ago
314
315
s -> smb_data0 = val ;
s -> smb_data1 = val >> 8 ;
316
317
} else {
smbus_write_word ( bus , addr , cmd , ( s -> smb_data1 << 8 ) | s -> smb_data0 );
ths
authored
18 years ago
318
319
320
321
}
break ;
case 0x5 :
if ( read ) {
322
323
324
s -> smb_data0 = smbus_read_block ( bus , addr , cmd , s -> smb_data );
} else {
smbus_write_block ( bus , addr , cmd , s -> smb_data , s -> smb_data0 );
ths
authored
18 years ago
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
}
break ;
default :
goto error ;
}
return ;
error :
s -> smb_stat |= 0x04 ;
}
static void smb_ioport_writeb ( void * opaque , uint32_t addr , uint32_t val )
{
PIIX4PMState * s = opaque ;
addr &= 0x3f ;
# ifdef DEBUG
printf ( "SMB writeb port=0x%04x val=0x%02x \n " , addr , val );
# endif
switch ( addr ) {
case SMBHSTSTS :
s -> smb_stat = 0 ;
s -> smb_index = 0 ;
break ;
case SMBHSTCNT :
s -> smb_ctl = val ;
if ( val & 0x40 )
smb_transaction ( s );
break ;
case SMBHSTCMD :
s -> smb_cmd = val ;
break ;
case SMBHSTADD :
s -> smb_addr = val ;
break ;
case SMBHSTDAT0 :
s -> smb_data0 = val ;
break ;
case SMBHSTDAT1 :
s -> smb_data1 = val ;
break ;
case SMBBLKDAT :
s -> smb_data [ s -> smb_index ++ ] = val ;
if ( s -> smb_index > 31 )
s -> smb_index = 0 ;
break ;
default :
break ;
}
}
static uint32_t smb_ioport_readb ( void * opaque , uint32_t addr )
{
PIIX4PMState * s = opaque ;
uint32_t val ;
addr &= 0x3f ;
switch ( addr ) {
case SMBHSTSTS :
val = s -> smb_stat ;
break ;
case SMBHSTCNT :
s -> smb_index = 0 ;
val = s -> smb_ctl & 0x1f ;
break ;
case SMBHSTCMD :
val = s -> smb_cmd ;
break ;
case SMBHSTADD :
val = s -> smb_addr ;
break ;
case SMBHSTDAT0 :
val = s -> smb_data0 ;
break ;
case SMBHSTDAT1 :
val = s -> smb_data1 ;
break ;
case SMBBLKDAT :
val = s -> smb_data [ s -> smb_index ++ ];
if ( s -> smb_index > 31 )
s -> smb_index = 0 ;
break ;
default :
val = 0 ;
break ;
}
# ifdef DEBUG
printf ( "SMB readb port=0x%04x val=0x%02x \n " , addr , val );
# endif
return val ;
}
416
417
418
419
420
421
static void pm_io_space_update ( PIIX4PMState * s )
{
uint32_t pm_io_base ;
if ( s -> dev . config [ 0x80 ] & 1 ) {
pm_io_base = le32_to_cpu ( * ( uint32_t * )( s -> dev . config + 0x40 ));
ths
authored
17 years ago
422
pm_io_base &= 0xffc0 ;
423
424
425
426
427
428
429
430
431
432
433
434
/* XXX: need to improve memory and ioport allocation */
# if defined ( DEBUG )
printf ( "PM: mapping to 0x%x \n " , pm_io_base );
# endif
register_ioport_write ( pm_io_base , 64 , 2 , pm_ioport_writew , s );
register_ioport_read ( pm_io_base , 64 , 2 , pm_ioport_readw , s );
register_ioport_write ( pm_io_base , 64 , 4 , pm_ioport_writel , s );
register_ioport_read ( pm_io_base , 64 , 4 , pm_ioport_readl , s );
}
}
ths
authored
18 years ago
435
static void pm_write_config ( PCIDevice * d ,
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
uint32_t address , uint32_t val , int len )
{
pci_default_write_config ( d , address , val , len );
if ( address == 0x80 )
pm_io_space_update (( PIIX4PMState * ) d );
}
static void pm_save ( QEMUFile * f , void * opaque )
{
PIIX4PMState * s = opaque ;
pci_device_save ( & s -> dev , f );
qemu_put_be16s ( f , & s -> pmsts );
qemu_put_be16s ( f , & s -> pmen );
qemu_put_be16s ( f , & s -> pmcntrl );
qemu_put_8s ( f , & s -> apmc );
qemu_put_8s ( f , & s -> apms );
qemu_put_timer ( f , s -> tmr_timer );
ths
authored
17 years ago
455
qemu_put_be64 ( f , s -> tmr_overflow_time );
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
}
static int pm_load ( QEMUFile * f , void * opaque , int version_id )
{
PIIX4PMState * s = opaque ;
int ret ;
if ( version_id > 1 )
return - EINVAL ;
ret = pci_device_load ( & s -> dev , f );
if ( ret < 0 )
return ret ;
qemu_get_be16s ( f , & s -> pmsts );
qemu_get_be16s ( f , & s -> pmen );
qemu_get_be16s ( f , & s -> pmcntrl );
qemu_get_8s ( f , & s -> apmc );
qemu_get_8s ( f , & s -> apms );
qemu_get_timer ( f , s -> tmr_timer );
ths
authored
17 years ago
476
s -> tmr_overflow_time = qemu_get_be64 ( f );
477
478
479
480
481
482
pm_io_space_update ( s );
return 0 ;
}
483
484
static void piix4_reset ( void * opaque )
{
485
486
487
488
489
490
491
PIIX4PMState * s = opaque ;
uint8_t * pci_conf = s -> dev . config ;
pci_conf [ 0x58 ] = 0 ;
pci_conf [ 0x59 ] = 0 ;
pci_conf [ 0x5a ] = 0 ;
pci_conf [ 0x5b ] = 0 ;
492
493
494
495
496
if ( kvm_enabled ()) {
/* Mark SMM as already inited (until KVM supports SMM). */
pci_conf [ 0x5B ] = 0x02 ;
}
497
498
}
499
500
i2c_bus * piix4_pm_init ( PCIBus * bus , int devfn , uint32_t smb_io_base ,
qemu_irq sci_irq )
501
502
503
504
505
506
{
PIIX4PMState * s ;
uint8_t * pci_conf ;
s = ( PIIX4PMState * ) pci_register_device ( bus ,
"PM" , sizeof ( PIIX4PMState ),
507
devfn , NULL , pm_write_config );
508
pm_state = s ;
509
pci_conf = s -> dev . config ;
510
511
pci_config_set_vendor_id ( pci_conf , PCI_VENDOR_ID_INTEL );
pci_config_set_device_id ( pci_conf , PCI_DEVICE_ID_INTEL_82371AB_3 );
ths
authored
17 years ago
512
513
pci_conf [ 0x06 ] = 0x80 ;
pci_conf [ 0x07 ] = 0x02 ;
514
pci_conf [ 0x08 ] = 0x03 ; // revision number
515
pci_conf [ 0x09 ] = 0x00 ;
516
pci_config_set_class ( pci_conf , PCI_CLASS_BRIDGE_OTHER );
517
pci_conf [ PCI_HEADER_TYPE ] = PCI_HEADER_TYPE_NORMAL ; // header_type
518
pci_conf [ 0x3d ] = 0x01 ; // interrupt pin 1
ths
authored
18 years ago
519
520
pci_conf [ 0x40 ] = 0x01 ; /* PM io base read only bit */
ths
authored
18 years ago
521
522
523
524
register_ioport_write ( 0xb2 , 2 , 1 , pm_smi_writeb , s );
register_ioport_read ( 0xb2 , 2 , 1 , pm_smi_readb , s );
525
526
register_ioport_write ( ACPI_DBG_IO_ADDR , 4 , 4 , acpi_dbg_writel , s );
527
528
529
530
531
532
if ( kvm_enabled ()) {
/* Mark SMM as already inited to prevent SMM from running . KVM does not
* support SMM mode . */
pci_conf [ 0x5B ] = 0x02 ;
}
533
534
535
536
537
538
539
/* XXX : which specification is used ? The i82731AB has different
mappings */
pci_conf [ 0x5f ] = ( parallel_hds [ 0 ] != NULL ? 0x80 : 0 ) | 0x10 ;
pci_conf [ 0x63 ] = 0x60 ;
pci_conf [ 0x67 ] = ( serial_hds [ 0 ] != NULL ? 0x08 : 0 ) |
( serial_hds [ 1 ] != NULL ? 0x90 : 0 );
ths
authored
18 years ago
540
541
542
543
544
545
pci_conf [ 0x90 ] = smb_io_base | 1 ;
pci_conf [ 0x91 ] = smb_io_base >> 8 ;
pci_conf [ 0xd2 ] = 0x09 ;
register_ioport_write ( smb_io_base , 64 , 1 , smb_ioport_writeb , s );
register_ioport_read ( smb_io_base , 64 , 1 , smb_ioport_readb , s );
546
547
s -> tmr_timer = qemu_new_timer ( vm_clock , pm_tmr_timer , s );
548
register_savevm ( "piix4_pm" , 0 , 1 , pm_save , pm_load , s );
ths
authored
18 years ago
549
550
s -> smbus = i2c_init_bus ( NULL , "i2c" );
551
s -> irq = sci_irq ;
552
qemu_register_reset ( piix4_reset , s );
553
554
return s -> smbus ;
555
}
556
557
558
559
# if defined ( TARGET_I386 )
void qemu_system_powerdown ( void )
{
560
561
562
if ( ! pm_state ) {
qemu_system_shutdown_request ();
} else if ( pm_state -> pmen & PWRBTN_EN ) {
563
564
565
566
567
pm_state -> pmsts |= PWRBTN_EN ;
pm_update_sci ( pm_state );
}
}
# endif
568
569
# define GPE_BASE 0xafe0
570
571
# define PCI_BASE 0xae00
# define PCI_EJ_BASE 0xae08
572
573
574
575
576
577
struct gpe_regs {
uint16_t sts ; /* status */
uint16_t en ; /* enabled */
};
578
579
580
581
582
struct pci_status {
uint32_t up ;
uint32_t down ;
};
583
static struct gpe_regs gpe ;
584
static struct pci_status pci0_status ;
585
586
587
588
589
590
591
592
static uint32_t gpe_read_val ( uint16_t val , uint32_t addr )
{
if ( addr & 1 )
return ( val >> 8 ) & 0xff ;
return val & 0xff ;
}
593
594
595
596
597
598
599
static uint32_t gpe_readb ( void * opaque , uint32_t addr )
{
uint32_t val = 0 ;
struct gpe_regs * g = opaque ;
switch ( addr ) {
case GPE_BASE :
case GPE_BASE + 1 :
600
val = gpe_read_val ( g -> sts , addr );
601
602
603
break ;
case GPE_BASE + 2 :
case GPE_BASE + 3 :
604
val = gpe_read_val ( g -> en , addr );
605
606
607
608
609
610
break ;
default :
break ;
}
# if defined ( DEBUG )
611
printf ( "gpe read %x == %x \n " , addr , val );
612
613
614
615
# endif
return val ;
}
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
static void gpe_write_val ( uint16_t * cur , int addr , uint32_t val )
{
if ( addr & 1 )
* cur = ( * cur & 0xff ) | ( val << 8 );
else
* cur = ( * cur & 0xff00 ) | ( val & 0xff );
}
static void gpe_reset_val ( uint16_t * cur , int addr , uint32_t val )
{
uint16_t x1 , x0 = val & 0xff ;
int shift = ( addr & 1 ) ? 8 : 0 ;
x1 = ( * cur >> shift ) & 0xff ;
x1 = x1 & ~ x0 ;
* cur = ( * cur & ( 0xff << ( 8 - shift ))) | ( x1 << shift );
}
636
637
638
639
640
641
static void gpe_writeb ( void * opaque , uint32_t addr , uint32_t val )
{
struct gpe_regs * g = opaque ;
switch ( addr ) {
case GPE_BASE :
case GPE_BASE + 1 :
642
gpe_reset_val ( & g -> sts , addr , val );
643
644
645
break ;
case GPE_BASE + 2 :
case GPE_BASE + 3 :
646
gpe_write_val ( & g -> en , addr , val );
647
648
649
650
651
652
break ;
default :
break ;
}
# if defined ( DEBUG )
653
printf ( "gpe write %x <== %d \n " , addr , val );
654
655
656
# endif
}
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
static uint32_t pcihotplug_read ( void * opaque , uint32_t addr )
{
uint32_t val = 0 ;
struct pci_status * g = opaque ;
switch ( addr ) {
case PCI_BASE :
val = g -> up ;
break ;
case PCI_BASE + 4 :
val = g -> down ;
break ;
default :
break ;
}
# if defined ( DEBUG )
673
printf ( "pcihotplug read %x == %x \n " , addr , val );
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
# endif
return val ;
}
static void pcihotplug_write ( void * opaque , uint32_t addr , uint32_t val )
{
struct pci_status * g = opaque ;
switch ( addr ) {
case PCI_BASE :
g -> up = val ;
break ;
case PCI_BASE + 4 :
g -> down = val ;
break ;
}
# if defined ( DEBUG )
691
printf ( "pcihotplug write %x <== %d \n " , addr , val );
692
693
694
695
696
697
# endif
}
static uint32_t pciej_read ( void * opaque , uint32_t addr )
{
# if defined ( DEBUG )
698
printf ( "pciej read %x \n " , addr );
699
700
701
702
703
704
# endif
return 0 ;
}
static void pciej_write ( void * opaque , uint32_t addr , uint32_t val )
{
705
# if defined ( TARGET_I386 )
706
707
int slot = ffs ( val ) - 1 ;
708
709
710
pci_device_hot_remove_success ( 0 , slot );
# endif
711
# if defined ( DEBUG )
712
printf ( "pciej write %x <== %d \n " , addr , val );
713
714
715
# endif
}
716
717
718
static void piix4_device_hot_add ( int bus , int slot , int state );
void piix4_acpi_system_hot_add_init ( void )
719
720
721
722
{
register_ioport_write ( GPE_BASE , 4 , 1 , gpe_writeb , & gpe );
register_ioport_read ( GPE_BASE , 4 , 1 , gpe_readb , & gpe );
723
724
725
726
727
register_ioport_write ( PCI_BASE , 8 , 4 , pcihotplug_write , & pci0_status );
register_ioport_read ( PCI_BASE , 8 , 4 , pcihotplug_read , & pci0_status );
register_ioport_write ( PCI_EJ_BASE , 4 , 4 , pciej_write , NULL );
register_ioport_read ( PCI_EJ_BASE , 4 , 4 , pciej_read , NULL );
728
729
qemu_system_device_hot_add_register ( piix4_device_hot_add );
730
731
732
733
734
735
736
737
738
739
740
741
742
743
}
static void enable_device ( struct pci_status * p , struct gpe_regs * g , int slot )
{
g -> sts |= 2 ;
p -> up |= ( 1 << slot );
}
static void disable_device ( struct pci_status * p , struct gpe_regs * g , int slot )
{
g -> sts |= 2 ;
p -> down |= ( 1 << slot );
}
744
static void piix4_device_hot_add ( int bus , int slot , int state )
745
746
747
748
749
750
751
{
pci0_status . up = 0 ;
pci0_status . down = 0 ;
if ( state )
enable_device ( & pci0_status , & gpe , slot );
else
disable_device ( & pci0_status , & gpe , slot );
752
753
754
755
if ( gpe . en & 2 ) {
qemu_set_irq ( pm_state -> irq , 1 );
qemu_set_irq ( pm_state -> irq , 0 );
}
756
}
757
758
759
760
761
762
763
764
765
766
767
768
769
static qemu_system_device_hot_add_t device_hot_add_callback ;
void qemu_system_device_hot_add_register ( qemu_system_device_hot_add_t callback )
{
device_hot_add_callback = callback ;
}
void qemu_system_device_hot_add ( int pcibus , int slot , int state )
{
if ( device_hot_add_callback )
device_hot_add_callback ( pcibus , slot , state );
}
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
struct acpi_table_header
{
char signature [ 4 ]; /* ACPI signature (4 ASCII characters) */
uint32_t length ; /* Length of table, in bytes, including header */
uint8_t revision ; /* ACPI Specification minor version # */
uint8_t checksum ; /* To make sum of entire table == 0 */
char oem_id [ 6 ]; /* OEM identification */
char oem_table_id [ 8 ]; /* OEM table identification */
uint32_t oem_revision ; /* OEM revision number */
char asl_compiler_id [ 4 ]; /* ASL compiler vendor ID */
uint32_t asl_compiler_revision ; /* ASL compiler revision number */
} __attribute__ (( packed ));
char * acpi_tables ;
size_t acpi_tables_len ;
static int acpi_checksum ( const uint8_t * data , int len )
{
int sum , i ;
sum = 0 ;
for ( i = 0 ; i < len ; i ++ )
sum += data [ i ];
return ( - sum ) & 0xff ;
}
int acpi_table_add ( const char * t )
{
static const char * dfl_id = "QEMUQEMU" ;
char buf [ 1024 ], * p , * f ;
struct acpi_table_header acpi_hdr ;
unsigned long val ;
size_t off ;
memset ( & acpi_hdr , 0 , sizeof ( acpi_hdr ));
if ( get_param_value ( buf , sizeof ( buf ), "sig" , t )) {
strncpy ( acpi_hdr . signature , buf , 4 );
} else {
strncpy ( acpi_hdr . signature , dfl_id , 4 );
}
if ( get_param_value ( buf , sizeof ( buf ), "rev" , t )) {
val = strtoul ( buf , & p , 10 );
if ( val > 255 || * p != '\0' )
goto out ;
} else {
val = 1 ;
}
acpi_hdr . revision = ( int8_t ) val ;
if ( get_param_value ( buf , sizeof ( buf ), "oem_id" , t )) {
strncpy ( acpi_hdr . oem_id , buf , 6 );
} else {
strncpy ( acpi_hdr . oem_id , dfl_id , 6 );
}
if ( get_param_value ( buf , sizeof ( buf ), "oem_table_id" , t )) {
strncpy ( acpi_hdr . oem_table_id , buf , 8 );
} else {
strncpy ( acpi_hdr . oem_table_id , dfl_id , 8 );
}
if ( get_param_value ( buf , sizeof ( buf ), "oem_rev" , t )) {
val = strtol ( buf , & p , 10 );
if ( * p != '\0' )
goto out ;
} else {
val = 1 ;
}
acpi_hdr . oem_revision = cpu_to_le32 ( val );
if ( get_param_value ( buf , sizeof ( buf ), "asl_compiler_id" , t )) {
strncpy ( acpi_hdr . asl_compiler_id , buf , 4 );
} else {
strncpy ( acpi_hdr . asl_compiler_id , dfl_id , 4 );
}
if ( get_param_value ( buf , sizeof ( buf ), "asl_compiler_rev" , t )) {
val = strtol ( buf , & p , 10 );
if ( * p != '\0' )
goto out ;
} else {
val = 1 ;
}
acpi_hdr . asl_compiler_revision = cpu_to_le32 ( val );
if ( ! get_param_value ( buf , sizeof ( buf ), "data" , t )) {
buf [ 0 ] = '\0' ;
}
acpi_hdr . length = sizeof ( acpi_hdr );
f = buf ;
while ( buf [ 0 ]) {
struct stat s ;
864
char * n = strchr ( f , ':' );
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
if ( n )
* n = '\0' ;
if ( stat ( f , & s ) < 0 ) {
fprintf ( stderr , "Can't stat file '%s': %s \n " , f , strerror ( errno ));
goto out ;
}
acpi_hdr . length += s . st_size ;
if ( ! n )
break ;
* n = ':' ;
f = n + 1 ;
}
if ( ! acpi_tables ) {
acpi_tables_len = sizeof ( uint16_t );
acpi_tables = qemu_mallocz ( acpi_tables_len );
}
p = acpi_tables + acpi_tables_len ;
acpi_tables_len += sizeof ( uint16_t ) + acpi_hdr . length ;
acpi_tables = qemu_realloc ( acpi_tables , acpi_tables_len );
acpi_hdr . length = cpu_to_le32 ( acpi_hdr . length );
* ( uint16_t * ) p = acpi_hdr . length ;
p += sizeof ( uint16_t );
memcpy ( p , & acpi_hdr , sizeof ( acpi_hdr ));
off = sizeof ( acpi_hdr );
f = buf ;
while ( buf [ 0 ]) {
struct stat s ;
int fd ;
896
char * n = strchr ( f , ':' );
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
if ( n )
* n = '\0' ;
fd = open ( f , O_RDONLY );
if ( fd < 0 )
goto out ;
if ( fstat ( fd , & s ) < 0 ) {
close ( fd );
goto out ;
}
do {
int r ;
r = read ( fd , p + off , s . st_size );
if ( r > 0 ) {
off += r ;
s . st_size -= r ;
} else if (( r < 0 && errno != EINTR ) || r == 0 ) {
close ( fd );
goto out ;
}
} while ( s . st_size );
close ( fd );
if ( ! n )
break ;
f = n + 1 ;
}
(( struct acpi_table_header * ) p ) -> checksum = acpi_checksum (( uint8_t * ) p , off );
/* increase number of tables */
( * ( uint16_t * ) acpi_tables ) =
cpu_to_le32 ( le32_to_cpu ( * ( uint16_t * ) acpi_tables ) + 1 );
return 0 ;
out :
if ( acpi_tables ) {
free ( acpi_tables );
acpi_tables = NULL ;
}
return - 1 ;
}