gwj / at91sam9263 · Commits

Commit 6515b203702b01cd7d4ef8f9cbad77474fc2ed42

Authored by bellard
1 parent 10765455

ACPI support 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1902 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 7 changed files with 1287 additions and 1 deletions
Makefile.target
  View file @6515b20
... ... @@ -316,7 +316,7 @@ ifeq ($(TARGET_BASE_ARCH), i386)
316 316 # Hardware support
317 317 VL_OBJS+= ide.o pckbd.o ps2.o vga.o $(SOUND_HW) dma.o $(AUDIODRV)
318 318 VL_OBJS+= fdc.o mc146818rtc.o serial.o i8259.o i8254.o pcspk.o pc.o
319   -VL_OBJS+= cirrus_vga.o mixeng.o apic.o parallel.o
  319 +VL_OBJS+= cirrus_vga.o mixeng.o apic.o parallel.o acpi.o
320 320 DEFINES += -DHAS_AUDIO
321 321 endif
322 322 ifeq ($(TARGET_BASE_ARCH), ppc)
... ... @@ -471,6 +471,11 @@ endif
471 471  
472 472 loader.o: loader.c elf_ops.h
473 473  
  474 +acpi.o: acpi.c acpi-dsdt.hex
  475 +
  476 +#$(SRC_PATH)/hw/acpi-dsdt.hex: acpi-dsdt.dsl
  477 +# iasl -tc -p $@ $<
  478 +
474 479 ifeq ($(TARGET_ARCH), sh4)
475 480 op.o: op.c op_mem.c cpu.h
476 481 op_helper.o: op_helper.c exec.h cpu.h
... ...
hw/acpi-dsdt.dsl 0 → 100644
  View file @6515b20
  1 +/*
  2 + * QEMU ACPI DSDT ASL definition
  3 + *
  4 + * Copyright (c) 2006 Fabrice Bellard
  5 + *
  6 + * This library is free software; you can redistribute it and/or
  7 + * modify it under the terms of the GNU Lesser General Public
  8 + * License version 2 as published by the Free Software Foundation.
  9 + *
  10 + * This library is distributed in the hope that it will be useful,
  11 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13 + * Lesser General Public License for more details.
  14 + *
  15 + * You should have received a copy of the GNU Lesser General Public
  16 + * License along with this library; if not, write to the Free Software
  17 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18 + */
  19 +DefinitionBlock (
  20 + "acpi-dsdt.aml", // Output Filename
  21 + "DSDT", // Signature
  22 + 0x01, // DSDT Compliance Revision
  23 + "QEMU", // OEMID
  24 + "QEMUDSDT", // TABLE ID
  25 + 0x1 // OEM Revision
  26 + )
  27 +{
  28 + Scope (\)
  29 + {
  30 + /* CMOS memory access */
  31 + OperationRegion (CMS, SystemIO, 0x70, 0x02)
  32 + Field (CMS, ByteAcc, NoLock, Preserve)
  33 + {
  34 + CMSI, 8,
  35 + CMSD, 8
  36 + }
  37 + Method (CMRD, 1, NotSerialized)
  38 + {
  39 + Store (Arg0, CMSI)
  40 + Store (CMSD, Local0)
  41 + Return (Local0)
  42 + }
  43 +
  44 + /* Debug Output */
  45 + OperationRegion (DBG, SystemIO, 0xb044, 0x04)
  46 + Field (DBG, DWordAcc, NoLock, Preserve)
  47 + {
  48 + DBGL, 32,
  49 + }
  50 + }
  51 +
  52 +
  53 + /* PCI Bus definition */
  54 + Scope(\_SB) {
  55 + Device(PCI0) {
  56 + Name (_HID, EisaId ("PNP0A03"))
  57 + Name (_ADR, 0x00)
  58 + Name (_UID, 1)
  59 + Name(_PRT, Package() {
  60 + /* PCI IRQ routing table, example from ACPI 2.0a specification,
  61 + section 6.2.8.1 */
  62 + /* Note: we provide the same info as the PCI routing
  63 + table of the Bochs BIOS */
  64 +
  65 + // PCI Slot 0
  66 + Package() {0x0000ffff, 0, LNKA, 0},
  67 + Package() {0x0000ffff, 1, LNKB, 0},
  68 + Package() {0x0000ffff, 2, LNKC, 0},
  69 + Package() {0x0000ffff, 3, LNKD, 0},
  70 +
  71 + // PCI Slot 1
  72 + Package() {0x0001ffff, 0, LNKB, 0},
  73 + Package() {0x0001ffff, 1, LNKC, 0},
  74 + Package() {0x0001ffff, 2, LNKD, 0},
  75 + Package() {0x0001ffff, 3, LNKA, 0},
  76 +
  77 + // PCI Slot 2
  78 + Package() {0x0002ffff, 0, LNKC, 0},
  79 + Package() {0x0002ffff, 1, LNKD, 0},
  80 + Package() {0x0002ffff, 2, LNKA, 0},
  81 + Package() {0x0002ffff, 3, LNKB, 0},
  82 +
  83 + // PCI Slot 3
  84 + Package() {0x0003ffff, 0, LNKD, 0},
  85 + Package() {0x0003ffff, 1, LNKA, 0},
  86 + Package() {0x0003ffff, 2, LNKB, 0},
  87 + Package() {0x0003ffff, 3, LNKC, 0},
  88 +
  89 + // PCI Slot 4
  90 + Package() {0x0004ffff, 0, LNKA, 0},
  91 + Package() {0x0004ffff, 1, LNKB, 0},
  92 + Package() {0x0004ffff, 2, LNKC, 0},
  93 + Package() {0x0004ffff, 3, LNKD, 0},
  94 +
  95 + // PCI Slot 5
  96 + Package() {0x0005ffff, 0, LNKB, 0},
  97 + Package() {0x0005ffff, 1, LNKC, 0},
  98 + Package() {0x0005ffff, 2, LNKD, 0},
  99 + Package() {0x0005ffff, 3, LNKA, 0},
  100 + })
  101 +
  102 + Method (_CRS, 0, NotSerialized)
  103 + {
  104 + Name (MEMP, ResourceTemplate ()
  105 + {
  106 + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
  107 + 0x0000, // Address Space Granularity
  108 + 0x0000, // Address Range Minimum
  109 + 0x00FF, // Address Range Maximum
  110 + 0x0000, // Address Translation Offset
  111 + 0x0100, // Address Length
  112 + ,, )
  113 + IO (Decode16,
  114 + 0x0CF8, // Address Range Minimum
  115 + 0x0CF8, // Address Range Maximum
  116 + 0x01, // Address Alignment
  117 + 0x08, // Address Length
  118 + )
  119 + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
  120 + 0x0000, // Address Space Granularity
  121 + 0x0000, // Address Range Minimum
  122 + 0x0CF7, // Address Range Maximum
  123 + 0x0000, // Address Translation Offset
  124 + 0x0CF8, // Address Length
  125 + ,, , TypeStatic)
  126 + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
  127 + 0x0000, // Address Space Granularity
  128 + 0x0D00, // Address Range Minimum
  129 + 0xFFFF, // Address Range Maximum
  130 + 0x0000, // Address Translation Offset
  131 + 0xF300, // Address Length
  132 + ,, , TypeStatic)
  133 + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
  134 + 0x00000000, // Address Space Granularity
  135 + 0x000A0000, // Address Range Minimum
  136 + 0x000BFFFF, // Address Range Maximum
  137 + 0x00000000, // Address Translation Offset
  138 + 0x00020000, // Address Length
  139 + ,, , AddressRangeMemory, TypeStatic)
  140 + DWordMemory (ResourceProducer, PosDecode, MinNotFixed, MaxFixed, NonCacheable, ReadWrite,
  141 + 0x00000000, // Address Space Granularity
  142 + 0x00000000, // Address Range Minimum
  143 + 0xFEBFFFFF, // Address Range Maximum
  144 + 0x00000000, // Address Translation Offset
  145 + 0x00000000, // Address Length
  146 + ,, MEMF, AddressRangeMemory, TypeStatic)
  147 + })
  148 + CreateDWordField (MEMP, \_SB.PCI0._CRS.MEMF._MIN, PMIN)
  149 + CreateDWordField (MEMP, \_SB.PCI0._CRS.MEMF._MAX, PMAX)
  150 + CreateDWordField (MEMP, \_SB.PCI0._CRS.MEMF._LEN, PLEN)
  151 + /* compute available RAM */
  152 + Add(CMRD(0x34), ShiftLeft(CMRD(0x35), 8), Local0)
  153 + ShiftLeft(Local0, 16, Local0)
  154 + Add(Local0, 0x1000000, Local0)
  155 + /* update field of last region */
  156 + Store(Local0, PMIN)
  157 + Subtract (PMAX, PMIN, PLEN)
  158 + Increment (PLEN)
  159 + Return (MEMP)
  160 + }
  161 + }
  162 + }
  163 +
  164 + /* PIIX3 ISA bridge */
  165 + Scope(\_SB.PCI0) {
  166 + Device (ISA) {
  167 + Name (_ADR, 0x00010000)
  168 +
  169 + /* PIIX PCI to ISA irq remapping */
  170 + OperationRegion (P40C, PCI_Config, 0x60, 0x04)
  171 +
  172 +
  173 + /* Keyboard seems to be important for WinXP install */
  174 + Device (KBD)
  175 + {
  176 + Name (_HID, EisaId ("PNP0303"))
  177 + Method (_STA, 0, NotSerialized)
  178 + {
  179 + Return (0x0f)
  180 + }
  181 +
  182 + Method (_CRS, 0, NotSerialized)
  183 + {
  184 + Name (TMP, ResourceTemplate ()
  185 + {
  186 + IO (Decode16,
  187 + 0x0060, // Address Range Minimum
  188 + 0x0060, // Address Range Maximum
  189 + 0x01, // Address Alignment
  190 + 0x01, // Address Length
  191 + )
  192 + IO (Decode16,
  193 + 0x0064, // Address Range Minimum
  194 + 0x0064, // Address Range Maximum
  195 + 0x01, // Address Alignment
  196 + 0x01, // Address Length
  197 + )
  198 + IRQNoFlags ()
  199 + {1}
  200 + })
  201 + Return (TMP)
  202 + }
  203 + }
  204 +
  205 + Device (MOU)
  206 + {
  207 + Name (_HID, EisaId ("PNP0F13"))
  208 + Method (_STA, 0, NotSerialized)
  209 + {
  210 + Return (0x0f)
  211 + }
  212 +
  213 + Method (_CRS, 0, NotSerialized)
  214 + {
  215 + Name (TMP, ResourceTemplate ()
  216 + {
  217 + IRQNoFlags () {12}
  218 + })
  219 + Return (TMP)
  220 + }
  221 + }
  222 + }
  223 + }
  224 +
  225 + /* PCI IRQs */
  226 + Scope(\_SB) {
  227 + Field (\_SB.PCI0.ISA.P40C, ByteAcc, NoLock, Preserve)
  228 + {
  229 + PRQ0, 8,
  230 + PRQ1, 8,
  231 + PRQ2, 8,
  232 + PRQ3, 8
  233 + }
  234 +
  235 + Device(LNKA){
  236 + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
  237 + Name(_UID, 1)
  238 + Name(_PRS, ResourceTemplate(){
  239 + IRQ (Level, ActiveLow, Shared)
  240 + {3,4,5,6,7,9,10,11,12}
  241 + })
  242 + Method (_STA, 0, NotSerialized)
  243 + {
  244 + Store (0x0B, Local0)
  245 + If (And (0x80, PRQ0, Local1))
  246 + {
  247 + Store (0x09, Local0)
  248 + }
  249 + Return (Local0)
  250 + }
  251 + Method (_DIS, 0, NotSerialized)
  252 + {
  253 + Or (PRQ0, 0x80, PRQ0)
  254 + }
  255 + Method (_CRS, 0, NotSerialized)
  256 + {
  257 + Name (PRR0, ResourceTemplate ()
  258 + {
  259 + IRQ (Level, ActiveLow, Shared)
  260 + {1}
  261 + })
  262 + CreateWordField (PRR0, 0x01, TMP)
  263 + Store (PRQ0, Local0)
  264 + If (LLess (Local0, 0x80))
  265 + {
  266 + ShiftLeft (One, Local0, TMP)
  267 + }
  268 + Else
  269 + {
  270 + Store (Zero, TMP)
  271 + }
  272 + Return (PRR0)
  273 + }
  274 + Method (_SRS, 1, NotSerialized)
  275 + {
  276 + CreateWordField (Arg0, 0x01, TMP)
  277 + FindSetRightBit (TMP, Local0)
  278 + Decrement (Local0)
  279 + Store (Local0, PRQ0)
  280 + }
  281 + }
  282 + Device(LNKB){
  283 + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
  284 + Name(_UID, 2)
  285 + Name(_PRS, ResourceTemplate(){
  286 + IRQ (Level, ActiveLow, Shared)
  287 + {3,4,5,6,7,9,10,11,12}
  288 + })
  289 + Method (_STA, 0, NotSerialized)
  290 + {
  291 + Store (0x0B, Local0)
  292 + If (And (0x80, PRQ1, Local1))
  293 + {
  294 + Store (0x09, Local0)
  295 + }
  296 + Return (Local0)
  297 + }
  298 + Method (_DIS, 0, NotSerialized)
  299 + {
  300 + Or (PRQ1, 0x80, PRQ1)
  301 + }
  302 + Method (_CRS, 0, NotSerialized)
  303 + {
  304 + Name (PRR0, ResourceTemplate ()
  305 + {
  306 + IRQ (Level, ActiveLow, Shared)
  307 + {1}
  308 + })
  309 + CreateWordField (PRR0, 0x01, TMP)
  310 + Store (PRQ1, Local0)
  311 + If (LLess (Local0, 0x80))
  312 + {
  313 + ShiftLeft (One, Local0, TMP)
  314 + }
  315 + Else
  316 + {
  317 + Store (Zero, TMP)
  318 + }
  319 + Return (PRR0)
  320 + }
  321 + Method (_SRS, 1, NotSerialized)
  322 + {
  323 + CreateWordField (Arg0, 0x01, TMP)
  324 + FindSetRightBit (TMP, Local0)
  325 + Decrement (Local0)
  326 + Store (Local0, PRQ1)
  327 + }
  328 + }
  329 + Device(LNKC){
  330 + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
  331 + Name(_UID, 3)
  332 + Name(_PRS, ResourceTemplate(){
  333 + IRQ (Level, ActiveLow, Shared)
  334 + {3,4,5,6,7,9,10,11,12}
  335 + })
  336 + Method (_STA, 0, NotSerialized)
  337 + {
  338 + Store (0x0B, Local0)
  339 + If (And (0x80, PRQ2, Local1))
  340 + {
  341 + Store (0x09, Local0)
  342 + }
  343 + Return (Local0)
  344 + }
  345 + Method (_DIS, 0, NotSerialized)
  346 + {
  347 + Or (PRQ2, 0x80, PRQ2)
  348 + }
  349 + Method (_CRS, 0, NotSerialized)
  350 + {
  351 + Name (PRR0, ResourceTemplate ()
  352 + {
  353 + IRQ (Level, ActiveLow, Shared)
  354 + {1}
  355 + })
  356 + CreateWordField (PRR0, 0x01, TMP)
  357 + Store (PRQ2, Local0)
  358 + If (LLess (Local0, 0x80))
  359 + {
  360 + ShiftLeft (One, Local0, TMP)
  361 + }
  362 + Else
  363 + {
  364 + Store (Zero, TMP)
  365 + }
  366 + Return (PRR0)
  367 + }
  368 + Method (_SRS, 1, NotSerialized)
  369 + {
  370 + CreateWordField (Arg0, 0x01, TMP)
  371 + FindSetRightBit (TMP, Local0)
  372 + Decrement (Local0)
  373 + Store (Local0, PRQ2)
  374 + }
  375 + }
  376 + Device(LNKD){
  377 + Name(_HID, EISAID("PNP0C0F")) // PCI interrupt link
  378 + Name(_UID, 4)
  379 + Name(_PRS, ResourceTemplate(){
  380 + IRQ (Level, ActiveLow, Shared)
  381 + {3,4,5,6,7,9,10,11,12}
  382 + })
  383 + Method (_STA, 0, NotSerialized)
  384 + {
  385 + Store (0x0B, Local0)
  386 + If (And (0x80, PRQ3, Local1))
  387 + {
  388 + Store (0x09, Local0)
  389 + }
  390 + Return (Local0)
  391 + }
  392 + Method (_DIS, 0, NotSerialized)
  393 + {
  394 + Or (PRQ3, 0x80, PRQ3)
  395 + }
  396 + Method (_CRS, 0, NotSerialized)
  397 + {
  398 + Name (PRR0, ResourceTemplate ()
  399 + {
  400 + IRQ (Level, ActiveLow, Shared)
  401 + {1}
  402 + })
  403 + CreateWordField (PRR0, 0x01, TMP)
  404 + Store (PRQ3, Local0)
  405 + If (LLess (Local0, 0x80))
  406 + {
  407 + ShiftLeft (One, Local0, TMP)
  408 + }
  409 + Else
  410 + {
  411 + Store (Zero, TMP)
  412 + }
  413 + Return (PRR0)
  414 + }
  415 + Method (_SRS, 1, NotSerialized)
  416 + {
  417 + CreateWordField (Arg0, 0x01, TMP)
  418 + FindSetRightBit (TMP, Local0)
  419 + Decrement (Local0)
  420 + Store (Local0, PRQ3)
  421 + }
  422 + }
  423 + }
  424 +
  425 + /* S5 = power off state */
  426 + Name (_S5, Package (4) {
  427 + 0x00, // PM1a_CNT.SLP_TYP
  428 + 0x00, // PM2a_CNT.SLP_TYP
  429 + 0x00, // reserved
  430 + 0x00, // reserved
  431 + })
  432 +}
... ...
hw/acpi-dsdt.hex 0 → 100644
  View file @6515b20
  1 +/*
  2 + *
  3 + * Intel ACPI Component Architecture
  4 + * ASL Optimizing Compiler version 20060421 [Apr 29 2006]
  5 + * Copyright (C) 2000 - 2006 Intel Corporation
  6 + * Supports ACPI Specification Revision 3.0a
  7 + *
  8 + * Compilation of "/usr/local/home/bellard/qemu-current/hw/acpi-dsdt.dsl" - Wed May 3 22:49:16 2006
  9 + *
  10 + * C source code output
  11 + *
  12 + */
  13 +unsigned char AmlCode[] =
  14 +{
  15 + 0x44,0x53,0x44,0x54,0x73,0x06,0x00,0x00, /* 00000000 "DSDTs..." */
  16 + 0x01,0x39,0x51,0x45,0x4D,0x55,0x00,0x00, /* 00000008 ".9QEMU.." */
  17 + 0x51,0x45,0x4D,0x55,0x44,0x53,0x44,0x54, /* 00000010 "QEMUDSDT" */
  18 + 0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */
  19 + 0x21,0x04,0x06,0x20,0x10,0x4F,0x04,0x5C, /* 00000020 "!.. .O.\" */
  20 + 0x00,0x5B,0x80,0x43,0x4D,0x53,0x5F,0x01, /* 00000028 ".[.CMS_." */
  21 + 0x0A,0x70,0x0A,0x02,0x5B,0x81,0x10,0x43, /* 00000030 ".p..[..C" */
  22 + 0x4D,0x53,0x5F,0x01,0x43,0x4D,0x53,0x49, /* 00000038 "MS_.CMSI" */
  23 + 0x08,0x43,0x4D,0x53,0x44,0x08,0x14,0x14, /* 00000040 ".CMSD..." */
  24 + 0x43,0x4D,0x52,0x44,0x01,0x70,0x68,0x43, /* 00000048 "CMRD.phC" */
  25 + 0x4D,0x53,0x49,0x70,0x43,0x4D,0x53,0x44, /* 00000050 "MSIpCMSD" */
  26 + 0x60,0xA4,0x60,0x5B,0x80,0x44,0x42,0x47, /* 00000058 "`.`[.DBG" */
  27 + 0x5F,0x01,0x0B,0x44,0xB0,0x0A,0x04,0x5B, /* 00000060 "_..D...[" */
  28 + 0x81,0x0B,0x44,0x42,0x47,0x5F,0x03,0x44, /* 00000068 "..DBG_.D" */
  29 + 0x42,0x47,0x4C,0x20,0x10,0x4E,0x25,0x5F, /* 00000070 "BGL .N%_" */
  30 + 0x53,0x42,0x5F,0x5B,0x82,0x46,0x25,0x50, /* 00000078 "SB_[.F%P" */
  31 + 0x43,0x49,0x30,0x08,0x5F,0x48,0x49,0x44, /* 00000080 "CI0._HID" */
  32 + 0x0C,0x41,0xD0,0x0A,0x03,0x08,0x5F,0x41, /* 00000088 ".A...._A" */
  33 + 0x44,0x52,0x00,0x08,0x5F,0x55,0x49,0x44, /* 00000090 "DR.._UID" */
  34 + 0x01,0x08,0x5F,0x50,0x52,0x54,0x12,0x47, /* 00000098 ".._PRT.G" */
  35 + 0x15,0x18,0x12,0x0B,0x04,0x0B,0xFF,0xFF, /* 000000A0 "........" */
  36 + 0x00,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0B, /* 000000A8 ".LNKA..." */
  37 + 0x04,0x0B,0xFF,0xFF,0x01,0x4C,0x4E,0x4B, /* 000000B0 ".....LNK" */
  38 + 0x42,0x00,0x12,0x0C,0x04,0x0B,0xFF,0xFF, /* 000000B8 "B......." */
  39 + 0x0A,0x02,0x4C,0x4E,0x4B,0x43,0x00,0x12, /* 000000C0 "..LNKC.." */
  40 + 0x0C,0x04,0x0B,0xFF,0xFF,0x0A,0x03,0x4C, /* 000000C8 ".......L" */
  41 + 0x4E,0x4B,0x44,0x00,0x12,0x0D,0x04,0x0C, /* 000000D0 "NKD....." */
  42 + 0xFF,0xFF,0x01,0x00,0x00,0x4C,0x4E,0x4B, /* 000000D8 ".....LNK" */
  43 + 0x42,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 000000E0 "B......." */
  44 + 0x01,0x00,0x01,0x4C,0x4E,0x4B,0x43,0x00, /* 000000E8 "...LNKC." */
  45 + 0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x01,0x00, /* 000000F0 "........" */
  46 + 0x0A,0x02,0x4C,0x4E,0x4B,0x44,0x00,0x12, /* 000000F8 "..LNKD.." */
  47 + 0x0E,0x04,0x0C,0xFF,0xFF,0x01,0x00,0x0A, /* 00000100 "........" */
  48 + 0x03,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D, /* 00000108 ".LNKA..." */
  49 + 0x04,0x0C,0xFF,0xFF,0x02,0x00,0x00,0x4C, /* 00000110 ".......L" */
  50 + 0x4E,0x4B,0x43,0x00,0x12,0x0D,0x04,0x0C, /* 00000118 "NKC....." */
  51 + 0xFF,0xFF,0x02,0x00,0x01,0x4C,0x4E,0x4B, /* 00000120 ".....LNK" */
  52 + 0x44,0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF, /* 00000128 "D......." */
  53 + 0x02,0x00,0x0A,0x02,0x4C,0x4E,0x4B,0x41, /* 00000130 "....LNKA" */
  54 + 0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x02, /* 00000138 "........" */
  55 + 0x00,0x0A,0x03,0x4C,0x4E,0x4B,0x42,0x00, /* 00000140 "...LNKB." */
  56 + 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x03,0x00, /* 00000148 "........" */
  57 + 0x00,0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0D, /* 00000150 ".LNKD..." */
  58 + 0x04,0x0C,0xFF,0xFF,0x03,0x00,0x01,0x4C, /* 00000158 ".......L" */
  59 + 0x4E,0x4B,0x41,0x00,0x12,0x0E,0x04,0x0C, /* 00000160 "NKA....." */
  60 + 0xFF,0xFF,0x03,0x00,0x0A,0x02,0x4C,0x4E, /* 00000168 "......LN" */
  61 + 0x4B,0x42,0x00,0x12,0x0E,0x04,0x0C,0xFF, /* 00000170 "KB......" */
  62 + 0xFF,0x03,0x00,0x0A,0x03,0x4C,0x4E,0x4B, /* 00000178 ".....LNK" */
  63 + 0x43,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 00000180 "C......." */
  64 + 0x04,0x00,0x00,0x4C,0x4E,0x4B,0x41,0x00, /* 00000188 "...LNKA." */
  65 + 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x04,0x00, /* 00000190 "........" */
  66 + 0x01,0x4C,0x4E,0x4B,0x42,0x00,0x12,0x0E, /* 00000198 ".LNKB..." */
  67 + 0x04,0x0C,0xFF,0xFF,0x04,0x00,0x0A,0x02, /* 000001A0 "........" */
  68 + 0x4C,0x4E,0x4B,0x43,0x00,0x12,0x0E,0x04, /* 000001A8 "LNKC...." */
  69 + 0x0C,0xFF,0xFF,0x04,0x00,0x0A,0x03,0x4C, /* 000001B0 ".......L" */
  70 + 0x4E,0x4B,0x44,0x00,0x12,0x0D,0x04,0x0C, /* 000001B8 "NKD....." */
  71 + 0xFF,0xFF,0x05,0x00,0x00,0x4C,0x4E,0x4B, /* 000001C0 ".....LNK" */
  72 + 0x42,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF, /* 000001C8 "B......." */
  73 + 0x05,0x00,0x01,0x4C,0x4E,0x4B,0x43,0x00, /* 000001D0 "...LNKC." */
  74 + 0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x05,0x00, /* 000001D8 "........" */
  75 + 0x0A,0x02,0x4C,0x4E,0x4B,0x44,0x00,0x12, /* 000001E0 "..LNKD.." */
  76 + 0x0E,0x04,0x0C,0xFF,0xFF,0x05,0x00,0x0A, /* 000001E8 "........" */
  77 + 0x03,0x4C,0x4E,0x4B,0x41,0x00,0x14,0x4C, /* 000001F0 ".LNKA..L" */
  78 + 0x0D,0x5F,0x43,0x52,0x53,0x00,0x08,0x4D, /* 000001F8 "._CRS..M" */
  79 + 0x45,0x4D,0x50,0x11,0x42,0x07,0x0A,0x6E, /* 00000200 "EMP.B..n" */
  80 + 0x88,0x0D,0x00,0x02,0x0C,0x00,0x00,0x00, /* 00000208 "........" */
  81 + 0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x01, /* 00000210 "........" */
  82 + 0x47,0x01,0xF8,0x0C,0xF8,0x0C,0x01,0x08, /* 00000218 "G......." */
  83 + 0x88,0x0D,0x00,0x01,0x0C,0x03,0x00,0x00, /* 00000220 "........" */
  84 + 0x00,0x00,0xF7,0x0C,0x00,0x00,0xF8,0x0C, /* 00000228 "........" */
  85 + 0x88,0x0D,0x00,0x01,0x0C,0x03,0x00,0x00, /* 00000230 "........" */
  86 + 0x00,0x0D,0xFF,0xFF,0x00,0x00,0x00,0xF3, /* 00000238 "........" */
  87 + 0x87,0x17,0x00,0x00,0x0C,0x03,0x00,0x00, /* 00000240 "........" */
  88 + 0x00,0x00,0x00,0x00,0x0A,0x00,0xFF,0xFF, /* 00000248 "........" */
  89 + 0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000250 "........" */
  90 + 0x02,0x00,0x87,0x17,0x00,0x00,0x08,0x01, /* 00000258 "........" */
  91 + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* 00000260 "........" */
  92 + 0xFF,0xFF,0xBF,0xFE,0x00,0x00,0x00,0x00, /* 00000268 "........" */
  93 + 0x00,0x00,0x00,0x00,0x79,0x00,0x8A,0x4D, /* 00000270 "....y..M" */
  94 + 0x45,0x4D,0x50,0x0A,0x5C,0x50,0x4D,0x49, /* 00000278 "EMP.\PMI" */
  95 + 0x4E,0x8A,0x4D,0x45,0x4D,0x50,0x0A,0x60, /* 00000280 "N.MEMP.`" */
  96 + 0x50,0x4D,0x41,0x58,0x8A,0x4D,0x45,0x4D, /* 00000288 "PMAX.MEM" */
  97 + 0x50,0x0A,0x68,0x50,0x4C,0x45,0x4E,0x72, /* 00000290 "P.hPLENr" */
  98 + 0x43,0x4D,0x52,0x44,0x0A,0x34,0x79,0x43, /* 00000298 "CMRD.4yC" */
  99 + 0x4D,0x52,0x44,0x0A,0x35,0x0A,0x08,0x00, /* 000002A0 "MRD.5..." */
  100 + 0x60,0x79,0x60,0x0A,0x10,0x60,0x72,0x60, /* 000002A8 "`y`..`r`" */
  101 + 0x0C,0x00,0x00,0x00,0x01,0x60,0x70,0x60, /* 000002B0 ".....`p`" */
  102 + 0x50,0x4D,0x49,0x4E,0x74,0x50,0x4D,0x41, /* 000002B8 "PMINtPMA" */
  103 + 0x58,0x50,0x4D,0x49,0x4E,0x50,0x4C,0x45, /* 000002C0 "XPMINPLE" */
  104 + 0x4E,0x75,0x50,0x4C,0x45,0x4E,0xA4,0x4D, /* 000002C8 "NuPLEN.M" */
  105 + 0x45,0x4D,0x50,0x10,0x43,0x0A,0x2E,0x5F, /* 000002D0 "EMP.C.._" */
  106 + 0x53,0x42,0x5F,0x50,0x43,0x49,0x30,0x5B, /* 000002D8 "SB_PCI0[" */
  107 + 0x82,0x46,0x09,0x49,0x53,0x41,0x5F,0x08, /* 000002E0 ".F.ISA_." */
  108 + 0x5F,0x41,0x44,0x52,0x0C,0x00,0x00,0x01, /* 000002E8 "_ADR...." */
  109 + 0x00,0x5B,0x80,0x50,0x34,0x30,0x43,0x02, /* 000002F0 ".[.P40C." */
  110 + 0x0A,0x60,0x0A,0x04,0x5B,0x82,0x44,0x04, /* 000002F8 ".`..[.D." */
  111 + 0x4B,0x42,0x44,0x5F,0x08,0x5F,0x48,0x49, /* 00000300 "KBD_._HI" */
  112 + 0x44,0x0C,0x41,0xD0,0x03,0x03,0x14,0x09, /* 00000308 "D.A....." */
  113 + 0x5F,0x53,0x54,0x41,0x00,0xA4,0x0A,0x0F, /* 00000310 "_STA...." */
  114 + 0x14,0x29,0x5F,0x43,0x52,0x53,0x00,0x08, /* 00000318 ".)_CRS.." */
  115 + 0x54,0x4D,0x50,0x5F,0x11,0x18,0x0A,0x15, /* 00000320 "TMP_...." */
  116 + 0x47,0x01,0x60,0x00,0x60,0x00,0x01,0x01, /* 00000328 "G.`.`..." */
  117 + 0x47,0x01,0x64,0x00,0x64,0x00,0x01,0x01, /* 00000330 "G.d.d..." */
  118 + 0x22,0x02,0x00,0x79,0x00,0xA4,0x54,0x4D, /* 00000338 ""..y..TM" */
  119 + 0x50,0x5F,0x5B,0x82,0x33,0x4D,0x4F,0x55, /* 00000340 "P_[.3MOU" */
  120 + 0x5F,0x08,0x5F,0x48,0x49,0x44,0x0C,0x41, /* 00000348 "_._HID.A" */
  121 + 0xD0,0x0F,0x13,0x14,0x09,0x5F,0x53,0x54, /* 00000350 "....._ST" */
  122 + 0x41,0x00,0xA4,0x0A,0x0F,0x14,0x19,0x5F, /* 00000358 "A......_" */
  123 + 0x43,0x52,0x53,0x00,0x08,0x54,0x4D,0x50, /* 00000360 "CRS..TMP" */
  124 + 0x5F,0x11,0x08,0x0A,0x05,0x22,0x00,0x10, /* 00000368 "_....".." */
  125 + 0x79,0x00,0xA4,0x54,0x4D,0x50,0x5F,0x10, /* 00000370 "y..TMP_." */
  126 + 0x4F,0x2E,0x5F,0x53,0x42,0x5F,0x5B,0x81, /* 00000378 "O._SB_[." */
  127 + 0x24,0x2F,0x03,0x50,0x43,0x49,0x30,0x49, /* 00000380 "$/.PCI0I" */
  128 + 0x53,0x41,0x5F,0x50,0x34,0x30,0x43,0x01, /* 00000388 "SA_P40C." */
  129 + 0x50,0x52,0x51,0x30,0x08,0x50,0x52,0x51, /* 00000390 "PRQ0.PRQ" */
  130 + 0x31,0x08,0x50,0x52,0x51,0x32,0x08,0x50, /* 00000398 "1.PRQ2.P" */
  131 + 0x52,0x51,0x33,0x08,0x5B,0x82,0x4E,0x0A, /* 000003A0 "RQ3.[.N." */
  132 + 0x4C,0x4E,0x4B,0x41,0x08,0x5F,0x48,0x49, /* 000003A8 "LNKA._HI" */
  133 + 0x44,0x0C,0x41,0xD0,0x0C,0x0F,0x08,0x5F, /* 000003B0 "D.A...._" */
  134 + 0x55,0x49,0x44,0x01,0x08,0x5F,0x50,0x52, /* 000003B8 "UID.._PR" */
  135 + 0x53,0x11,0x09,0x0A,0x06,0x23,0xF8,0x1E, /* 000003C0 "S....#.." */
  136 + 0x18,0x79,0x00,0x14,0x1A,0x5F,0x53,0x54, /* 000003C8 ".y..._ST" */
  137 + 0x41,0x00,0x70,0x0A,0x0B,0x60,0xA0,0x0D, /* 000003D0 "A.p..`.." */
  138 + 0x7B,0x0A,0x80,0x50,0x52,0x51,0x30,0x61, /* 000003D8 "{..PRQ0a" */
  139 + 0x70,0x0A,0x09,0x60,0xA4,0x60,0x14,0x11, /* 000003E0 "p..`.`.." */
  140 + 0x5F,0x44,0x49,0x53,0x00,0x7D,0x50,0x52, /* 000003E8 "_DIS.}PR" */
  141 + 0x51,0x30,0x0A,0x80,0x50,0x52,0x51,0x30, /* 000003F0 "Q0..PRQ0" */
  142 + 0x14,0x3F,0x5F,0x43,0x52,0x53,0x00,0x08, /* 000003F8 ".?_CRS.." */
  143 + 0x50,0x52,0x52,0x30,0x11,0x09,0x0A,0x06, /* 00000400 "PRR0...." */
  144 + 0x23,0x02,0x00,0x18,0x79,0x00,0x8B,0x50, /* 00000408 "#...y..P" */
  145 + 0x52,0x52,0x30,0x01,0x54,0x4D,0x50,0x5F, /* 00000410 "RR0.TMP_" */
  146 + 0x70,0x50,0x52,0x51,0x30,0x60,0xA0,0x0C, /* 00000418 "pPRQ0`.." */
  147 + 0x95,0x60,0x0A,0x80,0x79,0x01,0x60,0x54, /* 00000420 ".`..y.`T" */
  148 + 0x4D,0x50,0x5F,0xA1,0x07,0x70,0x00,0x54, /* 00000428 "MP_..p.T" */
  149 + 0x4D,0x50,0x5F,0xA4,0x50,0x52,0x52,0x30, /* 00000430 "MP_.PRR0" */
  150 + 0x14,0x1B,0x5F,0x53,0x52,0x53,0x01,0x8B, /* 00000438 ".._SRS.." */
  151 + 0x68,0x01,0x54,0x4D,0x50,0x5F,0x82,0x54, /* 00000440 "h.TMP_.T" */
  152 + 0x4D,0x50,0x5F,0x60,0x76,0x60,0x70,0x60, /* 00000448 "MP_`v`p`" */
  153 + 0x50,0x52,0x51,0x30,0x5B,0x82,0x4F,0x0A, /* 00000450 "PRQ0[.O." */
  154 + 0x4C,0x4E,0x4B,0x42,0x08,0x5F,0x48,0x49, /* 00000458 "LNKB._HI" */
  155 + 0x44,0x0C,0x41,0xD0,0x0C,0x0F,0x08,0x5F, /* 00000460 "D.A...._" */
  156 + 0x55,0x49,0x44,0x0A,0x02,0x08,0x5F,0x50, /* 00000468 "UID..._P" */
  157 + 0x52,0x53,0x11,0x09,0x0A,0x06,0x23,0xF8, /* 00000470 "RS....#." */
  158 + 0x1E,0x18,0x79,0x00,0x14,0x1A,0x5F,0x53, /* 00000478 "..y..._S" */
  159 + 0x54,0x41,0x00,0x70,0x0A,0x0B,0x60,0xA0, /* 00000480 "TA.p..`." */
  160 + 0x0D,0x7B,0x0A,0x80,0x50,0x52,0x51,0x31, /* 00000488 ".{..PRQ1" */
  161 + 0x61,0x70,0x0A,0x09,0x60,0xA4,0x60,0x14, /* 00000490 "ap..`.`." */
  162 + 0x11,0x5F,0x44,0x49,0x53,0x00,0x7D,0x50, /* 00000498 "._DIS.}P" */
  163 + 0x52,0x51,0x31,0x0A,0x80,0x50,0x52,0x51, /* 000004A0 "RQ1..PRQ" */
  164 + 0x31,0x14,0x3F,0x5F,0x43,0x52,0x53,0x00, /* 000004A8 "1.?_CRS." */
  165 + 0x08,0x50,0x52,0x52,0x30,0x11,0x09,0x0A, /* 000004B0 ".PRR0..." */
  166 + 0x06,0x23,0x02,0x00,0x18,0x79,0x00,0x8B, /* 000004B8 ".#...y.." */
  167 + 0x50,0x52,0x52,0x30,0x01,0x54,0x4D,0x50, /* 000004C0 "PRR0.TMP" */
  168 + 0x5F,0x70,0x50,0x52,0x51,0x31,0x60,0xA0, /* 000004C8 "_pPRQ1`." */
  169 + 0x0C,0x95,0x60,0x0A,0x80,0x79,0x01,0x60, /* 000004D0 "..`..y.`" */
  170 + 0x54,0x4D,0x50,0x5F,0xA1,0x07,0x70,0x00, /* 000004D8 "TMP_..p." */
  171 + 0x54,0x4D,0x50,0x5F,0xA4,0x50,0x52,0x52, /* 000004E0 "TMP_.PRR" */
  172 + 0x30,0x14,0x1B,0x5F,0x53,0x52,0x53,0x01, /* 000004E8 "0.._SRS." */
  173 + 0x8B,0x68,0x01,0x54,0x4D,0x50,0x5F,0x82, /* 000004F0 ".h.TMP_." */
  174 + 0x54,0x4D,0x50,0x5F,0x60,0x76,0x60,0x70, /* 000004F8 "TMP_`v`p" */
  175 + 0x60,0x50,0x52,0x51,0x31,0x5B,0x82,0x4F, /* 00000500 "`PRQ1[.O" */
  176 + 0x0A,0x4C,0x4E,0x4B,0x43,0x08,0x5F,0x48, /* 00000508 ".LNKC._H" */
  177 + 0x49,0x44,0x0C,0x41,0xD0,0x0C,0x0F,0x08, /* 00000510 "ID.A...." */
  178 + 0x5F,0x55,0x49,0x44,0x0A,0x03,0x08,0x5F, /* 00000518 "_UID..._" */
  179 + 0x50,0x52,0x53,0x11,0x09,0x0A,0x06,0x23, /* 00000520 "PRS....#" */
  180 + 0xF8,0x1E,0x18,0x79,0x00,0x14,0x1A,0x5F, /* 00000528 "...y..._" */
  181 + 0x53,0x54,0x41,0x00,0x70,0x0A,0x0B,0x60, /* 00000530 "STA.p..`" */
  182 + 0xA0,0x0D,0x7B,0x0A,0x80,0x50,0x52,0x51, /* 00000538 "..{..PRQ" */
  183 + 0x32,0x61,0x70,0x0A,0x09,0x60,0xA4,0x60, /* 00000540 "2ap..`.`" */
  184 + 0x14,0x11,0x5F,0x44,0x49,0x53,0x00,0x7D, /* 00000548 ".._DIS.}" */
  185 + 0x50,0x52,0x51,0x32,0x0A,0x80,0x50,0x52, /* 00000550 "PRQ2..PR" */
  186 + 0x51,0x32,0x14,0x3F,0x5F,0x43,0x52,0x53, /* 00000558 "Q2.?_CRS" */
  187 + 0x00,0x08,0x50,0x52,0x52,0x30,0x11,0x09, /* 00000560 "..PRR0.." */
  188 + 0x0A,0x06,0x23,0x02,0x00,0x18,0x79,0x00, /* 00000568 "..#...y." */
  189 + 0x8B,0x50,0x52,0x52,0x30,0x01,0x54,0x4D, /* 00000570 ".PRR0.TM" */
  190 + 0x50,0x5F,0x70,0x50,0x52,0x51,0x32,0x60, /* 00000578 "P_pPRQ2`" */
  191 + 0xA0,0x0C,0x95,0x60,0x0A,0x80,0x79,0x01, /* 00000580 "...`..y." */
  192 + 0x60,0x54,0x4D,0x50,0x5F,0xA1,0x07,0x70, /* 00000588 "`TMP_..p" */
  193 + 0x00,0x54,0x4D,0x50,0x5F,0xA4,0x50,0x52, /* 00000590 ".TMP_.PR" */
  194 + 0x52,0x30,0x14,0x1B,0x5F,0x53,0x52,0x53, /* 00000598 "R0.._SRS" */
  195 + 0x01,0x8B,0x68,0x01,0x54,0x4D,0x50,0x5F, /* 000005A0 "..h.TMP_" */
  196 + 0x82,0x54,0x4D,0x50,0x5F,0x60,0x76,0x60, /* 000005A8 ".TMP_`v`" */
  197 + 0x70,0x60,0x50,0x52,0x51,0x32,0x5B,0x82, /* 000005B0 "p`PRQ2[." */
  198 + 0x4F,0x0A,0x4C,0x4E,0x4B,0x44,0x08,0x5F, /* 000005B8 "O.LNKD._" */
  199 + 0x48,0x49,0x44,0x0C,0x41,0xD0,0x0C,0x0F, /* 000005C0 "HID.A..." */
  200 + 0x08,0x5F,0x55,0x49,0x44,0x0A,0x04,0x08, /* 000005C8 "._UID..." */
  201 + 0x5F,0x50,0x52,0x53,0x11,0x09,0x0A,0x06, /* 000005D0 "_PRS...." */
  202 + 0x23,0xF8,0x1E,0x18,0x79,0x00,0x14,0x1A, /* 000005D8 "#...y..." */
  203 + 0x5F,0x53,0x54,0x41,0x00,0x70,0x0A,0x0B, /* 000005E0 "_STA.p.." */
  204 + 0x60,0xA0,0x0D,0x7B,0x0A,0x80,0x50,0x52, /* 000005E8 "`..{..PR" */
  205 + 0x51,0x33,0x61,0x70,0x0A,0x09,0x60,0xA4, /* 000005F0 "Q3ap..`." */
  206 + 0x60,0x14,0x11,0x5F,0x44,0x49,0x53,0x00, /* 000005F8 "`.._DIS." */
  207 + 0x7D,0x50,0x52,0x51,0x33,0x0A,0x80,0x50, /* 00000600 "}PRQ3..P" */
  208 + 0x52,0x51,0x33,0x14,0x3F,0x5F,0x43,0x52, /* 00000608 "RQ3.?_CR" */
  209 + 0x53,0x00,0x08,0x50,0x52,0x52,0x30,0x11, /* 00000610 "S..PRR0." */
  210 + 0x09,0x0A,0x06,0x23,0x02,0x00,0x18,0x79, /* 00000618 "...#...y" */
  211 + 0x00,0x8B,0x50,0x52,0x52,0x30,0x01,0x54, /* 00000620 "..PRR0.T" */
  212 + 0x4D,0x50,0x5F,0x70,0x50,0x52,0x51,0x33, /* 00000628 "MP_pPRQ3" */
  213 + 0x60,0xA0,0x0C,0x95,0x60,0x0A,0x80,0x79, /* 00000630 "`...`..y" */
  214 + 0x01,0x60,0x54,0x4D,0x50,0x5F,0xA1,0x07, /* 00000638 ".`TMP_.." */
  215 + 0x70,0x00,0x54,0x4D,0x50,0x5F,0xA4,0x50, /* 00000640 "p.TMP_.P" */
  216 + 0x52,0x52,0x30,0x14,0x1B,0x5F,0x53,0x52, /* 00000648 "RR0.._SR" */
  217 + 0x53,0x01,0x8B,0x68,0x01,0x54,0x4D,0x50, /* 00000650 "S..h.TMP" */
  218 + 0x5F,0x82,0x54,0x4D,0x50,0x5F,0x60,0x76, /* 00000658 "_.TMP_`v" */
  219 + 0x60,0x70,0x60,0x50,0x52,0x51,0x33,0x08, /* 00000660 "`p`PRQ3." */
  220 + 0x5F,0x53,0x35,0x5F,0x12,0x06,0x04,0x00, /* 00000668 "_S5_...." */
  221 + 0x00,0x00,0x00,
  222 +};
... ...
hw/acpi.c 0 → 100644
  View file @6515b20
  1 +/*
  2 + * ACPI implementation
  3 + *
  4 + * Copyright (c) 2006 Fabrice Bellard
  5 + *
  6 + * This library is free software; you can redistribute it and/or
  7 + * modify it under the terms of the GNU Lesser General Public
  8 + * License version 2 as published by the Free Software Foundation.
  9 + *
  10 + * This library is distributed in the hope that it will be useful,
  11 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13 + * Lesser General Public License for more details.
  14 + *
  15 + * You should have received a copy of the GNU Lesser General Public
  16 + * License along with this library; if not, write to the Free Software
  17 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18 + */
  19 +#include "vl.h"
  20 +
  21 +//#define DEBUG
  22 +
  23 +/* i82731AB (PIIX4) compatible power management function */
  24 +#define PM_FREQ 3579545
  25 +
  26 +/* XXX: make them variable */
  27 +#define PM_IO_BASE 0xb000
  28 +#define SMI_CMD_IO_ADDR 0xb040
  29 +#define ACPI_DBG_IO_ADDR 0xb044
  30 +
  31 +typedef struct PIIX4PMState {
  32 + PCIDevice dev;
  33 + uint16_t pmsts;
  34 + uint16_t pmen;
  35 + uint16_t pmcntrl;
  36 + QEMUTimer *tmr_timer;
  37 + int64_t tmr_overflow_time;
  38 +} PIIX4PMState;
  39 +
  40 +#define RTC_EN (1 << 10)
  41 +#define PWRBTN_EN (1 << 8)
  42 +#define GBL_EN (1 << 5)
  43 +#define TMROF_EN (1 << 0)
  44 +
  45 +#define SCI_EN (1 << 0)
  46 +
  47 +#define SUS_EN (1 << 13)
  48 +
  49 +/* Note: only used for ACPI bios init. Could be deleted when ACPI init
  50 + is integrated in Bochs BIOS */
  51 +static PIIX4PMState *piix4_pm_state;
  52 +
  53 +static uint32_t get_pmtmr(PIIX4PMState *s)
  54 +{
  55 + uint32_t d;
  56 + d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  57 + return d & 0xffffff;
  58 +}
  59 +
  60 +static int get_pmsts(PIIX4PMState *s)
  61 +{
  62 + int64_t d;
  63 + int pmsts;
  64 + pmsts = s->pmsts;
  65 + d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  66 + if (d >= s->tmr_overflow_time)
  67 + s->pmsts |= TMROF_EN;
  68 + return pmsts;
  69 +}
  70 +
  71 +static void pm_update_sci(PIIX4PMState *s)
  72 +{
  73 + int sci_level, pmsts;
  74 + int64_t expire_time;
  75 +
  76 + pmsts = get_pmsts(s);
  77 + sci_level = (((pmsts & s->pmen) &
  78 + (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
  79 + pci_set_irq(&s->dev, 0, sci_level);
  80 + /* schedule a timer interruption if needed */
  81 + if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
  82 + expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
  83 + qemu_mod_timer(s->tmr_timer, expire_time);
  84 + } else {
  85 + qemu_del_timer(s->tmr_timer);
  86 + }
  87 +}
  88 +
  89 +static void pm_tmr_timer(void *opaque)
  90 +{
  91 + PIIX4PMState *s = opaque;
  92 + pm_update_sci(s);
  93 +}
  94 +
  95 +static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
  96 +{
  97 + PIIX4PMState *s = opaque;
  98 + addr &= 0x3f;
  99 + switch(addr) {
  100 + case 0x00:
  101 + {
  102 + int64_t d;
  103 + int pmsts;
  104 + pmsts = get_pmsts(s);
  105 + if (pmsts & val & TMROF_EN) {
  106 + /* if TMRSTS is reset, then compute the new overflow time */
  107 + d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
  108 + s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
  109 + }
  110 + s->pmsts &= ~val;
  111 + pm_update_sci(s);
  112 + }
  113 + break;
  114 + case 0x02:
  115 + s->pmen = val;
  116 + pm_update_sci(s);
  117 + break;
  118 + case 0x04:
  119 + {
  120 + int sus_typ;
  121 + s->pmcntrl = val & ~(SUS_EN);
  122 + if (val & SUS_EN) {
  123 + /* change suspend type */
  124 + sus_typ = (val >> 10) & 3;
  125 + switch(sus_typ) {
  126 + case 0: /* soft power off */
  127 + qemu_system_shutdown_request();
  128 + break;
  129 + default:
  130 + break;
  131 + }
  132 + }
  133 + }
  134 + break;
  135 + default:
  136 + break;
  137 + }
  138 +#ifdef DEBUG
  139 + printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
  140 +#endif
  141 +}
  142 +
  143 +static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
  144 +{
  145 + PIIX4PMState *s = opaque;
  146 + uint32_t val;
  147 +
  148 + addr &= 0x3f;
  149 + switch(addr) {
  150 + case 0x00:
  151 + val = get_pmsts(s);
  152 + break;
  153 + case 0x02:
  154 + val = s->pmen;
  155 + break;
  156 + case 0x04:
  157 + val = s->pmcntrl;
  158 + break;
  159 + default:
  160 + val = 0;
  161 + break;
  162 + }
  163 +#ifdef DEBUG
  164 + printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
  165 +#endif
  166 + return val;
  167 +}
  168 +
  169 +static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
  170 +{
  171 + // PIIX4PMState *s = opaque;
  172 + addr &= 0x3f;
  173 +#ifdef DEBUG
  174 + printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
  175 +#endif
  176 +}
  177 +
  178 +static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
  179 +{
  180 + PIIX4PMState *s = opaque;
  181 + uint32_t val;
  182 +
  183 + addr &= 0x3f;
  184 + switch(addr) {
  185 + case 0x08:
  186 + val = get_pmtmr(s);
  187 + break;
  188 + default:
  189 + val = 0;
  190 + break;
  191 + }
  192 +#ifdef DEBUG
  193 + printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
  194 +#endif
  195 + return val;
  196 +}
  197 +
  198 +static void smi_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
  199 +{
  200 + PIIX4PMState *s = opaque;
  201 +#ifdef DEBUG
  202 + printf("SMI cmd val=0x%02x\n", val);
  203 +#endif
  204 + switch(val) {
  205 + case 0xf0: /* ACPI disable */
  206 + s->pmcntrl &= ~SCI_EN;
  207 + break;
  208 + case 0xf1: /* ACPI enable */
  209 + s->pmcntrl |= SCI_EN;
  210 + break;
  211 + }
  212 +}
  213 +
  214 +static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
  215 +{
  216 +#if defined(DEBUG)
  217 + printf("ACPI: DBG: 0x%08x\n", val);
  218 +#endif
  219 +}
  220 +
  221 +/* XXX: we still add it to the PIIX3 and we count on the fact that
  222 + OSes are smart enough to accept this strange configuration */
  223 +void piix4_pm_init(PCIBus *bus)
  224 +{
  225 + PIIX4PMState *s;
  226 + uint8_t *pci_conf;
  227 + uint32_t pm_io_base;
  228 +
  229 + s = (PIIX4PMState *)pci_register_device(bus,
  230 + "PM", sizeof(PIIX4PMState),
  231 + ((PCIDevice *)piix3_state)->devfn + 3,
  232 + NULL, NULL);
  233 + pci_conf = s->dev.config;
  234 + pci_conf[0x00] = 0x86;
  235 + pci_conf[0x01] = 0x80;
  236 + pci_conf[0x02] = 0x13;
  237 + pci_conf[0x03] = 0x70;
  238 + pci_conf[0x08] = 0x00; // revision number
  239 + pci_conf[0x09] = 0x00;
  240 + pci_conf[0x0a] = 0x80; // other bridge device
  241 + pci_conf[0x0b] = 0x06; // bridge device
  242 + pci_conf[0x0e] = 0x00; // header_type
  243 + pci_conf[0x3d] = 0x01; // interrupt pin 1
  244 + pci_conf[0x60] = 0x10; // release number
  245 +
  246 + pm_io_base = PM_IO_BASE;
  247 + pci_conf[0x40] = pm_io_base | 1;
  248 + pci_conf[0x41] = pm_io_base >> 8;
  249 + register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
  250 + register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
  251 + register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
  252 + register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
  253 +
  254 + register_ioport_write(SMI_CMD_IO_ADDR, 1, 1, smi_cmd_writeb, s);
  255 + register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
  256 +
  257 + s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
  258 + piix4_pm_state = s;
  259 +}
  260 +
  261 +/* ACPI tables */
  262 +/* XXX: move them in the Bochs BIOS ? */
  263 +
  264 +/*************************************************/
  265 +
  266 +/* Table structure from Linux kernel (the ACPI tables are under the
  267 + BSD license) */
  268 +
  269 +#define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
  270 + uint8_t signature [4]; /* ACPI signature (4 ASCII characters) */\
  271 + uint32_t length; /* Length of table, in bytes, including header */\
  272 + uint8_t revision; /* ACPI Specification minor version # */\
  273 + uint8_t checksum; /* To make sum of entire table == 0 */\
  274 + uint8_t oem_id [6]; /* OEM identification */\
  275 + uint8_t oem_table_id [8]; /* OEM table identification */\
  276 + uint32_t oem_revision; /* OEM revision number */\
  277 + uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */\
  278 + uint32_t asl_compiler_revision; /* ASL compiler revision number */
  279 +
  280 +
  281 +struct acpi_table_header /* ACPI common table header */
  282 +{
  283 + ACPI_TABLE_HEADER_DEF
  284 +};
  285 +
  286 +struct rsdp_descriptor /* Root System Descriptor Pointer */
  287 +{
  288 + uint8_t signature [8]; /* ACPI signature, contains "RSD PTR " */
  289 + uint8_t checksum; /* To make sum of struct == 0 */
  290 + uint8_t oem_id [6]; /* OEM identification */
  291 + uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */
  292 + uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */
  293 + uint32_t length; /* XSDT Length in bytes including hdr */
  294 + uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */
  295 + uint8_t extended_checksum; /* Checksum of entire table */
  296 + uint8_t reserved [3]; /* Reserved field must be 0 */
  297 +};
  298 +
  299 +/*
  300 + * ACPI 1.0 Root System Description Table (RSDT)
  301 + */
  302 +struct rsdt_descriptor_rev1
  303 +{
  304 + ACPI_TABLE_HEADER_DEF /* ACPI common table header */
  305 + uint32_t table_offset_entry [2]; /* Array of pointers to other */
  306 + /* ACPI tables */
  307 +};
  308 +
  309 +/*
  310 + * ACPI 1.0 Firmware ACPI Control Structure (FACS)
  311 + */
  312 +struct facs_descriptor_rev1
  313 +{
  314 + uint8_t signature[4]; /* ACPI Signature */
  315 + uint32_t length; /* Length of structure, in bytes */
  316 + uint32_t hardware_signature; /* Hardware configuration signature */
  317 + uint32_t firmware_waking_vector; /* ACPI OS waking vector */
  318 + uint32_t global_lock; /* Global Lock */
  319 + uint32_t S4bios_f : 1; /* Indicates if S4BIOS support is present */
  320 + uint32_t reserved1 : 31; /* Must be 0 */
  321 + uint8_t resverved3 [40]; /* Reserved - must be zero */
  322 +};
  323 +
  324 +
  325 +/*
  326 + * ACPI 1.0 Fixed ACPI Description Table (FADT)
  327 + */
  328 +struct fadt_descriptor_rev1
  329 +{
  330 + ACPI_TABLE_HEADER_DEF /* ACPI common table header */
  331 + uint32_t firmware_ctrl; /* Physical address of FACS */
  332 + uint32_t dsdt; /* Physical address of DSDT */
  333 + uint8_t model; /* System Interrupt Model */
  334 + uint8_t reserved1; /* Reserved */
  335 + uint16_t sci_int; /* System vector of SCI interrupt */
  336 + uint32_t smi_cmd; /* Port address of SMI command port */
  337 + uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
  338 + uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
  339 + uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
  340 + uint8_t reserved2; /* Reserved - must be zero */
  341 + uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
  342 + uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
  343 + uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
  344 + uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
  345 + uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
  346 + uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
  347 + uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
  348 + uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
  349 + uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
  350 + uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
  351 + uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
  352 + uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
  353 + uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
  354 + uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
  355 + uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
  356 + uint8_t reserved3; /* Reserved */
  357 + uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
  358 + uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
  359 + uint16_t flush_size; /* Size of area read to flush caches */
  360 + uint16_t flush_stride; /* Stride used in flushing caches */
  361 + uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
  362 + uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
  363 + uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
  364 + uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
  365 + uint8_t century; /* Index to century in RTC CMOS RAM */
  366 + uint8_t reserved4; /* Reserved */
  367 + uint8_t reserved4a; /* Reserved */
  368 + uint8_t reserved4b; /* Reserved */
  369 +#if 0
  370 + uint32_t wb_invd : 1; /* The wbinvd instruction works properly */
  371 + uint32_t wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
  372 + uint32_t proc_c1 : 1; /* All processors support C1 state */
  373 + uint32_t plvl2_up : 1; /* C2 state works on MP system */
  374 + uint32_t pwr_button : 1; /* Power button is handled as a generic feature */
  375 + uint32_t sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
  376 + uint32_t fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
  377 + uint32_t rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
  378 + uint32_t tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
  379 + uint32_t reserved5 : 23; /* Reserved - must be zero */
  380 +#else
  381 + uint32_t flags;
  382 +#endif
  383 +};
  384 +
  385 +/*
  386 + * MADT values and structures
  387 + */
  388 +
  389 +/* Values for MADT PCATCompat */
  390 +
  391 +#define DUAL_PIC 0
  392 +#define MULTIPLE_APIC 1
  393 +
  394 +
  395 +/* Master MADT */
  396 +
  397 +struct multiple_apic_table
  398 +{
  399 + ACPI_TABLE_HEADER_DEF /* ACPI common table header */
  400 + uint32_t local_apic_address; /* Physical address of local APIC */
  401 +#if 0
  402 + uint32_t PCATcompat : 1; /* A one indicates system also has dual 8259s */
  403 + uint32_t reserved1 : 31;
  404 +#else
  405 + uint32_t flags;
  406 +#endif
  407 +};
  408 +
  409 +
  410 +/* Values for Type in APIC_HEADER_DEF */
  411 +
  412 +#define APIC_PROCESSOR 0
  413 +#define APIC_IO 1
  414 +#define APIC_XRUPT_OVERRIDE 2
  415 +#define APIC_NMI 3
  416 +#define APIC_LOCAL_NMI 4
  417 +#define APIC_ADDRESS_OVERRIDE 5
  418 +#define APIC_IO_SAPIC 6
  419 +#define APIC_LOCAL_SAPIC 7
  420 +#define APIC_XRUPT_SOURCE 8
  421 +#define APIC_RESERVED 9 /* 9 and greater are reserved */
  422 +
  423 +/*
  424 + * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
  425 + */
  426 +#define APIC_HEADER_DEF /* Common APIC sub-structure header */\
  427 + uint8_t type; \
  428 + uint8_t length;
  429 +
  430 +/* Sub-structures for MADT */
  431 +
  432 +struct madt_processor_apic
  433 +{
  434 + APIC_HEADER_DEF
  435 + uint8_t processor_id; /* ACPI processor id */
  436 + uint8_t local_apic_id; /* Processor's local APIC id */
  437 +#if 0
  438 + uint32_t processor_enabled: 1; /* Processor is usable if set */
  439 + uint32_t reserved2 : 31; /* Reserved, must be zero */
  440 +#else
  441 + uint32_t flags;
  442 +#endif
  443 +};
  444 +
  445 +struct madt_io_apic
  446 +{
  447 + APIC_HEADER_DEF
  448 + uint8_t io_apic_id; /* I/O APIC ID */
  449 + uint8_t reserved; /* Reserved - must be zero */
  450 + uint32_t address; /* APIC physical address */
  451 + uint32_t interrupt; /* Global system interrupt where INTI
  452 + * lines start */
  453 +};
  454 +
  455 +#include "acpi-dsdt.hex"
  456 +
  457 +static int acpi_checksum(const uint8_t *data, int len)
  458 +{
  459 + int sum, i;
  460 + sum = 0;
  461 + for(i = 0; i < len; i++)
  462 + sum += data[i];
  463 + return (-sum) & 0xff;
  464 +}
  465 +
  466 +static void acpi_build_table_header(struct acpi_table_header *h,
  467 + char *sig, int len)
  468 +{
  469 + memcpy(h->signature, sig, 4);
  470 + h->length = cpu_to_le32(len);
  471 + h->revision = 0;
  472 + memcpy(h->oem_id, "QEMU ", 6);
  473 + memcpy(h->oem_table_id, "QEMU", 4);
  474 + memcpy(h->oem_table_id + 4, sig, 4);
  475 + h->oem_revision = cpu_to_le32(1);
  476 + memcpy(h->asl_compiler_id, "QEMU", 4);
  477 + h->asl_compiler_revision = cpu_to_le32(1);
  478 + h->checksum = acpi_checksum((void *)h, len);
  479 +}
  480 +
  481 +#define ACPI_TABLES_BASE 0x000e8000
  482 +
  483 +/* base_addr must be a multiple of 4KB */
  484 +void acpi_bios_init(void)
  485 +{
  486 + struct rsdp_descriptor *rsdp;
  487 + struct rsdt_descriptor_rev1 *rsdt;
  488 + struct fadt_descriptor_rev1 *fadt;
  489 + struct facs_descriptor_rev1 *facs;
  490 + struct multiple_apic_table *madt;
  491 + uint8_t *dsdt;
  492 + uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr;
  493 + uint32_t pm_io_base, acpi_tables_size, madt_addr, madt_size;
  494 + int i;
  495 +
  496 + /* compute PCI I/O addresses */
  497 + pm_io_base = (piix4_pm_state->dev.config[0x40] |
  498 + (piix4_pm_state->dev.config[0x41] << 8)) & ~0x3f;
  499 +
  500 + base_addr = ACPI_TABLES_BASE;
  501 +
  502 + /* reserve memory space for tables */
  503 + addr = base_addr;
  504 + rsdp = (void *)(phys_ram_base + addr);
  505 + addr += sizeof(*rsdp);
  506 +
  507 + rsdt_addr = addr;
  508 + rsdt = (void *)(phys_ram_base + addr);
  509 + addr += sizeof(*rsdt);
  510 +
  511 + fadt_addr = addr;
  512 + fadt = (void *)(phys_ram_base + addr);
  513 + addr += sizeof(*fadt);
  514 +
  515 + /* XXX: FACS should be in RAM */
  516 + addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
  517 + facs_addr = addr;
  518 + facs = (void *)(phys_ram_base + addr);
  519 + addr += sizeof(*facs);
  520 +
  521 + dsdt_addr = addr;
  522 + dsdt = (void *)(phys_ram_base + addr);
  523 + addr += sizeof(AmlCode);
  524 +
  525 + madt_addr = addr;
  526 + madt_size = sizeof(*madt) +
  527 + sizeof(struct madt_processor_apic) * smp_cpus +
  528 + sizeof(struct madt_io_apic);
  529 + madt = (void *)(phys_ram_base + addr);
  530 + addr += madt_size;
  531 +
  532 + acpi_tables_size = addr - base_addr;
  533 +
  534 + cpu_register_physical_memory(base_addr, acpi_tables_size,
  535 + base_addr | IO_MEM_ROM);
  536 +
  537 + /* RSDP */
  538 + memset(rsdp, 0, sizeof(*rsdp));
  539 + memcpy(rsdp->signature, "RSD PTR ", 8);
  540 + memcpy(rsdp->oem_id, "QEMU ", 6);
  541 + rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
  542 + rsdp->checksum = acpi_checksum((void *)rsdp, 20);
  543 +
  544 + /* RSDT */
  545 + rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
  546 + rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
  547 + acpi_build_table_header((struct acpi_table_header *)rsdt,
  548 + "RSDT", sizeof(*rsdt));
  549 +
  550 + /* FADT */
  551 + memset(fadt, 0, sizeof(*fadt));
  552 + fadt->firmware_ctrl = cpu_to_le32(facs_addr);
  553 + fadt->dsdt = cpu_to_le32(dsdt_addr);
  554 + fadt->model = 1;
  555 + fadt->reserved1 = 0;
  556 + fadt->sci_int = cpu_to_le16(piix4_pm_state->dev.config[0x3c]);
  557 + fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
  558 + fadt->acpi_enable = 0xf1;
  559 + fadt->acpi_disable = 0xf0;
  560 + fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
  561 + fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
  562 + fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
  563 + fadt->pm1_evt_len = 4;
  564 + fadt->pm1_cnt_len = 2;
  565 + fadt->pm_tmr_len = 4;
  566 + fadt->plvl2_lat = cpu_to_le16(50);
  567 + fadt->plvl3_lat = cpu_to_le16(50);
  568 + fadt->plvl3_lat = cpu_to_le16(50);
  569 + /* WBINVD + PROC_C1 + PWR_BUTTON + SLP_BUTTON + FIX_RTC */
  570 + fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 4) | (1 << 5) | (1 << 6));
  571 + acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
  572 + sizeof(*fadt));
  573 +
  574 + /* FACS */
  575 + memset(facs, 0, sizeof(*facs));
  576 + memcpy(facs->signature, "FACS", 4);
  577 + facs->length = cpu_to_le32(sizeof(*facs));
  578 +
  579 + /* DSDT */
  580 + memcpy(dsdt, AmlCode, sizeof(AmlCode));
  581 +
  582 + /* MADT */
  583 + {
  584 + struct madt_processor_apic *apic;
  585 + struct madt_io_apic *io_apic;
  586 +
  587 + memset(madt, 0, madt_size);
  588 + madt->local_apic_address = cpu_to_le32(0xfee00000);
  589 + madt->flags = cpu_to_le32(1);
  590 + apic = (void *)(madt + 1);
  591 + for(i=0;i<smp_cpus;i++) {
  592 + apic->type = APIC_PROCESSOR;
  593 + apic->length = sizeof(*apic);
  594 + apic->processor_id = i;
  595 + apic->local_apic_id = i;
  596 + apic->flags = cpu_to_le32(1);
  597 + apic++;
  598 + }
  599 + io_apic = (void *)apic;
  600 + io_apic->type = APIC_IO;
  601 + io_apic->length = sizeof(*io_apic);
  602 + io_apic->io_apic_id = smp_cpus;
  603 + io_apic->address = cpu_to_le32(0xfec00000);
  604 + io_apic->interrupt = cpu_to_le32(0);
  605 +
  606 + acpi_build_table_header((struct acpi_table_header *)madt,
  607 + "APIC", madt_size);
  608 + }
  609 +}
... ...
... ... @@ -836,10 +836,15 @@ static void pc_init1(int ram_size, int vga_ram_size, int boot_device,
836 836 usb_attach(usb_root_ports[0], vm_usb_hub);
837 837 }
838 838  
  839 + if (pci_enabled && acpi_enabled) {
  840 + piix4_pm_init(pci_bus);
  841 + }
839 842 /* must be done after all PCI devices are instanciated */
840 843 /* XXX: should be done in the Bochs BIOS */
841 844 if (pci_enabled) {
842 845 pci_bios_init();
  846 + if (acpi_enabled)
  847 + acpi_bios_init();
843 848 }
844 849 }
845 850  
... ...
... ... @@ -157,6 +157,7 @@ int vnc_display = -1;
157 157 #else
158 158 #define MAX_CPUS 1
159 159 #endif
  160 +int acpi_enabled = 1;
160 161  
161 162 /***********************************************************/
162 163 /* x86 ISA bus support */
... ... @@ -4675,6 +4676,7 @@ void help(void)
4675 4676 " translation (t=none or lba) (usually qemu can guess them)\n"
4676 4677 "-L path set the directory for the BIOS and VGA BIOS\n"
4677 4678 #ifdef USE_KQEMU
  4679 + "-kernel-kqemu enable KQEMU full virtualization (default is user mode only)\n"
4678 4680 "-no-kqemu disable KQEMU kernel module usage\n"
4679 4681 #endif
4680 4682 #ifdef USE_CODE_COPY
... ... @@ -4683,6 +4685,7 @@ void help(void)
4683 4685 #ifdef TARGET_I386
4684 4686 "-std-vga simulate a standard VGA card with VESA Bochs Extensions\n"
4685 4687 " (default is CL-GD5446 PCI VGA)\n"
  4688 + "-no-acpi disable ACPI\n"
4686 4689 #endif
4687 4690 "-loadvm file start right away with a saved state (loadvm in monitor)\n"
4688 4691 "-vnc display start a VNC server on display\n"
... ... @@ -4770,6 +4773,7 @@ enum {
4770 4773 QEMU_OPTION_usbdevice,
4771 4774 QEMU_OPTION_smp,
4772 4775 QEMU_OPTION_vnc,
  4776 + QEMU_OPTION_no_acpi,
4773 4777 };
4774 4778  
4775 4779 typedef struct QEMUOption {
... ... @@ -4842,6 +4846,7 @@ const QEMUOption qemu_options[] = {
4842 4846 /* temporary options */
4843 4847 { "usb", 0, QEMU_OPTION_usb },
4844 4848 { "cirrusvga", 0, QEMU_OPTION_cirrusvga },
  4849 + { "no-acpi", 0, QEMU_OPTION_no_acpi },
4845 4850 { NULL },
4846 4851 };
4847 4852  
... ... @@ -5443,6 +5448,9 @@ int main(int argc, char **argv)
5443 5448 exit(1);
5444 5449 }
5445 5450 break;
  5451 + case QEMU_OPTION_no_acpi:
  5452 + acpi_enabled = 0;
  5453 + break;
5446 5454 }
5447 5455 }
5448 5456 }
... ...
... ... @@ -840,6 +840,11 @@ int pit_get_out(PITState *pit, int channel, int64_t current_time);
840 840 void pcspk_init(PITState *);
841 841 int pcspk_audio_init(AudioState *);
842 842  
  843 +/* acpi.c */
  844 +extern int acpi_enabled;
  845 +void piix4_pm_init(PCIBus *bus);
  846 +void acpi_bios_init(void);
  847 +
843 848 /* pc.c */
844 849 extern QEMUMachine pc_machine;
845 850 extern QEMUMachine isapc_machine;
... ...