gwj / at91sam9263 · Commits

Commit 3fffc2234fc6551a78533fe544ba96106e58379a

Authored by ths
1 parent 4a109bfb

PIIX4 SMBus host, EEPROM device emulation, by Ed Swierk. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2379 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 6 changed files with 330 additions and 1 deletions
Makefile.target
  View file @3fffc22
... ... @@ -370,7 +370,7 @@ ifeq ($(TARGET_BASE_ARCH), i386)
370 370 VL_OBJS+= ide.o pckbd.o ps2.o vga.o $(SOUND_HW) dma.o $(AUDIODRV)
371 371 VL_OBJS+= fdc.o mc146818rtc.o serial.o i8259.o i8254.o pcspk.o pc.o
372 372 VL_OBJS+= cirrus_vga.o mixeng.o apic.o parallel.o acpi.o piix_pci.o
373   -VL_OBJS+= usb-uhci.o
  373 +VL_OBJS+= usb-uhci.o smbus_eeprom.o
374 374 CPPFLAGS += -DHAS_AUDIO
375 375 endif
376 376 ifeq ($(TARGET_BASE_ARCH), ppc)
... ...
hw/acpi.c
  View file @3fffc22
... ... @@ -24,6 +24,7 @@
24 24 #define PM_FREQ 3579545
25 25  
26 26 #define ACPI_DBG_IO_ADDR 0xb044
  27 +#define SMB_IO_BASE 0xb100
27 28  
28 29 typedef struct PIIX4PMState {
29 30 PCIDevice dev;
... ... @@ -34,6 +35,15 @@ typedef struct PIIX4PMState {
34 35 uint8_t apms;
35 36 QEMUTimer *tmr_timer;
36 37 int64_t tmr_overflow_time;
  38 + SMBusDevice *smb_dev[128];
  39 + uint8_t smb_stat;
  40 + uint8_t smb_ctl;
  41 + uint8_t smb_cmd;
  42 + uint8_t smb_addr;
  43 + uint8_t smb_data0;
  44 + uint8_t smb_data1;
  45 + uint8_t smb_data[32];
  46 + uint8_t smb_index;
37 47 } PIIX4PMState;
38 48  
39 49 #define RTC_EN (1 << 10)
... ... @@ -45,6 +55,17 @@ typedef struct PIIX4PMState {
45 55  
46 56 #define SUS_EN (1 << 13)
47 57  
  58 +#define SMBHSTSTS 0x00
  59 +#define SMBHSTCNT 0x02
  60 +#define SMBHSTCMD 0x03
  61 +#define SMBHSTADD 0x04
  62 +#define SMBHSTDAT0 0x05
  63 +#define SMBHSTDAT1 0x06
  64 +#define SMBBLKDAT 0x07
  65 +
  66 +/* Note: only used for piix4_smbus_register_device */
  67 +static PIIX4PMState *piix4_pm_state;
  68 +
48 69 static uint32_t get_pmtmr(PIIX4PMState *s)
49 70 {
50 71 uint32_t d;
... ... @@ -231,6 +252,156 @@ static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
231 252 #endif
232 253 }
233 254  
  255 +static void smb_transaction(PIIX4PMState *s)
  256 +{
  257 + uint8_t prot = (s->smb_ctl >> 2) & 0x07;
  258 + uint8_t read = s->smb_addr & 0x01;
  259 + uint8_t cmd = s->smb_cmd;
  260 + uint8_t addr = s->smb_addr >> 1;
  261 + SMBusDevice *dev = s->smb_dev[addr];
  262 +
  263 +#ifdef DEBUG
  264 + printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
  265 +#endif
  266 + if (!dev) goto error;
  267 +
  268 + switch(prot) {
  269 + case 0x0:
  270 + if (!dev->quick_cmd) goto error;
  271 + (*dev->quick_cmd)(dev, read);
  272 + break;
  273 + case 0x1:
  274 + if (read) {
  275 + if (!dev->receive_byte) goto error;
  276 + s->smb_data0 = (*dev->receive_byte)(dev);
  277 + }
  278 + else {
  279 + if (!dev->send_byte) goto error;
  280 + (*dev->send_byte)(dev, cmd);
  281 + }
  282 + break;
  283 + case 0x2:
  284 + if (read) {
  285 + if (!dev->read_byte) goto error;
  286 + s->smb_data0 = (*dev->read_byte)(dev, cmd);
  287 + }
  288 + else {
  289 + if (!dev->write_byte) goto error;
  290 + (*dev->write_byte)(dev, cmd, s->smb_data0);
  291 + }
  292 + break;
  293 + case 0x3:
  294 + if (read) {
  295 + uint16_t val;
  296 + if (!dev->read_word) goto error;
  297 + val = (*dev->read_word)(dev, cmd);
  298 + s->smb_data0 = val;
  299 + s->smb_data1 = val >> 8;
  300 + }
  301 + else {
  302 + if (!dev->write_word) goto error;
  303 + (*dev->write_word)(dev, cmd, (s->smb_data1 << 8) | s->smb_data0);
  304 + }
  305 + break;
  306 + case 0x5:
  307 + if (read) {
  308 + if (!dev->read_block) goto error;
  309 + s->smb_data0 = (*dev->read_block)(dev, cmd, s->smb_data);
  310 + }
  311 + else {
  312 + if (!dev->write_block) goto error;
  313 + (*dev->write_block)(dev, cmd, s->smb_data0, s->smb_data);
  314 + }
  315 + break;
  316 + default:
  317 + goto error;
  318 + }
  319 + return;
  320 +
  321 + error:
  322 + s->smb_stat |= 0x04;
  323 +}
  324 +
  325 +static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
  326 +{
  327 + PIIX4PMState *s = opaque;
  328 + addr &= 0x3f;
  329 +#ifdef DEBUG
  330 + printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
  331 +#endif
  332 + switch(addr) {
  333 + case SMBHSTSTS:
  334 + s->smb_stat = 0;
  335 + s->smb_index = 0;
  336 + break;
  337 + case SMBHSTCNT:
  338 + s->smb_ctl = val;
  339 + if (val & 0x40)
  340 + smb_transaction(s);
  341 + break;
  342 + case SMBHSTCMD:
  343 + s->smb_cmd = val;
  344 + break;
  345 + case SMBHSTADD:
  346 + s->smb_addr = val;
  347 + break;
  348 + case SMBHSTDAT0:
  349 + s->smb_data0 = val;
  350 + break;
  351 + case SMBHSTDAT1:
  352 + s->smb_data1 = val;
  353 + break;
  354 + case SMBBLKDAT:
  355 + s->smb_data[s->smb_index++] = val;
  356 + if (s->smb_index > 31)
  357 + s->smb_index = 0;
  358 + break;
  359 + default:
  360 + break;
  361 + }
  362 +}
  363 +
  364 +static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
  365 +{
  366 + PIIX4PMState *s = opaque;
  367 + uint32_t val;
  368 +
  369 + addr &= 0x3f;
  370 + switch(addr) {
  371 + case SMBHSTSTS:
  372 + val = s->smb_stat;
  373 + break;
  374 + case SMBHSTCNT:
  375 + s->smb_index = 0;
  376 + val = s->smb_ctl & 0x1f;
  377 + break;
  378 + case SMBHSTCMD:
  379 + val = s->smb_cmd;
  380 + break;
  381 + case SMBHSTADD:
  382 + val = s->smb_addr;
  383 + break;
  384 + case SMBHSTDAT0:
  385 + val = s->smb_data0;
  386 + break;
  387 + case SMBHSTDAT1:
  388 + val = s->smb_data1;
  389 + break;
  390 + case SMBBLKDAT:
  391 + val = s->smb_data[s->smb_index++];
  392 + if (s->smb_index > 31)
  393 + s->smb_index = 0;
  394 + break;
  395 + default:
  396 + val = 0;
  397 + break;
  398 + }
  399 +#ifdef DEBUG
  400 + printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
  401 +#endif
  402 + return val;
  403 +}
  404 +
234 405 static void pm_io_space_update(PIIX4PMState *s)
235 406 {
236 407 uint32_t pm_io_base;
... ... @@ -302,6 +473,7 @@ void piix4_pm_init(PCIBus *bus, int devfn)
302 473 {
303 474 PIIX4PMState *s;
304 475 uint8_t *pci_conf;
  476 + uint32_t pm_io_base, smb_io_base;
305 477  
306 478 s = (PIIX4PMState *)pci_register_device(bus,
307 479 "PM", sizeof(PIIX4PMState),
... ... @@ -332,7 +504,20 @@ void piix4_pm_init(PCIBus *bus, int devfn)
332 504 pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
333 505 (serial_hds[1] != NULL ? 0x90 : 0);
334 506  
  507 + smb_io_base = SMB_IO_BASE;
  508 + pci_conf[0x90] = smb_io_base | 1;
  509 + pci_conf[0x91] = smb_io_base >> 8;
  510 + pci_conf[0xd2] = 0x09;
  511 + register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
  512 + register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
  513 +
335 514 s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
336 515  
337 516 register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
  517 + piix4_pm_state = s;
  518 +}
  519 +
  520 +void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr)
  521 +{
  522 + piix4_pm_state->smb_dev[addr] = dev;
338 523 }
... ...
... ... @@ -699,7 +699,13 @@ static void pc_init1(int ram_size, int vga_ram_size, int boot_device,
699 699 }
700 700  
701 701 if (pci_enabled && acpi_enabled) {
  702 + uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
702 703 piix4_pm_init(pci_bus, piix3_devfn + 3);
  704 + for (i = 0; i < 8; i++) {
  705 + SMBusDevice *eeprom = smbus_eeprom_device_init(0x50 + i,
  706 + eeprom_buf + (i * 256));
  707 + piix4_smbus_register_device(eeprom, 0x50 + i);
  708 + }
703 709 }
704 710  
705 711 if (i440fx_state) {
... ...
hw/smbus.h 0 → 100644
  View file @3fffc22
  1 +/*
  2 + * QEMU SMBus API
  3 + *
  4 + * Copyright (c) 2007 Arastra, Inc.
  5 + *
  6 + * Permission is hereby granted, free of charge, to any person obtaining a copy
  7 + * of this software and associated documentation files (the "Software"), to deal
  8 + * in the Software without restriction, including without limitation the rights
  9 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 + * copies of the Software, and to permit persons to whom the Software is
  11 + * furnished to do so, subject to the following conditions:
  12 + *
  13 + * The above copyright notice and this permission notice shall be included in
  14 + * all copies or substantial portions of the Software.
  15 + *
  16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 + * THE SOFTWARE.
  23 + */
  24 +
  25 +typedef struct SMBusDevice SMBusDevice;
  26 +
  27 +struct SMBusDevice {
  28 + uint8_t addr;
  29 + void (*quick_cmd)(SMBusDevice *dev, uint8_t read);
  30 + void (*send_byte)(SMBusDevice *dev, uint8_t val);
  31 + uint8_t (*receive_byte)(SMBusDevice *dev);
  32 + void (*write_byte)(SMBusDevice *dev, uint8_t cmd, uint8_t val);
  33 + uint8_t (*read_byte)(SMBusDevice *dev, uint8_t cmd);
  34 + void (*write_word)(SMBusDevice *dev, uint8_t cmd, uint16_t val);
  35 + uint16_t (*read_word)(SMBusDevice *dev, uint8_t cmd);
  36 + void (*write_block)(SMBusDevice *dev, uint8_t cmd, uint8_t len, uint8_t *buf);
  37 + uint8_t (*read_block)(SMBusDevice *dev, uint8_t cmd, uint8_t *buf);
  38 +};
... ...
hw/smbus_eeprom.c 0 → 100644
  View file @3fffc22
  1 +/*
  2 + * QEMU SMBus EEPROM device
  3 + *
  4 + * Copyright (c) 2007 Arastra, Inc.
  5 + *
  6 + * Permission is hereby granted, free of charge, to any person obtaining a copy
  7 + * of this software and associated documentation files (the "Software"), to deal
  8 + * in the Software without restriction, including without limitation the rights
  9 + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 + * copies of the Software, and to permit persons to whom the Software is
  11 + * furnished to do so, subject to the following conditions:
  12 + *
  13 + * The above copyright notice and this permission notice shall be included in
  14 + * all copies or substantial portions of the Software.
  15 + *
  16 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 + * THE SOFTWARE.
  23 + */
  24 +
  25 +#include "vl.h"
  26 +
  27 +//#define DEBUG
  28 +
  29 +typedef struct SMBusEEPROMDevice {
  30 + SMBusDevice dev;
  31 + uint8_t *data;
  32 + uint8_t offset;
  33 +} SMBusEEPROMDevice;
  34 +
  35 +static void eeprom_quick_cmd(SMBusDevice *dev, uint8_t read)
  36 +{
  37 +#ifdef DEBUG
  38 + printf("eeprom_quick_cmd: addr=0x%02x read=%d\n", dev->addr, read);
  39 +#endif
  40 +}
  41 +
  42 +static void eeprom_send_byte(SMBusDevice *dev, uint8_t val)
  43 +{
  44 + SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
  45 +#ifdef DEBUG
  46 + printf("eeprom_send_byte: addr=0x%02x val=0x%02x\n", dev->addr, val);
  47 +#endif
  48 + eeprom->offset = val;
  49 +}
  50 +
  51 +static uint8_t eeprom_receive_byte(SMBusDevice *dev)
  52 +{
  53 + SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
  54 + uint8_t val = eeprom->data[eeprom->offset++];
  55 +#ifdef DEBUG
  56 + printf("eeprom_receive_byte: addr=0x%02x val=0x%02x\n", dev->addr, val);
  57 +#endif
  58 + return val;
  59 +}
  60 +
  61 +static void eeprom_write_byte(SMBusDevice *dev, uint8_t cmd, uint8_t val)
  62 +{
  63 + SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
  64 +#ifdef DEBUG
  65 + printf("eeprom_write_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", dev->addr,
  66 + cmd, val);
  67 +#endif
  68 + eeprom->data[cmd] = val;
  69 +}
  70 +
  71 +static uint8_t eeprom_read_byte(SMBusDevice *dev, uint8_t cmd)
  72 +{
  73 + SMBusEEPROMDevice *eeprom = (SMBusEEPROMDevice *) dev;
  74 + uint8_t val = eeprom->data[cmd];
  75 +#ifdef DEBUG
  76 + printf("eeprom_read_byte: addr=0x%02x cmd=0x%02x val=0x%02x\n", dev->addr,
  77 + cmd, val);
  78 +#endif
  79 + return val;
  80 +}
  81 +
  82 +SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf)
  83 +{
  84 + SMBusEEPROMDevice *eeprom = qemu_mallocz(sizeof(SMBusEEPROMDevice));
  85 + eeprom->dev.addr = addr;
  86 + eeprom->dev.quick_cmd = eeprom_quick_cmd;
  87 + eeprom->dev.send_byte = eeprom_send_byte;
  88 + eeprom->dev.receive_byte = eeprom_receive_byte;
  89 + eeprom->dev.write_byte = eeprom_write_byte;
  90 + eeprom->dev.read_byte = eeprom_read_byte;
  91 + eeprom->data = buf;
  92 + eeprom->offset = 0;
  93 + return (SMBusDevice *) eeprom;
  94 +}
... ...
... ... @@ -1048,11 +1048,17 @@ int pit_get_out(PITState *pit, int channel, int64_t current_time);
1048 1048 void pcspk_init(PITState *);
1049 1049 int pcspk_audio_init(AudioState *);
1050 1050  
  1051 +#include "hw/smbus.h"
  1052 +
1051 1053 /* acpi.c */
1052 1054 extern int acpi_enabled;
1053 1055 void piix4_pm_init(PCIBus *bus, int devfn);
  1056 +void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1054 1057 void acpi_bios_init(void);
1055 1058  
  1059 +/* smbus_eeprom.c */
  1060 +SMBusDevice *smbus_eeprom_device_init(uint8_t addr, uint8_t *buf);
  1061 +
1056 1062 /* pc.c */
1057 1063 extern QEMUMachine pc_machine;
1058 1064 extern QEMUMachine isapc_machine;
... ...