gwj / at91sam9263 · Commits

Commit 6407f37373093fd56cde9e20b0b5a878b67521ca

Authored by Isaku Yamahata
Committed by Blue Swirl
1 parent ccbb4d44

use PCI_HEADER_TYPE. 

use symbolic value instead of 0x0e and related value.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Inline Side-by-side
Showing 21 changed files with 37 additions and 32 deletions
hw/ac97.c
  View file @6407f37
... ... @@ -1348,7 +1348,7 @@ int ac97_init (PCIBus *bus, AudioState *audio)
1348 1348 c[0x08] = 0x01; /* rid revision ro */
1349 1349 c[0x09] = 0x00; /* pi programming interface ro */
1350 1350 pci_config_set_class(c, PCI_CLASS_MULTIMEDIA_AUDIO); /* ro */
1351   - c[0x0e] = 0x00; /* headtyp header type ro */
  1351 + c[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; /* headtyp header type ro */
1352 1352  
1353 1353 c[0x10] = 0x01; /* nabmar native audio mixer base
1354 1354 address rw */
... ...
hw/acpi.c
  View file @6407f37
... ... @@ -515,7 +515,7 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
515 515 pci_conf[0x08] = 0x03; // revision number
516 516 pci_conf[0x09] = 0x00;
517 517 pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
518   - pci_conf[0x0e] = 0x00; // header_type
  518 + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
519 519 pci_conf[0x3d] = 0x01; // interrupt pin 1
520 520  
521 521 pci_conf[0x40] = 0x01; /* PM io base read only bit */
... ...
hw/apb_pci.c
  View file @6407f37
... ... @@ -262,7 +262,7 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
262 262 d->config[0x09] = 0x00; // programming i/f
263 263 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
264 264 d->config[0x0D] = 0x10; // latency_timer
265   - d->config[0x0E] = 0x00; // header_type
  265 + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
266 266  
267 267 /* APB secondary busses */
268 268 *bus2 = pci_bridge_init(s->bus, 8, PCI_VENDOR_ID_SUN,
... ...
hw/cirrus_vga.c
  View file @6407f37
... ... @@ -187,7 +187,6 @@
187 187 // PCI 0x08, 0x00ff0000
188 188 #define PCI_CLASS_SUB_VGA 0x00
189 189 // PCI 0x0c, 0x00ff0000 (0x0c:cacheline,0x0d:latency,0x0e:headertype,0x0f:Built-in self test)
190   -#define PCI_CLASS_HEADERTYPE_00h 0x00
191 190 // 0x10-0x3f (headertype 00h)
192 191 // PCI 0x10,0x14,0x18,0x1c,0x20,0x24: base address mapping registers
193 192 // 0x10: MEMBASE, 0x14: IOBASE(hard-coded in XFree86 3.x)
... ... @@ -3319,7 +3318,7 @@ void pci_cirrus_vga_init(PCIBus *bus, int vga_ram_size)
3319 3318 pci_config_set_device_id(pci_conf, device_id);
3320 3319 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3321 3320 pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
3322   - pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
  3321 + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
3323 3322  
3324 3323 /* setup VGA */
3325 3324 s = &d->cirrus_vga;
... ...
hw/grackle_pci.c
  View file @6407f37
... ... @@ -149,7 +149,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
149 149 d->config[0x08] = 0x00; // revision
150 150 d->config[0x09] = 0x01;
151 151 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
152   - d->config[0x0e] = 0x00; // header_type
  152 + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
153 153  
154 154 #if 0
155 155 /* PCI2PCI bridge same values as PearPC - check this */
... ... @@ -157,7 +157,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
157 157 pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
158 158 d->config[0x08] = 0x02; // revision
159 159 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
160   - d->config[0x0e] = 0x01; // header_type
  160 + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
161 161  
162 162 d->config[0x18] = 0x0; // primary_bus
163 163 d->config[0x19] = 0x1; // secondary_bus
... ...
hw/ide.c
  View file @6407f37
... ... @@ -3301,7 +3301,7 @@ void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
3301 3301 pci_conf[0x09] = 0x8f;
3302 3302  
3303 3303 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
3304   - pci_conf[0x0e] = 0x00; // header_type
  3304 + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
3305 3305  
3306 3306 pci_conf[0x51] = 0x04; // enable IDE0
3307 3307 if (secondary_ide_enabled) {
... ... @@ -3371,7 +3371,7 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
3371 3371 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_1);
3372 3372 pci_conf[0x09] = 0x80; // legacy ATA mode
3373 3373 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
3374   - pci_conf[0x0e] = 0x00; // header_type
  3374 + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
3375 3375  
3376 3376 qemu_register_reset(piix3_reset, d);
3377 3377 piix3_reset(d);
... ... @@ -3411,7 +3411,7 @@ void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
3411 3411 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB);
3412 3412 pci_conf[0x09] = 0x80; // legacy ATA mode
3413 3413 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
3414   - pci_conf[0x0e] = 0x00; // header_type
  3414 + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
3415 3415  
3416 3416 qemu_register_reset(piix3_reset, d);
3417 3417 piix3_reset(d);
... ...
hw/macio.c
  View file @6407f37
... ... @@ -110,7 +110,7 @@ void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
110 110 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
111 111 pci_config_set_device_id(d->config, device_id);
112 112 pci_config_set_class(d->config, PCI_CLASS_OTHERS << 8);
113   - d->config[0x0e] = 0x00; // header_type
  113 + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
114 114  
115 115 d->config[0x3d] = 0x01; // interrupt on pin 1
116 116  
... ...
hw/ne2000.c
  View file @6407f37
... ... @@ -817,7 +817,7 @@ PCIDevice *pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn)
817 817 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
818 818 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8029);
819 819 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
820   - pci_conf[0x0e] = 0x00; // header_type
  820 + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
821 821 pci_conf[0x3d] = 1; // interrupt pin 0
822 822  
823 823 pci_register_io_region(&d->dev, 0, 0x100,
... ...
hw/openpic.c
  View file @6407f37
... ... @@ -1208,7 +1208,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
1208 1208 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
1209 1209 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_OPENPIC2);
1210 1210 pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER); // FIXME?
1211   - pci_conf[0x0e] = 0x00; // header_type
  1211 + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
1212 1212 pci_conf[0x3d] = 0x00; // no interrupt pin
1213 1213  
1214 1214 /* Register I/O spaces */
... ...
hw/pci.c
  View file @6407f37
... ... @@ -883,7 +883,8 @@ PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
883 883 s->dev.config[0x09] = 0x00; // programming i/f
884 884 pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
885 885 s->dev.config[0x0D] = 0x10; // latency_timer
886   - s->dev.config[0x0E] = 0x81; // header_type
  886 + s->dev.config[PCI_HEADER_TYPE] =
  887 + PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
887 888 s->dev.config[0x1E] = 0xa0; // secondary status
888 889  
889 890 s->bus = pci_register_secondary_bus(&s->dev, map_irq);
... ...
hw/pci.h
  View file @6407f37
... ... @@ -102,6 +102,10 @@ typedef struct PCIIORegion {
102 102 #define PCI_REVISION_ID 0x08 /* 8 bits */
103 103 #define PCI_CLASS_DEVICE 0x0a /* Device class */
104 104 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
  105 +#define PCI_HEADER_TYPE_NORMAL 0
  106 +#define PCI_HEADER_TYPE_BRIDGE 1
  107 +#define PCI_HEADER_TYPE_CARDBUS 2
  108 +#define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
105 109 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c /* 16 bits */
106 110 #define PCI_SUBSYSTEM_ID 0x2e /* 16 bits */
107 111 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
... ...
hw/pcnet.c
  View file @6407f37
... ... @@ -2037,7 +2037,7 @@ PCIDevice *pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn)
2037 2037 pci_conf[0x08] = 0x10;
2038 2038 pci_conf[0x09] = 0x00;
2039 2039 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
2040   - pci_conf[0x0e] = 0x00; // header_type
  2040 + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
2041 2041  
2042 2042 *(uint32_t *)&pci_conf[0x10] = cpu_to_le32(0x00000001);
2043 2043 *(uint32_t *)&pci_conf[0x14] = cpu_to_le32(0x00000000);
... ...
hw/piix_pci.c
  View file @6407f37
... ... @@ -196,7 +196,7 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
196 196 pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_82441);
197 197 d->config[0x08] = 0x02; // revision
198 198 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
199   - d->config[0x0e] = 0x00; // header_type
  199 + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
200 200  
201 201 d->config[0x72] = 0x02; /* SMRAM */
202 202  
... ... @@ -334,7 +334,8 @@ int piix3_init(PCIBus *bus, int devfn)
334 334 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
335 335 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
336 336 pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
337   - pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
  337 + pci_conf[PCI_HEADER_TYPE] =
  338 + PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
338 339  
339 340 piix3_reset(d);
340 341 return d->devfn;
... ... @@ -355,7 +356,9 @@ int piix4_init(PCIBus *bus, int devfn)
355 356 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
356 357 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_0); // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
357 358 pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
358   - pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
  359 + pci_conf[PCI_HEADER_TYPE] =
  360 + PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
  361 +
359 362  
360 363 piix4_reset(d);
361 364 return d->devfn;
... ...
hw/prep_pci.c
  View file @6407f37
... ... @@ -161,7 +161,7 @@ PCIBus *pci_prep_init(qemu_irq *pic)
161 161 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
162 162 d->config[0x0C] = 0x08; // cache_line_size
163 163 d->config[0x0D] = 0x10; // latency_timer
164   - d->config[0x0E] = 0x00; // header_type
  164 + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
165 165 d->config[0x34] = 0x00; // capabilities_pointer
166 166  
167 167 return s->bus;
... ...
hw/rtl8139.c
  View file @6407f37
... ... @@ -3462,7 +3462,7 @@ PCIDevice *pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn)
3462 3462 pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */
3463 3463 pci_conf[0x08] = RTL8139_PCI_REVID; /* PCI revision ID; >=0x20 is for 8139C+ */
3464 3464 pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
3465   - pci_conf[0x0e] = 0x00; /* header_type */
  3465 + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; /* header_type */
3466 3466 pci_conf[0x3d] = 1; /* interrupt pin 0 */
3467 3467 pci_conf[0x34] = 0xdc;
3468 3468  
... ...
hw/sun4u.c
  View file @6407f37
... ... @@ -318,7 +318,7 @@ pci_ebus_init(PCIBus *bus, int devfn)
318 318 s->config[0x09] = 0x00; // programming i/f
319 319 pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
320 320 s->config[0x0D] = 0x0a; // latency_timer
321   - s->config[0x0E] = 0x00; // header_type
  321 + s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
322 322  
323 323 pci_register_io_region(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM,
324 324 ebus_mmio_mapfunc);
... ...
hw/unin_pci.c
  View file @6407f37
... ... @@ -192,7 +192,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
192 192 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
193 193 d->config[0x0C] = 0x08; // cache_line_size
194 194 d->config[0x0D] = 0x10; // latency_timer
195   - d->config[0x0E] = 0x00; // header_type
  195 + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
196 196 d->config[0x34] = 0x00; // capabilities_pointer
197 197  
198 198 #if 0 // XXX: not activated as PPC BIOS doesn't handle multiple buses properly
... ... @@ -205,7 +205,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
205 205 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
206 206 d->config[0x0C] = 0x08; // cache_line_size
207 207 d->config[0x0D] = 0x20; // latency_timer
208   - d->config[0x0E] = 0x01; // header_type
  208 + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_BRIDGE; // header_type
209 209  
210 210 d->config[0x18] = 0x01; // primary_bus
211 211 d->config[0x19] = 0x02; // secondary_bus
... ... @@ -240,7 +240,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
240 240 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
241 241 d->config[0x0C] = 0x08; // cache_line_size
242 242 d->config[0x0D] = 0x10; // latency_timer
243   - d->config[0x0E] = 0x00; // header_type
  243 + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
244 244 // d->config[0x34] = 0x80; // capabilities_pointer
245 245  
246 246 #if 0 // XXX: not needed for now
... ... @@ -261,7 +261,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
261 261 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
262 262 d->config[0x0C] = 0x08; // cache_line_size
263 263 d->config[0x0D] = 0x10; // latency_timer
264   - d->config[0x0E] = 0x00; // header_type
  264 + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
265 265 d->config[0x34] = 0x00; // capabilities_pointer
266 266 #endif
267 267 register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, d);
... ...
hw/usb-uhci.c
  View file @6407f37
... ... @@ -1084,7 +1084,7 @@ void usb_uhci_piix3_init(PCIBus *bus, int devfn)
1084 1084 pci_conf[0x08] = 0x01; // revision number
1085 1085 pci_conf[0x09] = 0x00;
1086 1086 pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB);
1087   - pci_conf[0x0e] = 0x00; // header_type
  1087 + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
1088 1088 pci_conf[0x3d] = 4; // interrupt pin 3
1089 1089 pci_conf[0x60] = 0x10; // release number
1090 1090  
... ... @@ -1118,7 +1118,7 @@ void usb_uhci_piix4_init(PCIBus *bus, int devfn)
1118 1118 pci_conf[0x08] = 0x01; // revision number
1119 1119 pci_conf[0x09] = 0x00;
1120 1120 pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB);
1121   - pci_conf[0x0e] = 0x00; // header_type
  1121 + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
1122 1122 pci_conf[0x3d] = 4; // interrupt pin 3
1123 1123 pci_conf[0x60] = 0x10; // release number
1124 1124  
... ...
hw/vga.c
  View file @6407f37
... ... @@ -2507,7 +2507,7 @@ int pci_vga_init(PCIBus *bus, int vga_ram_size,
2507 2507 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_QEMU);
2508 2508 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_QEMU_VGA);
2509 2509 pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
2510   - pci_conf[0x0e] = 0x00; // header_type
  2510 + pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
2511 2511  
2512 2512 /* XXX: vga_ram_size must be a power of two */
2513 2513 pci_register_io_region(&d->dev, 0, vga_ram_size,
... ...
hw/virtio.c
  View file @6407f37
... ... @@ -788,7 +788,7 @@ VirtIODevice *virtio_init_pci(PCIBus *bus, const char *name,
788 788  
789 789 config[0x09] = pif;
790 790 pci_config_set_class(config, class_code);
791   - config[0x0e] = 0x00;
  791 + config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
792 792  
793 793 config[0x2c] = subvendor & 0xFF;
794 794 config[0x2d] = (subvendor >> 8) & 0xFF;
... ...
hw/vmware_vga.c
  View file @6407f37
... ... @@ -1210,8 +1210,6 @@ static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
1210 1210 iomemtype);
1211 1211 }
1212 1212  
1213   -#define PCI_CLASS_HEADERTYPE_00h 0x00
1214   -
1215 1213 void pci_vmsvga_init(PCIBus *bus, int vga_ram_size)
1216 1214 {
1217 1215 struct pci_vmsvga_state_s *s;
... ... @@ -1226,7 +1224,7 @@ void pci_vmsvga_init(PCIBus *bus, int vga_ram_size)
1226 1224 pci_config_set_class(s->card.config, PCI_CLASS_DISPLAY_VGA);
1227 1225 s->card.config[0x0c] = 0x08; /* Cache line size */
1228 1226 s->card.config[0x0d] = 0x40; /* Latency timer */
1229   - s->card.config[0x0e] = PCI_CLASS_HEADERTYPE_00h;
  1227 + s->card.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL;
1230 1228 s->card.config[0x2c] = PCI_VENDOR_ID_VMWARE & 0xff;
1231 1229 s->card.config[0x2d] = PCI_VENDOR_ID_VMWARE >> 8;
1232 1230 s->card.config[0x2e] = SVGA_PCI_DEVICE_ID & 0xff;
... ...