gwj / at91sam9263 · Commits

Commit 173a543b36d0b2491438cf1dcc2c7bb34d59bb5c

Authored by blueswir1
1 parent 4ebcf884

Add and use #defines for PCI device classes 

This patch adds and uses #defines for PCI device classes and subclases,
using a new pci_config_set_class() function, similar to the recently
added pci_config_set_vendor_id() and pci_config_set_device_id().

Change since v1: fixed compilation of hw/sun4u.c

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6491 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 34 changed files with 81 additions and 86 deletions
hw/ac97.c
  View file @173a543
... ... @@ -1347,8 +1347,7 @@ int ac97_init (PCIBus *bus, AudioState *audio)
1347 1347  
1348 1348 c[0x08] = 0x01; /* rid revision ro */
1349 1349 c[0x09] = 0x00; /* pi programming interface ro */
1350   - c[0x0a] = 0x01; /* scc sub class code ro */
1351   - c[0x0b] = 0x04; /* bcc base class code ro */
  1350 + pci_config_set_class(c, PCI_CLASS_MULTIMEDIA_AUDIO); /* ro */
1352 1351 c[0x0e] = 0x00; /* headtyp header type ro */
1353 1352  
1354 1353 c[0x10] = 0x01; /* nabmar native audio mixer base
... ...
hw/acpi.c
  View file @173a543
... ... @@ -509,8 +509,7 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
509 509 pci_conf[0x07] = 0x02;
510 510 pci_conf[0x08] = 0x03; // revision number
511 511 pci_conf[0x09] = 0x00;
512   - pci_conf[0x0a] = 0x80; // other bridge device
513   - pci_conf[0x0b] = 0x06; // bridge device
  512 + pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
514 513 pci_conf[0x0e] = 0x00; // header_type
515 514 pci_conf[0x3d] = 0x01; // interrupt pin 1
516 515  
... ...
hw/apb_pci.c
  View file @173a543
... ... @@ -260,8 +260,7 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
260 260 d->config[0x07] = 0x03; // status = medium devsel
261 261 d->config[0x08] = 0x00; // revision
262 262 d->config[0x09] = 0x00; // programming i/f
263   - d->config[0x0A] = 0x00; // class_sub = pci host
264   - d->config[0x0B] = 0x06; // class_base = PCI_bridge
  263 + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
265 264 d->config[0x0D] = 0x10; // latency_timer
266 265 d->config[0x0E] = 0x00; // header_type
267 266  
... ...
hw/cirrus_vga.c
  View file @173a543
... ... @@ -3378,8 +3378,7 @@ void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
3378 3378 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CIRRUS);
3379 3379 pci_config_set_device_id(pci_conf, device_id);
3380 3380 pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
3381   - pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
3382   - pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
  3381 + pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
3383 3382 pci_conf[0x0e] = PCI_CLASS_HEADERTYPE_00h;
3384 3383  
3385 3384 /* setup VGA */
... ...
hw/e1000.c
  View file @173a543
... ... @@ -1054,8 +1054,7 @@ pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn)
1054 1054 *(uint16_t *)(pci_conf+0x04) = cpu_to_le16(0x0407);
1055 1055 *(uint16_t *)(pci_conf+0x06) = cpu_to_le16(0x0010);
1056 1056 pci_conf[0x08] = 0x03;
1057   - pci_conf[0x0a] = 0x00; // ethernet network controller
1058   - pci_conf[0x0b] = 0x02;
  1057 + pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
1059 1058 pci_conf[0x0c] = 0x10;
1060 1059  
1061 1060 pci_conf[0x3d] = 1; // interrupt pin 0
... ...
hw/eepro100.c
  View file @173a543
... ... @@ -433,8 +433,7 @@ static void pci_reset(EEPRO100State * s)
433 433 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
434 434 /* PCI Class Code */
435 435 PCI_CONFIG_8(0x09, 0x00);
436   - PCI_CONFIG_8(PCI_SUBCLASS_CODE, 0x00); // ethernet network controller
437   - PCI_CONFIG_8(PCI_CLASS_CODE, 0x02); // network controller
  436 + pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
438 437 /* PCI Cache Line Size */
439 438 /* check cache line size!!! */
440 439 //~ PCI_CONFIG_8(0x0c, 0x00);
... ...
hw/es1370.c
  View file @173a543
... ... @@ -1034,8 +1034,7 @@ int es1370_init (PCIBus *bus, AudioState *audio)
1034 1034 pci_config_set_vendor_id(c, PCI_VENDOR_ID_ENSONIQ);
1035 1035 pci_config_set_device_id(c, PCI_DEVICE_ID_ENSONIQ_ES1370);
1036 1036 c[0x07] = 2 << 1;
1037   - c[0x0a] = 0x01;
1038   - c[0x0b] = 0x04;
  1037 + pci_config_set_class(c, PCI_CLASS_MULTIMEDIA_AUDIO);
1039 1038  
1040 1039 #if 1
1041 1040 c[0x2c] = 0x42;
... ...
hw/grackle_pci.c
  View file @173a543
... ... @@ -148,8 +148,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
148 148 pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_MPC106);
149 149 d->config[0x08] = 0x00; // revision
150 150 d->config[0x09] = 0x01;
151   - d->config[0x0a] = 0x00; // class_sub = host
152   - d->config[0x0b] = 0x06; // class_base = PCI_bridge
  151 + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
153 152 d->config[0x0e] = 0x00; // header_type
154 153  
155 154 #if 0
... ... @@ -157,8 +156,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
157 156 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
158 157 pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
159 158 d->config[0x08] = 0x02; // revision
160   - d->config[0x0a] = 0x04; // class_sub = pci2pci
161   - d->config[0x0b] = 0x06; // class_base = PCI_bridge
  159 + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
162 160 d->config[0x0e] = 0x01; // header_type
163 161  
164 162 d->config[0x18] = 0x0; // primary_bus
... ...
hw/gt64xxx.c
  View file @173a543
... ... @@ -1146,8 +1146,7 @@ PCIBus *pci_gt64120_init(qemu_irq *pic)
1146 1146  
1147 1147 d->config[0x08] = 0x10;
1148 1148 d->config[0x09] = 0x00;
1149   - d->config[0x0A] = 0x00;
1150   - d->config[0x0B] = 0x06;
  1149 + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
1151 1150  
1152 1151 d->config[0x10] = 0x08;
1153 1152 d->config[0x14] = 0x08;
... ...
hw/ide.c
  View file @173a543
... ... @@ -3353,8 +3353,7 @@ void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
3353 3353 pci_conf[0x08] = 0x07; // IDE controller revision
3354 3354 pci_conf[0x09] = 0x8f;
3355 3355  
3356   - pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
3357   - pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
  3356 + pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
3358 3357 pci_conf[0x0e] = 0x00; // header_type
3359 3358  
3360 3359 pci_conf[0x51] = 0x04; // enable IDE0
... ... @@ -3423,8 +3422,7 @@ void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
3423 3422 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
3424 3423 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_1);
3425 3424 pci_conf[0x09] = 0x80; // legacy ATA mode
3426   - pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
3427   - pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
  3425 + pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
3428 3426 pci_conf[0x0e] = 0x00; // header_type
3429 3427  
3430 3428 qemu_register_reset(piix3_reset, d);
... ... @@ -3460,8 +3458,7 @@ void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
3460 3458 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
3461 3459 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB);
3462 3460 pci_conf[0x09] = 0x80; // legacy ATA mode
3463   - pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
3464   - pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
  3461 + pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
3465 3462 pci_conf[0x0e] = 0x00; // header_type
3466 3463  
3467 3464 qemu_register_reset(piix3_reset, d);
... ...
hw/lsi53c895a.c
  View file @173a543
... ... @@ -1979,7 +1979,7 @@ void *lsi_scsi_init(PCIBus *bus, int devfn)
1979 1979 /* PCI device ID (word) */
1980 1980 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_LSI_53C895A);
1981 1981 /* PCI base class code */
1982   - pci_conf[0x0b] = 0x01;
  1982 + pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_SCSI);
1983 1983 /* PCI subsystem ID */
1984 1984 pci_conf[0x2e] = 0x00;
1985 1985 pci_conf[0x2f] = 0x10;
... ...
hw/macio.c
  View file @173a543
... ... @@ -109,9 +109,7 @@ void macio_init (PCIBus *bus, int device_id, int is_oldworld, int pic_mem_index,
109 109  
110 110 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
111 111 pci_config_set_device_id(d->config, device_id);
112   -
113   - d->config[0x0a] = 0x00; // class_sub = pci2pci
114   - d->config[0x0b] = 0xff; // class_base = bridge
  112 + pci_config_set_class(d->config, PCI_CLASS_OTHERS << 8);
115 113 d->config[0x0e] = 0x00; // header_type
116 114  
117 115 d->config[0x3d] = 0x01; // interrupt on pin 1
... ...
hw/ne2000.c
  View file @173a543
... ... @@ -792,8 +792,7 @@ void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn)
792 792 pci_conf = d->dev.config;
793 793 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
794 794 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_RTL8029);
795   - pci_conf[0x0a] = 0x00; // ethernet network controller
796   - pci_conf[0x0b] = 0x02;
  795 + pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
797 796 pci_conf[0x0e] = 0x00; // header_type
798 797 pci_conf[0x3d] = 1; // interrupt pin 0
799 798  
... ...
hw/openpic.c
  View file @173a543
... ... @@ -1019,8 +1019,7 @@ qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
1019 1019 pci_conf = opp->pci_dev.config;
1020 1020 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
1021 1021 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_OPENPIC2);
1022   - pci_conf[0x0a] = 0x80; // PIC
1023   - pci_conf[0x0b] = 0x08;
  1022 + pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER); // FIXME?
1024 1023 pci_conf[0x0e] = 0x00; // header_type
1025 1024 pci_conf[0x3d] = 0x00; // no interrupt pin
1026 1025  
... ...
hw/pci.c
  View file @173a543
... ... @@ -729,8 +729,7 @@ PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
729 729 s->dev.config[0x07] = 0x00; // status = fast devsel
730 730 s->dev.config[0x08] = 0x00; // revision
731 731 s->dev.config[0x09] = 0x00; // programming i/f
732   - s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge
733   - s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge
  732 + pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
734 733 s->dev.config[0x0D] = 0x10; // latency_timer
735 734 s->dev.config[0x0E] = 0x81; // header_type
736 735 s->dev.config[0x1E] = 0xa0; // secondary status
... ...
hw/pci.h
  View file @173a543
... ... @@ -8,6 +8,36 @@
8 8  
9 9 extern target_phys_addr_t pci_mem_base;
10 10  
  11 +/* Device classes and subclasses */
  12 +
  13 +#define PCI_CLASS_STORAGE_SCSI 0x0100
  14 +#define PCI_CLASS_STORAGE_IDE 0x0101
  15 +#define PCI_CLASS_STORAGE_OTHER 0x0180
  16 +
  17 +#define PCI_CLASS_NETWORK_ETHERNET 0x0200
  18 +
  19 +#define PCI_CLASS_DISPLAY_VGA 0x0300
  20 +#define PCI_CLASS_DISPLAY_OTHER 0x0380
  21 +
  22 +#define PCI_CLASS_MULTIMEDIA_AUDIO 0x0401
  23 +
  24 +#define PCI_CLASS_MEMORY_RAM 0x0500
  25 +
  26 +#define PCI_CLASS_SYSTEM_OTHER 0x0880
  27 +
  28 +#define PCI_CLASS_SERIAL_USB 0x0c03
  29 +
  30 +#define PCI_CLASS_BRIDGE_HOST 0x0600
  31 +#define PCI_CLASS_BRIDGE_ISA 0x0601
  32 +#define PCI_CLASS_BRIDGE_PCI 0x0604
  33 +#define PCI_CLASS_BRIDGE_OTHER 0x0680
  34 +
  35 +#define PCI_CLASS_PROCESSOR_CO 0x0b40
  36 +
  37 +#define PCI_CLASS_OTHERS 0xff
  38 +
  39 +/* Vendors and devices. */
  40 +
11 41 #define PCI_VENDOR_ID_LSI_LOGIC 0x1000
12 42 #define PCI_DEVICE_ID_LSI_53C895A 0x0012
13 43  
... ... @@ -209,6 +239,12 @@ pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
209 239 cpu_to_le16wu((uint16_t *)&pci_config[PCI_DEVICE_ID], val);
210 240 }
211 241  
  242 +static inline void
  243 +pci_config_set_class(uint8_t *pci_config, uint16_t val)
  244 +{
  245 + cpu_to_le16wu((uint16_t *)&pci_config[PCI_CLASS_DEVICE], val);
  246 +}
  247 +
212 248 /* lsi53c895a.c */
213 249 #define LSI_MAX_DEVS 7
214 250 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
... ...
hw/pcnet.c
  View file @173a543
... ... @@ -2006,8 +2006,7 @@ void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn)
2006 2006 *(uint16_t *)&pci_conf[0x06] = cpu_to_le16(0x0280);
2007 2007 pci_conf[0x08] = 0x10;
2008 2008 pci_conf[0x09] = 0x00;
2009   - pci_conf[0x0a] = 0x00; // ethernet network controller
2010   - pci_conf[0x0b] = 0x02;
  2009 + pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
2011 2010 pci_conf[0x0e] = 0x00; // header_type
2012 2011  
2013 2012 *(uint32_t *)&pci_conf[0x10] = cpu_to_le32(0x00000001);
... ...
hw/piix_pci.c
  View file @173a543
... ... @@ -195,8 +195,7 @@ PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
195 195 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
196 196 pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_82441);
197 197 d->config[0x08] = 0x02; // revision
198   - d->config[0x0a] = 0x00; // class_sub = host2pci
199   - d->config[0x0b] = 0x06; // class_base = PCI_bridge
  198 + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
200 199 d->config[0x0e] = 0x00; // header_type
201 200  
202 201 d->config[0x72] = 0x02; /* SMRAM */
... ... @@ -337,8 +336,7 @@ int piix3_init(PCIBus *bus, int devfn)
337 336  
338 337 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
339 338 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
340   - pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
341   - pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
  339 + pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
342 340 pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
343 341  
344 342 piix3_reset(d);
... ... @@ -359,8 +357,7 @@ int piix4_init(PCIBus *bus, int devfn)
359 357  
360 358 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
361 359 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_0); // 82371AB/EB/MB PIIX4 PCI-to-ISA bridge
362   - pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
363   - pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
  360 + pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
364 361 pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
365 362  
366 363 piix4_reset(d);
... ...
hw/ppc4xx_pci.c
  View file @173a543
... ... @@ -382,8 +382,7 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
382 382 pci_conf = controller->pci_dev->config;
383 383 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
384 384 pci_config_set_device_id(pci_conf, 0x027f); // device_id
385   - pci_conf[0x0a] = 0x80; // class_sub = other bridge type
386   - pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
  385 + pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
387 386  
388 387 /* CFGADDR */
389 388 index = cpu_register_io_memory(0, pci4xx_cfgaddr_read,
... ...
hw/prep_pci.c
  View file @173a543
... ... @@ -158,8 +158,7 @@ PCIBus *pci_prep_init(qemu_irq *pic)
158 158 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_MOTOROLA);
159 159 pci_config_set_device_id(d->config, PCI_DEVICE_ID_MOTOROLA_RAVEN);
160 160 d->config[0x08] = 0x00; // revision
161   - d->config[0x0A] = 0x00; // class_sub = pci host
162   - d->config[0x0B] = 0x06; // class_base = PCI_bridge
  161 + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
163 162 d->config[0x0C] = 0x08; // cache_line_size
164 163 d->config[0x0D] = 0x10; // latency_timer
165 164 d->config[0x0E] = 0x00; // header_type
... ...
hw/rtl8139.c
  View file @173a543
... ... @@ -3429,8 +3429,7 @@ void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn)
3429 3429 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139);
3430 3430 pci_conf[0x04] = 0x05; /* command = I/O space, Bus Master */
3431 3431 pci_conf[0x08] = RTL8139_PCI_REVID; /* PCI revision ID; >=0x20 is for 8139C+ */
3432   - pci_conf[0x0a] = 0x00; /* ethernet network controller */
3433   - pci_conf[0x0b] = 0x02;
  3432 + pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
3434 3433 pci_conf[0x0e] = 0x00; /* header_type */
3435 3434 pci_conf[0x3d] = 1; /* interrupt pin 0 */
3436 3435 pci_conf[0x34] = 0xdc;
... ...
hw/sun4u.c
  View file @173a543
... ... @@ -373,8 +373,7 @@ pci_ebus_init(PCIBus *bus, int devfn)
373 373 s->config[0x07] = 0x03; // status = medium devsel
374 374 s->config[0x08] = 0x01; // revision
375 375 s->config[0x09] = 0x00; // programming i/f
376   - s->config[0x0A] = 0x80; // class_sub = misc bridge
377   - s->config[0x0B] = 0x06; // class_base = PCI_bridge
  376 + pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
378 377 s->config[0x0D] = 0x0a; // latency_timer
379 378 s->config[0x0E] = 0x00; // header_type
380 379  
... ...
hw/unin_pci.c
  View file @173a543
... ... @@ -177,8 +177,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
177 177 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
178 178 pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_PCI);
179 179 d->config[0x08] = 0x00; // revision
180   - d->config[0x0A] = 0x00; // class_sub = pci host
181   - d->config[0x0B] = 0x06; // class_base = PCI_bridge
  180 + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
182 181 d->config[0x0C] = 0x08; // cache_line_size
183 182 d->config[0x0D] = 0x10; // latency_timer
184 183 d->config[0x0E] = 0x00; // header_type
... ... @@ -191,8 +190,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
191 190 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_DEC);
192 191 pci_config_set_device_id(d->config, PCI_DEVICE_ID_DEC_21154);
193 192 d->config[0x08] = 0x05; // revision
194   - d->config[0x0A] = 0x04; // class_sub = pci2pci
195   - d->config[0x0B] = 0x06; // class_base = PCI_bridge
  193 + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
196 194 d->config[0x0C] = 0x08; // cache_line_size
197 195 d->config[0x0D] = 0x20; // latency_timer
198 196 d->config[0x0E] = 0x01; // header_type
... ... @@ -228,8 +226,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
228 226 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
229 227 pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_AGP);
230 228 d->config[0x08] = 0x00; // revision
231   - d->config[0x0A] = 0x00; // class_sub = pci host
232   - d->config[0x0B] = 0x06; // class_base = PCI_bridge
  229 + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
233 230 d->config[0x0C] = 0x08; // cache_line_size
234 231 d->config[0x0D] = 0x10; // latency_timer
235 232 d->config[0x0E] = 0x00; // header_type
... ... @@ -251,8 +248,7 @@ PCIBus *pci_pmac_init(qemu_irq *pic)
251 248 pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE);
252 249 pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI);
253 250 d->config[0x08] = 0x00; // revision
254   - d->config[0x0A] = 0x00; // class_sub = pci host
255   - d->config[0x0B] = 0x06; // class_base = PCI_bridge
  251 + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
256 252 d->config[0x0C] = 0x08; // cache_line_size
257 253 d->config[0x0D] = 0x10; // latency_timer
258 254 d->config[0x0E] = 0x00; // header_type
... ...
hw/usb-ohci.c
  View file @173a543
... ... @@ -1682,8 +1682,7 @@ void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn)
1682 1682 pci_config_set_vendor_id(ohci->pci_dev.config, PCI_VENDOR_ID_APPLE);
1683 1683 pci_config_set_device_id(ohci->pci_dev.config, 0x003f); // device_id
1684 1684 ohci->pci_dev.config[0x09] = 0x10; /* OHCI */
1685   - ohci->pci_dev.config[0x0a] = 0x3;
1686   - ohci->pci_dev.config[0x0b] = 0xc;
  1685 + pci_config_set_class(ohci->pci_dev.config, PCI_CLASS_SERIAL_USB);
1687 1686 ohci->pci_dev.config[0x3d] = 0x01; /* interrupt pin 1 */
1688 1687  
1689 1688 usb_ohci_init(&ohci->state, num_ports, devfn, ohci->pci_dev.irq[0],
... ...
hw/usb-uhci.c
  View file @173a543
... ... @@ -1084,8 +1084,7 @@ void usb_uhci_piix3_init(PCIBus *bus, int devfn)
1084 1084 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_2);
1085 1085 pci_conf[0x08] = 0x01; // revision number
1086 1086 pci_conf[0x09] = 0x00;
1087   - pci_conf[0x0a] = 0x03;
1088   - pci_conf[0x0b] = 0x0c;
  1087 + pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB);
1089 1088 pci_conf[0x0e] = 0x00; // header_type
1090 1089 pci_conf[0x3d] = 4; // interrupt pin 3
1091 1090 pci_conf[0x60] = 0x10; // release number
... ... @@ -1119,8 +1118,7 @@ void usb_uhci_piix4_init(PCIBus *bus, int devfn)
1119 1118 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_2);
1120 1119 pci_conf[0x08] = 0x01; // revision number
1121 1120 pci_conf[0x09] = 0x00;
1122   - pci_conf[0x0a] = 0x03;
1123   - pci_conf[0x0b] = 0x0c;
  1121 + pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB);
1124 1122 pci_conf[0x0e] = 0x00; // header_type
1125 1123 pci_conf[0x3d] = 4; // interrupt pin 3
1126 1124 pci_conf[0x60] = 0x10; // release number
... ...
hw/versatile_pci.c
  View file @173a543
... ... @@ -133,8 +133,7 @@ PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview)
133 133 d->config[0x07] = 0x02;
134 134 d->config[0x08] = 0x00; // revision
135 135 d->config[0x09] = 0x00; // programming i/f
136   - d->config[0x0A] = 0x40; // class_sub = pci host
137   - d->config[0x0B] = 0x0b; // class_base = PCI_bridge
  136 + pci_config_set_class(d->config, PCI_CLASS_PROCESSOR_CO);
138 137 d->config[0x0D] = 0x10; // latency_timer
139 138  
140 139 return s;
... ...
hw/vga.c
  View file @173a543
... ... @@ -2513,8 +2513,7 @@ int pci_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
2513 2513 // dummy VGA (same as Bochs ID)
2514 2514 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_QEMU);
2515 2515 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_QEMU_VGA);
2516   - pci_conf[0x0a] = 0x00; // VGA controller
2517   - pci_conf[0x0b] = 0x03;
  2516 + pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
2518 2517 pci_conf[0x0e] = 0x00; // header_type
2519 2518  
2520 2519 /* XXX: vga_ram_size must be a power of two */
... ...
hw/virtio-balloon.c
  View file @173a543
... ... @@ -176,7 +176,7 @@ void *virtio_balloon_init(PCIBus *bus)
176 176 PCI_DEVICE_ID_VIRTIO_BALLOON,
177 177 PCI_VENDOR_ID_REDHAT_QUMRANET,
178 178 VIRTIO_ID_BALLOON,
179   - 0x05, 0x00, 0x00,
  179 + PCI_CLASS_MEMORY_RAM, 0x00,
180 180 8, sizeof(VirtIOBalloon));
181 181 if (s == NULL)
182 182 return NULL;
... ...
hw/virtio-blk.c
  View file @173a543
... ... @@ -305,7 +305,7 @@ void *virtio_blk_init(PCIBus *bus, BlockDriverState *bs)
305 305 PCI_DEVICE_ID_VIRTIO_BLOCK,
306 306 PCI_VENDOR_ID_REDHAT_QUMRANET,
307 307 VIRTIO_ID_BLOCK,
308   - 0x01, 0x80, 0x00,
  308 + PCI_CLASS_STORAGE_OTHER, 0x00,
309 309 sizeof(struct virtio_blk_config), sizeof(VirtIOBlock));
310 310 if (!s)
311 311 return NULL;
... ...
hw/virtio-console.c
  View file @173a543
... ... @@ -130,7 +130,7 @@ void *virtio_console_init(PCIBus *bus, CharDriverState *chr)
130 130 PCI_DEVICE_ID_VIRTIO_CONSOLE,
131 131 PCI_VENDOR_ID_REDHAT_QUMRANET,
132 132 VIRTIO_ID_CONSOLE,
133   - 0x03, 0x80, 0x00,
  133 + PCI_CLASS_DISPLAY_OTHER, 0x00,
134 134 0, sizeof(VirtIOConsole));
135 135 if (s == NULL)
136 136 return NULL;
... ...
hw/virtio-net.c
  View file @173a543
... ... @@ -325,7 +325,7 @@ void virtio_net_init(PCIBus *bus, NICInfo *nd, int devfn)
325 325 PCI_DEVICE_ID_VIRTIO_NET,
326 326 PCI_VENDOR_ID_REDHAT_QUMRANET,
327 327 VIRTIO_ID_NET,
328   - 0x02, 0x00, 0x00,
  328 + PCI_CLASS_NETWORK_ETHERNET, 0x00,
329 329 sizeof(struct virtio_net_config),
330 330 sizeof(VirtIONet));
331 331 if (!n)
... ...
hw/virtio.c
  View file @173a543
... ... @@ -811,9 +811,8 @@ void virtio_load(VirtIODevice *vdev, QEMUFile *f)
811 811 VirtIODevice *virtio_init_pci(PCIBus *bus, const char *name,
812 812 uint16_t vendor, uint16_t device,
813 813 uint16_t subvendor, uint16_t subdevice,
814   - uint8_t class_code, uint8_t subclass_code,
815   - uint8_t pif, size_t config_size,
816   - size_t struct_size)
  814 + uint16_t class_code, uint8_t pif,
  815 + size_t config_size, size_t struct_size)
817 816 {
818 817 VirtIODevice *vdev;
819 818 PCIDevice *pci_dev;
... ... @@ -839,8 +838,7 @@ VirtIODevice *virtio_init_pci(PCIBus *bus, const char *name,
839 838 config[0x08] = VIRTIO_PCI_ABI_VERSION;
840 839  
841 840 config[0x09] = pif;
842   - config[0x0a] = subclass_code;
843   - config[0x0b] = class_code;
  841 + pci_config_set_class(config, class_code);
844 842 config[0x0e] = 0x00;
845 843  
846 844 config[0x2c] = subvendor & 0xFF;
... ...
hw/virtio.h
  View file @173a543
... ... @@ -92,9 +92,8 @@ struct VirtIODevice
92 92 VirtIODevice *virtio_init_pci(PCIBus *bus, const char *name,
93 93 uint16_t vendor, uint16_t device,
94 94 uint16_t subvendor, uint16_t subdevice,
95   - uint8_t class_code, uint8_t subclass_code,
96   - uint8_t pif, size_t config_size,
97   - size_t struct_size);
  95 + uint16_t class_code, uint8_t pif,
  96 + size_t config_size, size_t struct_size);
98 97  
99 98 VirtQueue *virtio_add_queue(VirtIODevice *vdev, int queue_size,
100 99 void (*handle_output)(VirtIODevice *,
... ...
hw/vmware_vga.c
  View file @173a543
... ... @@ -1204,8 +1204,6 @@ static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
1204 1204 iomemtype);
1205 1205 }
1206 1206  
1207   -#define PCI_CLASS_BASE_DISPLAY 0x03
1208   -#define PCI_CLASS_SUB_VGA 0x00
1209 1207 #define PCI_CLASS_HEADERTYPE_00h 0x00
1210 1208  
1211 1209 void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
... ... @@ -1220,8 +1218,7 @@ void pci_vmsvga_init(PCIBus *bus, uint8_t *vga_ram_base,
1220 1218 pci_config_set_vendor_id(s->card.config, PCI_VENDOR_ID_VMWARE);
1221 1219 pci_config_set_device_id(s->card.config, SVGA_PCI_DEVICE_ID);
1222 1220 s->card.config[PCI_COMMAND] = 0x07; /* I/O + Memory */
1223   - s->card.config[PCI_CLASS_DEVICE] = PCI_CLASS_SUB_VGA;
1224   - s->card.config[0x0b] = PCI_CLASS_BASE_DISPLAY;
  1221 + pci_config_set_class(s->card.config, PCI_CLASS_DISPLAY_VGA);
1225 1222 s->card.config[0x0c] = 0x08; /* Cache line size */
1226 1223 s->card.config[0x0d] = 0x40; /* Latency timer */
1227 1224 s->card.config[0x0e] = PCI_CLASS_HEADERTYPE_00h;
... ...