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/*
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* virtual page mapping and translated block handling
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*
* Copyright ( c ) 2003 Fabrice Bellard
*
* This library is free software ; you can redistribute it and / or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation ; either
* version 2 of the License , or ( at your option ) any later version .
*
* This library is distributed in the hope that it will be useful ,
* but WITHOUT ANY WARRANTY ; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE . See the GNU
* Lesser General Public License for more details .
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library ; if not , write to the Free Software
* Foundation , Inc ., 59 Temple Place , Suite 330 , Boston , MA 02111 - 1307 USA
*/
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# include "config.h"
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# ifdef _WIN32
# include < windows . h >
# else
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# include < sys / types . h >
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# include < sys / mman . h >
# endif
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# include < stdlib . h >
# include < stdio . h >
# include < stdarg . h >
# include < string . h >
# include < errno . h >
# include < unistd . h >
# include < inttypes . h >
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# include "cpu.h"
# include "exec-all.h"
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# if defined ( CONFIG_USER_ONLY )
# include < qemu . h >
# endif
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// # define DEBUG_TB_INVALIDATE
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// # define DEBUG_FLUSH
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// # define DEBUG_TLB
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// # define DEBUG_UNASSIGNED
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/* make various TB consistency checks */
// # define DEBUG_TB_CHECK
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// # define DEBUG_TLB_CHECK
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ths
authored
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// # define DEBUG_IOPORT
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// # define DEBUG_SUBPAGE
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authored
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# if ! defined ( CONFIG_USER_ONLY )
/* TB consistency checks only implemented for usermode emulation. */
# undef DEBUG_TB_CHECK
# endif
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/* threshold to flush the translated code buffer */
# define CODE_GEN_BUFFER_MAX_SIZE ( CODE_GEN_BUFFER_SIZE - CODE_GEN_MAX_SIZE )
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# define SMC_BITMAP_USE_THRESHOLD 10
# define MMAP_AREA_START 0x00000000
# define MMAP_AREA_END 0xa8000000
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# if defined ( TARGET_SPARC64 )
# define TARGET_PHYS_ADDR_SPACE_BITS 41
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# elif defined ( TARGET_SPARC )
# define TARGET_PHYS_ADDR_SPACE_BITS 36
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# elif defined ( TARGET_ALPHA )
# define TARGET_PHYS_ADDR_SPACE_BITS 42
# define TARGET_VIRT_ADDR_SPACE_BITS 42
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# elif defined ( TARGET_PPC64 )
# define TARGET_PHYS_ADDR_SPACE_BITS 42
# else
/* Note: for compatibility with kqemu, we use 32 bits for x86_64 */
# define TARGET_PHYS_ADDR_SPACE_BITS 32
# endif
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TranslationBlock tbs [ CODE_GEN_MAX_BLOCKS ];
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TranslationBlock * tb_phys_hash [ CODE_GEN_PHYS_HASH_SIZE ];
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int nb_tbs ;
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/* any access to the tbs or the page table must use this lock */
spinlock_t tb_lock = SPIN_LOCK_UNLOCKED ;
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uint8_t code_gen_buffer [ CODE_GEN_BUFFER_SIZE ] __attribute__ (( aligned ( 32 )));
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uint8_t * code_gen_ptr ;
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int phys_ram_size ;
int phys_ram_fd ;
uint8_t * phys_ram_base ;
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uint8_t * phys_ram_dirty ;
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static ram_addr_t phys_ram_alloc_offset = 0 ;
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CPUState * first_cpu ;
/* current CPU in the current thread . It is only valid inside
cpu_exec () */
CPUState * cpu_single_env ;
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typedef struct PageDesc {
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/* list of TBs intersecting this ram page */
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TranslationBlock * first_tb ;
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/* in order to optimize self modifying code , we count the number
of lookups we do to a given page to use a bitmap */
unsigned int code_write_count ;
uint8_t * code_bitmap ;
# if defined ( CONFIG_USER_ONLY )
unsigned long flags ;
# endif
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} PageDesc ;
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typedef struct PhysPageDesc {
/* offset in host memory of the page + io_index in the low 12 bits */
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uint32_t phys_offset ;
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} PhysPageDesc ;
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# define L2_BITS 10
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# if defined ( CONFIG_USER_ONLY ) && defined ( TARGET_VIRT_ADDR_SPACE_BITS )
/* XXX : this is a temporary hack for alpha target .
* In the future , this is to be replaced by a multi - level table
* to actually be able to handle the complete 64 bits address space .
*/
# define L1_BITS ( TARGET_VIRT_ADDR_SPACE_BITS - L2_BITS - TARGET_PAGE_BITS )
# else
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# define L1_BITS ( 32 - L2_BITS - TARGET_PAGE_BITS )
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# endif
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# define L1_SIZE ( 1 << L1_BITS )
# define L2_SIZE ( 1 << L2_BITS )
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static void io_mem_init ( void );
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unsigned long qemu_real_host_page_size ;
unsigned long qemu_host_page_bits ;
unsigned long qemu_host_page_size ;
unsigned long qemu_host_page_mask ;
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/* XXX: for system emulation, it could just be an array */
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static PageDesc * l1_map [ L1_SIZE ];
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PhysPageDesc ** l1_phys_map ;
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/* io memory support */
CPUWriteMemoryFunc * io_mem_write [ IO_MEM_NB_ENTRIES ][ 4 ];
CPUReadMemoryFunc * io_mem_read [ IO_MEM_NB_ENTRIES ][ 4 ];
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void * io_mem_opaque [ IO_MEM_NB_ENTRIES ];
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static int io_mem_nb ;
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# if defined ( CONFIG_SOFTMMU )
static int io_mem_watch ;
# endif
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/* log support */
char * logfilename = "/tmp/qemu.log" ;
FILE * logfile ;
int loglevel ;
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/* statistics */
static int tlb_flush_count ;
static int tb_flush_count ;
static int tb_phys_invalidate_count ;
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# define SUBPAGE_IDX ( addr ) (( addr ) & ~ TARGET_PAGE_MASK )
typedef struct subpage_t {
target_phys_addr_t base ;
CPUReadMemoryFunc ** mem_read [ TARGET_PAGE_SIZE ];
CPUWriteMemoryFunc ** mem_write [ TARGET_PAGE_SIZE ];
void * opaque [ TARGET_PAGE_SIZE ];
} subpage_t ;
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static void page_init ( void )
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{
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/* NOTE : we can always suppose that qemu_host_page_size >=
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TARGET_PAGE_SIZE */
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# ifdef _WIN32
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{
SYSTEM_INFO system_info ;
DWORD old_protect ;
GetSystemInfo ( & system_info );
qemu_real_host_page_size = system_info . dwPageSize ;
VirtualProtect ( code_gen_buffer , sizeof ( code_gen_buffer ),
PAGE_EXECUTE_READWRITE , & old_protect );
}
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# else
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qemu_real_host_page_size = getpagesize ();
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{
unsigned long start , end ;
start = ( unsigned long ) code_gen_buffer ;
start &= ~ ( qemu_real_host_page_size - 1 );
end = ( unsigned long ) code_gen_buffer + sizeof ( code_gen_buffer );
end += qemu_real_host_page_size - 1 ;
end &= ~ ( qemu_real_host_page_size - 1 );
mprotect (( void * ) start , end - start ,
PROT_READ | PROT_WRITE | PROT_EXEC );
}
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# endif
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if ( qemu_host_page_size == 0 )
qemu_host_page_size = qemu_real_host_page_size ;
if ( qemu_host_page_size < TARGET_PAGE_SIZE )
qemu_host_page_size = TARGET_PAGE_SIZE ;
qemu_host_page_bits = 0 ;
while (( 1 << qemu_host_page_bits ) < qemu_host_page_size )
qemu_host_page_bits ++ ;
qemu_host_page_mask = ~ ( qemu_host_page_size - 1 );
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l1_phys_map = qemu_vmalloc ( L1_SIZE * sizeof ( void * ));
memset ( l1_phys_map , 0 , L1_SIZE * sizeof ( void * ));
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}
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static inline PageDesc * page_find_alloc ( unsigned int index )
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{
PageDesc ** lp , * p ;
lp = & l1_map [ index >> L2_BITS ];
p = * lp ;
if ( ! p ) {
/* allocate if not found */
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p = qemu_malloc ( sizeof ( PageDesc ) * L2_SIZE );
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memset ( p , 0 , sizeof ( PageDesc ) * L2_SIZE );
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* lp = p ;
}
return p + ( index & ( L2_SIZE - 1 ));
}
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static inline PageDesc * page_find ( unsigned int index )
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{
PageDesc * p ;
p = l1_map [ index >> L2_BITS ];
if ( ! p )
return 0 ;
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return p + ( index & ( L2_SIZE - 1 ));
}
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static PhysPageDesc * phys_page_find_alloc ( target_phys_addr_t index , int alloc )
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{
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void ** lp , ** p ;
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PhysPageDesc * pd ;
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p = ( void ** ) l1_phys_map ;
# if TARGET_PHYS_ADDR_SPACE_BITS > 32
# if TARGET_PHYS_ADDR_SPACE_BITS > ( 32 + L1_BITS )
# error unsupported TARGET_PHYS_ADDR_SPACE_BITS
# endif
lp = p + (( index >> ( L1_BITS + L2_BITS )) & ( L1_SIZE - 1 ));
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p = * lp ;
if ( ! p ) {
/* allocate if not found */
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if ( ! alloc )
return NULL ;
p = qemu_vmalloc ( sizeof ( void * ) * L1_SIZE );
memset ( p , 0 , sizeof ( void * ) * L1_SIZE );
* lp = p ;
}
# endif
lp = p + (( index >> L2_BITS ) & ( L1_SIZE - 1 ));
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pd = * lp ;
if ( ! pd ) {
int i ;
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/* allocate if not found */
if ( ! alloc )
return NULL ;
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pd = qemu_vmalloc ( sizeof ( PhysPageDesc ) * L2_SIZE );
* lp = pd ;
for ( i = 0 ; i < L2_SIZE ; i ++ )
pd [ i ]. phys_offset = IO_MEM_UNASSIGNED ;
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}
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return (( PhysPageDesc * ) pd ) + ( index & ( L2_SIZE - 1 ));
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}
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static inline PhysPageDesc * phys_page_find ( target_phys_addr_t index )
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{
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return phys_page_find_alloc ( index , 0 );
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}
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# if ! defined ( CONFIG_USER_ONLY )
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static void tlb_protect_code ( ram_addr_t ram_addr );
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static void tlb_unprotect_code_phys ( CPUState * env , ram_addr_t ram_addr ,
target_ulong vaddr );
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# endif
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void cpu_exec_init ( CPUState * env )
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{
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CPUState ** penv ;
int cpu_index ;
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if ( ! code_gen_ptr ) {
code_gen_ptr = code_gen_buffer ;
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page_init ();
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io_mem_init ();
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}
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env -> next_cpu = NULL ;
penv = & first_cpu ;
cpu_index = 0 ;
while ( * penv != NULL ) {
penv = ( CPUState ** ) & ( * penv ) -> next_cpu ;
cpu_index ++ ;
}
env -> cpu_index = cpu_index ;
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env -> nb_watchpoints = 0 ;
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* penv = env ;
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}
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static inline void invalidate_page_bitmap ( PageDesc * p )
{
if ( p -> code_bitmap ) {
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qemu_free ( p -> code_bitmap );
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p -> code_bitmap = NULL ;
}
p -> code_write_count = 0 ;
}
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/* set to NULL all the 'first_tb' fields in all PageDescs */
static void page_flush_tb ( void )
{
int i , j ;
PageDesc * p ;
for ( i = 0 ; i < L1_SIZE ; i ++ ) {
p = l1_map [ i ];
if ( p ) {
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for ( j = 0 ; j < L2_SIZE ; j ++ ) {
p -> first_tb = NULL ;
invalidate_page_bitmap ( p );
p ++ ;
}
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}
}
}
/* flush all the translation blocks */
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/* XXX: tb_flush is currently not thread safe */
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void tb_flush ( CPUState * env1 )
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{
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CPUState * env ;
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# if defined ( DEBUG_FLUSH )
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printf ( "qemu: flush code_size=%d nb_tbs=%d avg_tb_size=%d \n " ,
code_gen_ptr - code_gen_buffer ,
nb_tbs ,
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nb_tbs > 0 ? ( code_gen_ptr - code_gen_buffer ) / nb_tbs : 0 );
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# endif
nb_tbs = 0 ;
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for ( env = first_cpu ; env != NULL ; env = env -> next_cpu ) {
memset ( env -> tb_jmp_cache , 0 , TB_JMP_CACHE_SIZE * sizeof ( void * ));
}
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memset ( tb_phys_hash , 0 , CODE_GEN_PHYS_HASH_SIZE * sizeof ( void * ));
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page_flush_tb ();
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code_gen_ptr = code_gen_buffer ;
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/* XXX : flush processor icache at this point if cache flush is
expensive */
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tb_flush_count ++ ;
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}
# ifdef DEBUG_TB_CHECK
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static void tb_invalidate_check ( target_ulong address )
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{
TranslationBlock * tb ;
int i ;
address &= TARGET_PAGE_MASK ;
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for ( i = 0 ; i < CODE_GEN_PHYS_HASH_SIZE ; i ++ ) {
for ( tb = tb_phys_hash [ i ]; tb != NULL ; tb = tb -> phys_hash_next ) {
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if ( ! ( address + TARGET_PAGE_SIZE <= tb -> pc ||
address >= tb -> pc + tb -> size )) {
printf ( "ERROR invalidate: address=%08lx PC=%08lx size=%04x \n " ,
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address , ( long ) tb -> pc , tb -> size );
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}
}
}
}
/* verify that all the pages have correct rights for code */
static void tb_page_check ( void )
{
TranslationBlock * tb ;
int i , flags1 , flags2 ;
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for ( i = 0 ; i < CODE_GEN_PHYS_HASH_SIZE ; i ++ ) {
for ( tb = tb_phys_hash [ i ]; tb != NULL ; tb = tb -> phys_hash_next ) {
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flags1 = page_get_flags ( tb -> pc );
flags2 = page_get_flags ( tb -> pc + tb -> size - 1 );
if (( flags1 & PAGE_WRITE ) || ( flags2 & PAGE_WRITE )) {
printf ( "ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x \n " ,
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( long ) tb -> pc , tb -> size , flags1 , flags2 );
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}
}
}
}
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void tb_jmp_check ( TranslationBlock * tb )
{
TranslationBlock * tb1 ;
unsigned int n1 ;
/* suppress any remaining jumps to this TB */
tb1 = tb -> jmp_first ;
for (;;) {
n1 = ( long ) tb1 & 3 ;
tb1 = ( TranslationBlock * )(( long ) tb1 & ~ 3 );
if ( n1 == 2 )
break ;
tb1 = tb1 -> jmp_next [ n1 ];
}
/* check end of list */
if ( tb1 != tb ) {
printf ( "ERROR: jmp_list from 0x%08lx \n " , ( long ) tb );
}
}
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# endif
/* invalidate one TB */
static inline void tb_remove ( TranslationBlock ** ptb , TranslationBlock * tb ,
int next_offset )
{
TranslationBlock * tb1 ;
for (;;) {
tb1 = * ptb ;
if ( tb1 == tb ) {
* ptb = * ( TranslationBlock ** )(( char * ) tb1 + next_offset );
break ;
}
ptb = ( TranslationBlock ** )(( char * ) tb1 + next_offset );
}
}
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static inline void tb_page_remove ( TranslationBlock ** ptb , TranslationBlock * tb )
{
TranslationBlock * tb1 ;
unsigned int n1 ;
for (;;) {
tb1 = * ptb ;
n1 = ( long ) tb1 & 3 ;
tb1 = ( TranslationBlock * )(( long ) tb1 & ~ 3 );
if ( tb1 == tb ) {
* ptb = tb1 -> page_next [ n1 ];
break ;
}
ptb = & tb1 -> page_next [ n1 ];
}
}
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static inline void tb_jmp_remove ( TranslationBlock * tb , int n )
{
TranslationBlock * tb1 , ** ptb ;
unsigned int n1 ;
ptb = & tb -> jmp_next [ n ];
tb1 = * ptb ;
if ( tb1 ) {
/* find tb(n) in circular list */
for (;;) {
tb1 = * ptb ;
n1 = ( long ) tb1 & 3 ;
tb1 = ( TranslationBlock * )(( long ) tb1 & ~ 3 );
if ( n1 == n && tb1 == tb )
break ;
if ( n1 == 2 ) {
ptb = & tb1 -> jmp_first ;
} else {
ptb = & tb1 -> jmp_next [ n1 ];
}
}
/* now we can suppress tb(n) from the list */
* ptb = tb -> jmp_next [ n ];
tb -> jmp_next [ n ] = NULL ;
}
}
/* reset the jump entry 'n' of a TB so that it is not chained to
another TB */
static inline void tb_reset_jump ( TranslationBlock * tb , int n )
{
tb_set_jmp_target ( tb , n , ( unsigned long )( tb -> tc_ptr + tb -> tb_next_offset [ n ]));
}
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static inline void tb_phys_invalidate ( TranslationBlock * tb , unsigned int page_addr )
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{
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CPUState * env ;
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PageDesc * p ;
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unsigned int h , n1 ;
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target_ulong phys_pc ;
TranslationBlock * tb1 , * tb2 ;
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/* remove the TB from the hash list */
phys_pc = tb -> page_addr [ 0 ] + ( tb -> pc & ~ TARGET_PAGE_MASK );
h = tb_phys_hash_func ( phys_pc );
tb_remove ( & tb_phys_hash [ h ], tb ,
offsetof ( TranslationBlock , phys_hash_next ));
/* remove the TB from the page list */
if ( tb -> page_addr [ 0 ] != page_addr ) {
p = page_find ( tb -> page_addr [ 0 ] >> TARGET_PAGE_BITS );
tb_page_remove ( & p -> first_tb , tb );
invalidate_page_bitmap ( p );
}
if ( tb -> page_addr [ 1 ] != - 1 && tb -> page_addr [ 1 ] != page_addr ) {
p = page_find ( tb -> page_addr [ 1 ] >> TARGET_PAGE_BITS );
tb_page_remove ( & p -> first_tb , tb );
invalidate_page_bitmap ( p );
}
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tb_invalidated_flag = 1 ;
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/* remove the TB from the hash list */
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h = tb_jmp_cache_hash_func ( tb -> pc );
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for ( env = first_cpu ; env != NULL ; env = env -> next_cpu ) {
if ( env -> tb_jmp_cache [ h ] == tb )
env -> tb_jmp_cache [ h ] = NULL ;
}
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/* suppress this TB from the two jump lists */
tb_jmp_remove ( tb , 0 );
tb_jmp_remove ( tb , 1 );
/* suppress any remaining jumps to this TB */
tb1 = tb -> jmp_first ;
for (;;) {
n1 = ( long ) tb1 & 3 ;
if ( n1 == 2 )
break ;
tb1 = ( TranslationBlock * )(( long ) tb1 & ~ 3 );
tb2 = tb1 -> jmp_next [ n1 ];
tb_reset_jump ( tb1 , n1 );
tb1 -> jmp_next [ n1 ] = NULL ;
tb1 = tb2 ;
}
tb -> jmp_first = ( TranslationBlock * )(( long ) tb | 2 ); /* fail safe */
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tb_phys_invalidate_count ++ ;
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}
static inline void set_bits ( uint8_t * tab , int start , int len )
{
int end , mask , end1 ;
end = start + len ;
tab += start >> 3 ;
mask = 0xff << ( start & 7 );
if (( start & ~ 7 ) == ( end & ~ 7 )) {
if ( start < end ) {
mask &= ~ ( 0xff << ( end & 7 ));
* tab |= mask ;
}
} else {
* tab ++ |= mask ;
start = ( start + 8 ) & ~ 7 ;
end1 = end & ~ 7 ;
while ( start < end1 ) {
* tab ++ = 0xff ;
start += 8 ;
}
if ( start < end ) {
mask = ~ ( 0xff << ( end & 7 ));
* tab |= mask ;
}
}
}
static void build_page_bitmap ( PageDesc * p )
{
int n , tb_start , tb_end ;
TranslationBlock * tb ;
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p -> code_bitmap = qemu_malloc ( TARGET_PAGE_SIZE / 8 );
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if ( ! p -> code_bitmap )
return ;
memset ( p -> code_bitmap , 0 , TARGET_PAGE_SIZE / 8 );
tb = p -> first_tb ;
while ( tb != NULL ) {
n = ( long ) tb & 3 ;
tb = ( TranslationBlock * )(( long ) tb & ~ 3 );
/* NOTE: this is subtle as a TB may span two physical pages */
if ( n == 0 ) {
/* NOTE : tb_end may be after the end of the page , but
it is not a problem */
tb_start = tb -> pc & ~ TARGET_PAGE_MASK ;
tb_end = tb_start + tb -> size ;
if ( tb_end > TARGET_PAGE_SIZE )
tb_end = TARGET_PAGE_SIZE ;
} else {
tb_start = 0 ;
tb_end = (( tb -> pc + tb -> size ) & ~ TARGET_PAGE_MASK );
}
set_bits ( p -> code_bitmap , tb_start , tb_end - tb_start );
tb = tb -> page_next [ n ];
}
}
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# ifdef TARGET_HAS_PRECISE_SMC
static void tb_gen_code ( CPUState * env ,
target_ulong pc , target_ulong cs_base , int flags ,
int cflags )
{
TranslationBlock * tb ;
uint8_t * tc_ptr ;
target_ulong phys_pc , phys_page2 , virt_page2 ;
int code_gen_size ;
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phys_pc = get_phys_addr_code ( env , pc );
tb = tb_alloc ( pc );
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if ( ! tb ) {
/* flush must be done */
tb_flush ( env );
/* cannot fail at this point */
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tb = tb_alloc ( pc );
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624
625
626
627
}
tc_ptr = code_gen_ptr ;
tb -> tc_ptr = tc_ptr ;
tb -> cs_base = cs_base ;
tb -> flags = flags ;
tb -> cflags = cflags ;
cpu_gen_code ( env , tb , CODE_GEN_MAX_SIZE , & code_gen_size );
code_gen_ptr = ( void * )((( unsigned long ) code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1 ) & ~ ( CODE_GEN_ALIGN - 1 ));
/* check next page if needed */
628
virt_page2 = ( pc + tb -> size - 1 ) & TARGET_PAGE_MASK ;
629
phys_page2 = - 1 ;
630
if (( pc & TARGET_PAGE_MASK ) != virt_page2 ) {
631
632
633
634
635
636
phys_page2 = get_phys_addr_code ( env , virt_page2 );
}
tb_link_phys ( tb , phys_pc , phys_page2 );
}
# endif
637
638
/* invalidate all TBs which intersect with the target physical page
starting in range [ start ; end [. NOTE : start and end must refer to
639
640
641
642
643
644
645
646
the same physical page . ' is_cpu_write_access ' should be true if called
from a real cpu write access : the virtual CPU will exit the current
TB if code is modified inside this TB . */
void tb_invalidate_phys_page_range ( target_ulong start , target_ulong end ,
int is_cpu_write_access )
{
int n , current_tb_modified , current_tb_not_found , current_flags ;
CPUState * env = cpu_single_env ;
647
PageDesc * p ;
648
TranslationBlock * tb , * tb_next , * current_tb , * saved_tb ;
649
target_ulong tb_start , tb_end ;
650
target_ulong current_pc , current_cs_base ;
651
652
653
654
655
p = page_find ( start >> TARGET_PAGE_BITS );
if ( ! p )
return ;
if ( ! p -> code_bitmap &&
656
657
++ p -> code_write_count >= SMC_BITMAP_USE_THRESHOLD &&
is_cpu_write_access ) {
658
659
660
661
662
663
/* build code bitmap */
build_page_bitmap ( p );
}
/* we remove all the TBs in the range [start, end[ */
/* XXX: see if in some cases it could be faster to invalidate all the code */
664
665
666
667
668
669
current_tb_not_found = is_cpu_write_access ;
current_tb_modified = 0 ;
current_tb = NULL ; /* avoid warning */
current_pc = 0 ; /* avoid warning */
current_cs_base = 0 ; /* avoid warning */
current_flags = 0 ; /* avoid warning */
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
tb = p -> first_tb ;
while ( tb != NULL ) {
n = ( long ) tb & 3 ;
tb = ( TranslationBlock * )(( long ) tb & ~ 3 );
tb_next = tb -> page_next [ n ];
/* NOTE: this is subtle as a TB may span two physical pages */
if ( n == 0 ) {
/* NOTE : tb_end may be after the end of the page , but
it is not a problem */
tb_start = tb -> page_addr [ 0 ] + ( tb -> pc & ~ TARGET_PAGE_MASK );
tb_end = tb_start + tb -> size ;
} else {
tb_start = tb -> page_addr [ 1 ];
tb_end = tb_start + (( tb -> pc + tb -> size ) & ~ TARGET_PAGE_MASK );
}
if ( ! ( tb_end <= start || tb_start >= end )) {
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
# ifdef TARGET_HAS_PRECISE_SMC
if ( current_tb_not_found ) {
current_tb_not_found = 0 ;
current_tb = NULL ;
if ( env -> mem_write_pc ) {
/* now we have a real cpu fault */
current_tb = tb_find_pc ( env -> mem_write_pc );
}
}
if ( current_tb == tb &&
! ( current_tb -> cflags & CF_SINGLE_INSN )) {
/* If we are modifying the current TB , we must stop
its execution . We could be more precise by checking
that the modification is after the current PC , but it
would require a specialized function to partially
restore the CPU state */
current_tb_modified = 1 ;
cpu_restore_state ( current_tb , env ,
env -> mem_write_pc , NULL );
# if defined ( TARGET_I386 )
current_flags = env -> hflags ;
current_flags |= ( env -> eflags & ( IOPL_MASK | TF_MASK | VM_MASK ));
current_cs_base = ( target_ulong ) env -> segs [ R_CS ]. base ;
current_pc = current_cs_base + env -> eip ;
# else
# error unsupported CPU
# endif
}
# endif /* TARGET_HAS_PRECISE_SMC */
716
717
718
719
720
721
722
/* we need to do that to handle the case where a signal
occurs while doing tb_phys_invalidate () */
saved_tb = NULL ;
if ( env ) {
saved_tb = env -> current_tb ;
env -> current_tb = NULL ;
}
723
tb_phys_invalidate ( tb , - 1 ) ;
724
725
726
727
728
if ( env ) {
env -> current_tb = saved_tb ;
if ( env -> interrupt_request && env -> current_tb )
cpu_interrupt ( env , env -> interrupt_request ) ;
}
729
730
731
732
733
734
735
}
tb = tb_next ;
}
# if ! defined ( CONFIG_USER_ONLY )
/* if no code remaining, no need to continue to use slow writes */
if ( ! p -> first_tb ) {
invalidate_page_bitmap ( p ) ;
736
737
738
739
740
741
742
743
744
745
if ( is_cpu_write_access ) {
tlb_unprotect_code_phys ( env , start , env -> mem_write_vaddr ) ;
}
}
# endif
# ifdef TARGET_HAS_PRECISE_SMC
if ( current_tb_modified ) {
/* we generate a block containing just the instruction
modifying the memory . It will ensure that it cannot modify
itself */
746
env -> current_tb = NULL ;
747
748
749
tb_gen_code ( env , current_pc , current_cs_base , current_flags ,
CF_SINGLE_INSN ) ;
cpu_resume_from_signal ( env , NULL ) ;
750
}
751
# endif
752
}
753
754
/* len must be <= 8 and start must be a multiple of len */
755
static inline void tb_invalidate_phys_page_fast ( target_ulong start , int len )
756
757
758
{
PageDesc * p ;
int offset , b ;
759
# if 0
760
761
762
763
764
765
766
if ( 1 ) {
if ( loglevel ) {
fprintf ( logfile , "modifying code at 0x%x size=%d EIP=%x PC=%08x \n " ,
cpu_single_env -> mem_write_vaddr , len ,
cpu_single_env -> eip ,
cpu_single_env -> eip + ( long ) cpu_single_env -> segs [ R_CS ]. base ) ;
}
767
768
}
# endif
769
770
771
772
773
774
775
776
777
778
p = page_find ( start >> TARGET_PAGE_BITS ) ;
if ( ! p )
return ;
if ( p -> code_bitmap ) {
offset = start & ~ TARGET_PAGE_MASK ;
b = p -> code_bitmap [ offset >> 3 ] >> ( offset & 7 ) ;
if ( b & (( 1 << len ) - 1 ))
goto do_invalidate ;
} else {
do_invalidate :
779
tb_invalidate_phys_page_range ( start , start + len , 1 );
780
781
782
783
}
}
# if ! defined ( CONFIG_SOFTMMU )
784
785
static void tb_invalidate_phys_page ( target_ulong addr ,
unsigned long pc , void * puc )
786
{
787
788
int n , current_flags , current_tb_modified ;
target_ulong current_pc , current_cs_base ;
789
PageDesc * p ;
790
791
792
793
TranslationBlock * tb , * current_tb ;
# ifdef TARGET_HAS_PRECISE_SMC
CPUState * env = cpu_single_env ;
# endif
794
795
796
797
798
799
addr &= TARGET_PAGE_MASK ;
p = page_find ( addr >> TARGET_PAGE_BITS );
if ( ! p )
return ;
tb = p -> first_tb ;
800
801
802
803
804
805
806
807
808
809
current_tb_modified = 0 ;
current_tb = NULL ;
current_pc = 0 ; /* avoid warning */
current_cs_base = 0 ; /* avoid warning */
current_flags = 0 ; /* avoid warning */
# ifdef TARGET_HAS_PRECISE_SMC
if ( tb && pc != 0 ) {
current_tb = tb_find_pc ( pc );
}
# endif
810
811
812
while ( tb != NULL ) {
n = ( long ) tb & 3 ;
tb = ( TranslationBlock * )(( long ) tb & ~ 3 );
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
# ifdef TARGET_HAS_PRECISE_SMC
if ( current_tb == tb &&
! ( current_tb -> cflags & CF_SINGLE_INSN )) {
/* If we are modifying the current TB , we must stop
its execution . We could be more precise by checking
that the modification is after the current PC , but it
would require a specialized function to partially
restore the CPU state */
current_tb_modified = 1 ;
cpu_restore_state ( current_tb , env , pc , puc );
# if defined ( TARGET_I386 )
current_flags = env -> hflags ;
current_flags |= ( env -> eflags & ( IOPL_MASK | TF_MASK | VM_MASK ));
current_cs_base = ( target_ulong ) env -> segs [ R_CS ]. base ;
current_pc = current_cs_base + env -> eip ;
# else
# error unsupported CPU
# endif
}
# endif /* TARGET_HAS_PRECISE_SMC */
834
835
836
tb_phys_invalidate ( tb , addr );
tb = tb -> page_next [ n ];
}
837
p -> first_tb = NULL ;
838
839
840
841
842
# ifdef TARGET_HAS_PRECISE_SMC
if ( current_tb_modified ) {
/* we generate a block containing just the instruction
modifying the memory . It will ensure that it cannot modify
itself */
843
env -> current_tb = NULL ;
844
845
846
847
848
tb_gen_code ( env , current_pc , current_cs_base , current_flags ,
CF_SINGLE_INSN );
cpu_resume_from_signal ( env , puc );
}
# endif
849
}
850
# endif
851
852
/* add the tb in the target page and protect it if necessary */
853
static inline void tb_alloc_page ( TranslationBlock * tb ,
854
unsigned int n , target_ulong page_addr )
855
856
{
PageDesc * p ;
857
858
859
TranslationBlock * last_first_tb ;
tb -> page_addr [ n ] = page_addr ;
860
p = page_find_alloc ( page_addr >> TARGET_PAGE_BITS );
861
862
863
864
tb -> page_next [ n ] = p -> first_tb ;
last_first_tb = p -> first_tb ;
p -> first_tb = ( TranslationBlock * )(( long ) tb | n );
invalidate_page_bitmap ( p );
865
866
# if defined ( TARGET_HAS_SMC ) || 1
867
868
# if defined ( CONFIG_USER_ONLY )
869
if ( p -> flags & PAGE_WRITE ) {
870
871
target_ulong addr ;
PageDesc * p2 ;
872
873
int prot ;
874
875
/* force the host page as non writable ( writes will have a
page fault + mprotect overhead ) */
876
page_addr &= qemu_host_page_mask ;
877
prot = 0 ;
878
879
880
881
882
883
884
885
886
887
888
for ( addr = page_addr ; addr < page_addr + qemu_host_page_size ;
addr += TARGET_PAGE_SIZE ) {
p2 = page_find ( addr >> TARGET_PAGE_BITS );
if ( ! p2 )
continue ;
prot |= p2 -> flags ;
p2 -> flags &= ~ PAGE_WRITE ;
page_get_flags ( addr );
}
mprotect ( g2h ( page_addr ), qemu_host_page_size ,
889
890
891
( prot & PAGE_BITS ) & ~ PAGE_WRITE );
# ifdef DEBUG_TB_INVALIDATE
printf ( "protecting code page: 0x%08lx \n " ,
892
page_addr );
893
894
# endif
}
895
896
897
898
899
# else
/* if some code is already present , then the pages are already
protected . So we handle the case where only the first TB is
allocated in a physical page */
if ( ! last_first_tb ) {
900
tlb_protect_code ( page_addr ) ;
901
902
}
# endif
903
904
# endif /* TARGET_HAS_SMC */
905
906
907
908
}
/* Allocate a new translation block . Flush the translation buffer if
too many translation blocks or too much generated code . */
909
TranslationBlock * tb_alloc ( target_ulong pc )
910
911
912
913
914
{
TranslationBlock * tb ;
if ( nb_tbs >= CODE_GEN_MAX_BLOCKS ||
( code_gen_ptr - code_gen_buffer ) >= CODE_GEN_BUFFER_MAX_SIZE )
915
return NULL ;
916
917
tb = & tbs [ nb_tbs ++ ] ;
tb -> pc = pc ;
918
tb -> cflags = 0 ;
919
920
921
return tb ;
}
922
923
924
925
/* add a new TB and link it to the physical page tables . phys_page2 is
( - 1 ) to indicate that only one page contains the TB . */
void tb_link_phys ( TranslationBlock * tb ,
target_ulong phys_pc , target_ulong phys_page2 )
926
{
927
928
929
930
931
932
933
934
unsigned int h ;
TranslationBlock ** ptb ;
/* add in the physical hash table */
h = tb_phys_hash_func ( phys_pc ) ;
ptb = & tb_phys_hash [ h ] ;
tb -> phys_hash_next = * ptb ;
* ptb = tb ;
935
936
/* add in the page list */
937
938
939
940
941
942
tb_alloc_page ( tb , 0 , phys_pc & TARGET_PAGE_MASK ) ;
if ( phys_page2 != - 1 )
tb_alloc_page ( tb , 1 , phys_page2 ) ;
else
tb -> page_addr [ 1 ] = - 1 ;
943
944
945
tb -> jmp_first = ( TranslationBlock * )(( long ) tb | 2 ) ;
tb -> jmp_next [ 0 ] = NULL ;
tb -> jmp_next [ 1 ] = NULL ;
946
947
948
949
950
# ifdef USE_CODE_COPY
tb -> cflags &= ~ CF_FP_USED ;
if ( tb -> cflags & CF_TB_FP_USED )
tb -> cflags |= CF_FP_USED ;
# endif
951
952
953
954
955
956
/* init original jump addresses */
if ( tb -> tb_next_offset [ 0 ] != 0xffff )
tb_reset_jump ( tb , 0 ) ;
if ( tb -> tb_next_offset [ 1 ] != 0xffff )
tb_reset_jump ( tb , 1 ) ;
957
958
959
960
# ifdef DEBUG_TB_CHECK
tb_page_check () ;
# endif
961
962
}
963
964
965
/* find the TB ' tb ' such that tb [ 0 ]. tc_ptr <= tc_ptr <
tb [ 1 ]. tc_ptr . Return NULL if not found */
TranslationBlock * tb_find_pc ( unsigned long tc_ptr )
966
{
967
968
969
int m_min , m_max , m ;
unsigned long v ;
TranslationBlock * tb ;
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
if ( nb_tbs <= 0 )
return NULL ;
if ( tc_ptr < ( unsigned long ) code_gen_buffer ||
tc_ptr >= ( unsigned long ) code_gen_ptr )
return NULL ;
/* binary search (cf Knuth) */
m_min = 0 ;
m_max = nb_tbs - 1 ;
while ( m_min <= m_max ) {
m = ( m_min + m_max ) >> 1 ;
tb = & tbs [ m ] ;
v = ( unsigned long ) tb -> tc_ptr ;
if ( v == tc_ptr )
return tb ;
else if ( tc_ptr < v ) {
m_max = m - 1 ;
} else {
m_min = m + 1 ;
}
}
return & tbs [ m_max ] ;
}
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
static void tb_reset_jump_recursive ( TranslationBlock * tb ) ;
static inline void tb_reset_jump_recursive2 ( TranslationBlock * tb , int n )
{
TranslationBlock * tb1 , * tb_next , ** ptb ;
unsigned int n1 ;
tb1 = tb -> jmp_next [ n ] ;
if ( tb1 != NULL ) {
/* find head of list */
for ( ;; ) {
n1 = ( long ) tb1 & 3 ;
tb1 = ( TranslationBlock * )(( long ) tb1 & ~ 3 ) ;
if ( n1 == 2 )
break ;
tb1 = tb1 -> jmp_next [ n1 ] ;
}
/* we are now sure now that tb jumps to tb1 */
tb_next = tb1 ;
/* remove tb from the jmp_first list */
ptb = & tb_next -> jmp_first ;
for ( ;; ) {
tb1 = * ptb ;
n1 = ( long ) tb1 & 3 ;
tb1 = ( TranslationBlock * )(( long ) tb1 & ~ 3 ) ;
if ( n1 == n && tb1 == tb )
break ;
ptb = & tb1 -> jmp_next [ n1 ] ;
}
* ptb = tb -> jmp_next [ n ] ;
tb -> jmp_next [ n ] = NULL ;
/* suppress the jump to next tb in generated code */
tb_reset_jump ( tb , n ) ;
1030
/* suppress jumps in the tb on which we could have jumped */
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
tb_reset_jump_recursive ( tb_next ) ;
}
}
static void tb_reset_jump_recursive ( TranslationBlock * tb )
{
tb_reset_jump_recursive2 ( tb , 0 ) ;
tb_reset_jump_recursive2 ( tb , 1 ) ;
}
1041
# if defined ( TARGET_HAS_ICE )
1042
1043
static void breakpoint_invalidate ( CPUState * env , target_ulong pc )
{
1044
1045
target_phys_addr_t addr ;
target_ulong pd ;
1046
1047
ram_addr_t ram_addr ;
PhysPageDesc * p ;
1048
1049
1050
1051
1052
1053
1054
1055
1056
addr = cpu_get_phys_page_debug ( env , pc ) ;
p = phys_page_find ( addr >> TARGET_PAGE_BITS ) ;
if ( ! p ) {
pd = IO_MEM_UNASSIGNED ;
} else {
pd = p -> phys_offset ;
}
ram_addr = ( pd & TARGET_PAGE_MASK ) | ( pc & ~ TARGET_PAGE_MASK ) ;
1057
tb_invalidate_phys_page_range ( ram_addr , ram_addr + 1 , 0 ) ;
1058
}
1059
# endif
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
/* Add a watchpoint. */
int cpu_watchpoint_insert ( CPUState * env , target_ulong addr )
{
int i ;
for ( i = 0 ; i < env -> nb_watchpoints ; i ++ ) {
if ( addr == env -> watchpoint [ i ]. vaddr )
return 0 ;
}
if ( env -> nb_watchpoints >= MAX_WATCHPOINTS )
return - 1 ;
i = env -> nb_watchpoints ++ ;
env -> watchpoint [ i ]. vaddr = addr ;
tlb_flush_page ( env , addr ) ;
/* FIXME : This flush is needed because of the hack to make memory ops
terminate the TB . It can be removed once the proper IO trap and
re - execute bits are in . */
tb_flush ( env );
return i ;
}
/* Remove a watchpoint. */
int cpu_watchpoint_remove ( CPUState * env , target_ulong addr )
{
int i ;
for ( i = 0 ; i < env -> nb_watchpoints ; i ++ ) {
if ( addr == env -> watchpoint [ i ]. vaddr ) {
env -> nb_watchpoints -- ;
env -> watchpoint [ i ] = env -> watchpoint [ env -> nb_watchpoints ];
tlb_flush_page ( env , addr );
return 0 ;
}
}
return - 1 ;
}
1099
1100
/* add a breakpoint . EXCP_DEBUG is returned by the CPU loop if a
breakpoint is reached */
1101
int cpu_breakpoint_insert ( CPUState * env , target_ulong pc )
1102
{
1103
# if defined ( TARGET_HAS_ICE )
1104
int i ;
1105
1106
1107
1108
1109
1110
1111
1112
1113
for ( i = 0 ; i < env -> nb_breakpoints ; i ++ ) {
if ( env -> breakpoints [ i ] == pc )
return 0 ;
}
if ( env -> nb_breakpoints >= MAX_BREAKPOINTS )
return - 1 ;
env -> breakpoints [ env -> nb_breakpoints ++ ] = pc ;
1114
1115
breakpoint_invalidate ( env , pc );
1116
1117
1118
1119
1120
1121
1122
return 0 ;
# else
return - 1 ;
# endif
}
/* remove a breakpoint */
1123
int cpu_breakpoint_remove ( CPUState * env , target_ulong pc )
1124
{
1125
# if defined ( TARGET_HAS_ICE )
1126
1127
1128
1129
1130
1131
1132
1133
int i ;
for ( i = 0 ; i < env -> nb_breakpoints ; i ++ ) {
if ( env -> breakpoints [ i ] == pc )
goto found ;
}
return - 1 ;
found :
env -> nb_breakpoints -- ;
1134
1135
if ( i < env -> nb_breakpoints )
env -> breakpoints [ i ] = env -> breakpoints [ env -> nb_breakpoints ];
1136
1137
breakpoint_invalidate ( env , pc );
1138
1139
1140
1141
1142
1143
return 0 ;
# else
return - 1 ;
# endif
}
1144
1145
1146
1147
/* enable or disable single step mode . EXCP_DEBUG is returned by the
CPU loop after each instruction */
void cpu_single_step ( CPUState * env , int enabled )
{
1148
# if defined ( TARGET_HAS_ICE )
1149
1150
1151
if ( env -> singlestep_enabled != enabled ) {
env -> singlestep_enabled = enabled ;
/* must flush all the translated code to avoid inconsistancies */
1152
/* XXX: only flush what is necessary */
1153
tb_flush ( env );
1154
1155
1156
1157
}
# endif
}
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
/* enable or disable low levels log */
void cpu_set_log ( int log_flags )
{
loglevel = log_flags ;
if ( loglevel && ! logfile ) {
logfile = fopen ( logfilename , "w" );
if ( ! logfile ) {
perror ( logfilename );
_exit ( 1 );
}
1168
1169
1170
1171
1172
1173
1174
# if ! defined ( CONFIG_SOFTMMU )
/* must avoid mmap() usage of glibc by setting a buffer "by hand" */
{
static uint8_t logfile_buf [ 4096 ];
setvbuf ( logfile , logfile_buf , _IOLBF , sizeof ( logfile_buf ));
}
# else
1175
setvbuf ( logfile , NULL , _IOLBF , 0 );
1176
# endif
1177
1178
1179
1180
1181
1182
1183
}
}
void cpu_set_log_filename ( const char * filename )
{
logfilename = strdup ( filename );
}
1184
1185
/* mask must never be zero, except for A20 change call */
1186
void cpu_interrupt ( CPUState * env , int mask )
1187
1188
{
TranslationBlock * tb ;
1189
static int interrupt_lock ;
1190
1191
env -> interrupt_request |= mask ;
1192
1193
1194
/* if the cpu is currently executing code , we must unlink it and
all the potentially executing TB */
tb = env -> current_tb ;
1195
1196
if ( tb && ! testandset ( & interrupt_lock )) {
env -> current_tb = NULL ;
1197
tb_reset_jump_recursive ( tb );
1198
interrupt_lock = 0 ;
1199
1200
1201
}
}
1202
1203
1204
1205
1206
void cpu_reset_interrupt ( CPUState * env , int mask )
{
env -> interrupt_request &= ~ mask ;
}
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
CPULogItem cpu_log_items [] = {
{ CPU_LOG_TB_OUT_ASM , "out_asm" ,
"show generated host assembly code for each compiled TB" },
{ CPU_LOG_TB_IN_ASM , "in_asm" ,
"show target assembly code for each compiled TB" },
{ CPU_LOG_TB_OP , "op" ,
"show micro ops for each compiled TB (only usable if 'in_asm' used)" },
# ifdef TARGET_I386
{ CPU_LOG_TB_OP_OPT , "op_opt" ,
"show micro ops after optimization for each compiled TB" },
# endif
{ CPU_LOG_INT , "int" ,
"show interrupts/exceptions in short format" },
{ CPU_LOG_EXEC , "exec" ,
"show trace before each executed TB (lots of logs)" },
1222
1223
{ CPU_LOG_TB_CPU , "cpu" ,
"show CPU state before bloc translation" },
1224
1225
1226
1227
# ifdef TARGET_I386
{ CPU_LOG_PCALL , "pcall" ,
"show protected mode far calls/returns/exceptions" },
# endif
1228
# ifdef DEBUG_IOPORT
1229
1230
{ CPU_LOG_IOPORT , "ioport" ,
"show all i/o ports accesses" },
1231
# endif
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
{ 0 , NULL , NULL },
};
static int cmp1 ( const char * s1 , int n , const char * s2 )
{
if ( strlen ( s2 ) != n )
return 0 ;
return memcmp ( s1 , s2 , n ) == 0 ;
}
/* takes a comma separated list of log masks. Return 0 if error. */
int cpu_str_to_log_mask ( const char * str )
{
CPULogItem * item ;
int mask ;
const char * p , * p1 ;
p = str ;
mask = 0 ;
for (;;) {
p1 = strchr ( p , ',' );
if ( ! p1 )
p1 = p + strlen ( p );
1255
1256
1257
1258
1259
if ( cmp1 ( p , p1 - p , "all" )) {
for ( item = cpu_log_items ; item -> mask != 0 ; item ++ ) {
mask |= item -> mask ;
}
} else {
1260
1261
1262
1263
1264
for ( item = cpu_log_items ; item -> mask != 0 ; item ++ ) {
if ( cmp1 ( p , p1 - p , item -> name ))
goto found ;
}
return 0 ;
1265
}
1266
1267
1268
1269
1270
1271
1272
1273
found :
mask |= item -> mask ;
if ( * p1 != ',' )
break ;
p = p1 + 1 ;
}
return mask ;
}
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
void cpu_abort ( CPUState * env , const char * fmt , ...)
{
va_list ap ;
va_start ( ap , fmt );
fprintf ( stderr , "qemu: fatal: " );
vfprintf ( stderr , fmt , ap );
fprintf ( stderr , " \n " );
# ifdef TARGET_I386
1284
1285
1286
cpu_dump_state ( env , stderr , fprintf , X86_DUMP_FPU | X86_DUMP_CCOP );
# else
cpu_dump_state ( env , stderr , fprintf , 0 );
1287
1288
1289
1290
1291
# endif
va_end ( ap );
abort ();
}
ths
authored
18 years ago
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
CPUState * cpu_copy ( CPUState * env )
{
CPUState * new_env = cpu_init ();
/* preserve chaining and index */
CPUState * next_cpu = new_env -> next_cpu ;
int cpu_index = new_env -> cpu_index ;
memcpy ( new_env , env , sizeof ( CPUState ));
new_env -> next_cpu = next_cpu ;
new_env -> cpu_index = cpu_index ;
return new_env ;
}
1304
1305
# if ! defined ( CONFIG_USER_ONLY )
1306
1307
1308
/* NOTE : if flush_global is true , also flush global entries ( not
implemented yet ) */
void tlb_flush ( CPUState * env , int flush_global )
1309
1310
{
int i ;
1311
1312
1313
1314
# if defined ( DEBUG_TLB )
printf ( "tlb_flush: \n " );
# endif
1315
1316
1317
1318
/* must reset current TB so that interrupts cannot modify the
links while we are modifying them */
env -> current_tb = NULL ;
1319
for ( i = 0 ; i < CPU_TLB_SIZE ; i ++ ) {
1320
1321
1322
1323
1324
1325
env -> tlb_table [ 0 ][ i ]. addr_read = - 1 ;
env -> tlb_table [ 0 ][ i ]. addr_write = - 1 ;
env -> tlb_table [ 0 ][ i ]. addr_code = - 1 ;
env -> tlb_table [ 1 ][ i ]. addr_read = - 1 ;
env -> tlb_table [ 1 ][ i ]. addr_write = - 1 ;
env -> tlb_table [ 1 ][ i ]. addr_code = - 1 ;
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
# if ( NB_MMU_MODES >= 3 )
env -> tlb_table [ 2 ][ i ]. addr_read = - 1 ;
env -> tlb_table [ 2 ][ i ]. addr_write = - 1 ;
env -> tlb_table [ 2 ][ i ]. addr_code = - 1 ;
# if ( NB_MMU_MODES == 4 )
env -> tlb_table [ 3 ][ i ]. addr_read = - 1 ;
env -> tlb_table [ 3 ][ i ]. addr_write = - 1 ;
env -> tlb_table [ 3 ][ i ]. addr_code = - 1 ;
# endif
# endif
1336
}
1337
1338
memset ( env -> tb_jmp_cache , 0 , TB_JMP_CACHE_SIZE * sizeof ( void * ));
1339
1340
1341
1342
# if ! defined ( CONFIG_SOFTMMU )
munmap (( void * ) MMAP_AREA_START , MMAP_AREA_END - MMAP_AREA_START );
# endif
1343
1344
1345
1346
1347
# ifdef USE_KQEMU
if ( env -> kqemu_enabled ) {
kqemu_flush ( env , flush_global );
}
# endif
1348
tlb_flush_count ++ ;
1349
1350
}
1351
static inline void tlb_flush_entry ( CPUTLBEntry * tlb_entry , target_ulong addr )
1352
{
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
if ( addr == ( tlb_entry -> addr_read &
( TARGET_PAGE_MASK | TLB_INVALID_MASK )) ||
addr == ( tlb_entry -> addr_write &
( TARGET_PAGE_MASK | TLB_INVALID_MASK )) ||
addr == ( tlb_entry -> addr_code &
( TARGET_PAGE_MASK | TLB_INVALID_MASK ))) {
tlb_entry -> addr_read = - 1 ;
tlb_entry -> addr_write = - 1 ;
tlb_entry -> addr_code = - 1 ;
}
1363
1364
}
1365
void tlb_flush_page ( CPUState * env , target_ulong addr )
1366
{
1367
int i ;
1368
TranslationBlock * tb ;
1369
1370
# if defined ( DEBUG_TLB )
1371
printf ( "tlb_flush_page: " TARGET_FMT_lx " \n " , addr );
1372
# endif
1373
1374
1375
/* must reset current TB so that interrupts cannot modify the
links while we are modifying them */
env -> current_tb = NULL ;
1376
1377
1378
addr &= TARGET_PAGE_MASK ;
i = ( addr >> TARGET_PAGE_BITS ) & ( CPU_TLB_SIZE - 1 );
1379
1380
tlb_flush_entry ( & env -> tlb_table [ 0 ][ i ], addr );
tlb_flush_entry ( & env -> tlb_table [ 1 ][ i ], addr );
1381
1382
1383
1384
1385
1386
# if ( NB_MMU_MODES >= 3 )
tlb_flush_entry ( & env -> tlb_table [ 2 ][ i ], addr );
# if ( NB_MMU_MODES == 4 )
tlb_flush_entry ( & env -> tlb_table [ 3 ][ i ], addr );
# endif
# endif
1387
1388
1389
1390
1391
1392
1393
1394
/* Discard jump cache entries for any tb which might potentially
overlap the flushed page . */
i = tb_jmp_cache_hash_page ( addr - TARGET_PAGE_SIZE );
memset ( & env -> tb_jmp_cache [ i ], 0 , TB_JMP_PAGE_SIZE * sizeof ( tb ));
i = tb_jmp_cache_hash_page ( addr );
memset ( & env -> tb_jmp_cache [ i ], 0 , TB_JMP_PAGE_SIZE * sizeof ( tb ));
1395
1396
# if ! defined ( CONFIG_SOFTMMU )
1397
if ( addr < MMAP_AREA_END )
1398
munmap (( void * ) addr , TARGET_PAGE_SIZE );
1399
# endif
1400
1401
1402
1403
1404
# ifdef USE_KQEMU
if ( env -> kqemu_enabled ) {
kqemu_flush_page ( env , addr );
}
# endif
1405
1406
1407
1408
}
/* update the TLBs so that writes to code in the virtual page ' addr '
can be detected */
1409
static void tlb_protect_code ( ram_addr_t ram_addr )
1410
{
1411
1412
1413
cpu_physical_memory_reset_dirty ( ram_addr ,
ram_addr + TARGET_PAGE_SIZE ,
CODE_DIRTY_FLAG );
1414
1415
1416
}
/* update the TLB so that writes in physical page ' phys_addr ' are no longer
1417
1418
1419
tested for self modifying code */
static void tlb_unprotect_code_phys ( CPUState * env , ram_addr_t ram_addr ,
target_ulong vaddr )
1420
{
1421
phys_ram_dirty [ ram_addr >> TARGET_PAGE_BITS ] |= CODE_DIRTY_FLAG ;
1422
1423
1424
1425
1426
1427
}
static inline void tlb_reset_dirty_range ( CPUTLBEntry * tlb_entry ,
unsigned long start , unsigned long length )
{
unsigned long addr ;
1428
1429
if (( tlb_entry -> addr_write & ~ TARGET_PAGE_MASK ) == IO_MEM_RAM ) {
addr = ( tlb_entry -> addr_write & TARGET_PAGE_MASK ) + tlb_entry -> addend ;
1430
if (( addr - start ) < length ) {
1431
tlb_entry -> addr_write = ( tlb_entry -> addr_write & TARGET_PAGE_MASK ) | IO_MEM_NOTDIRTY ;
1432
1433
1434
1435
}
}
}
1436
void cpu_physical_memory_reset_dirty ( ram_addr_t start , ram_addr_t end ,
1437
int dirty_flags )
1438
1439
{
CPUState * env ;
1440
unsigned long length , start1 ;
1441
1442
int i , mask , len ;
uint8_t * p ;
1443
1444
1445
1446
1447
1448
1449
start &= TARGET_PAGE_MASK ;
end = TARGET_PAGE_ALIGN ( end );
length = end - start ;
if ( length == 0 )
return ;
1450
len = length >> TARGET_PAGE_BITS ;
1451
# ifdef USE_KQEMU
1452
1453
/* XXX: should not depend on cpu context */
env = first_cpu ;
1454
if ( env -> kqemu_enabled ) {
1455
1456
1457
1458
1459
1460
ram_addr_t addr ;
addr = start ;
for ( i = 0 ; i < len ; i ++ ) {
kqemu_set_notdirty ( env , addr );
addr += TARGET_PAGE_SIZE ;
}
1461
1462
}
# endif
1463
1464
1465
1466
1467
mask = ~ dirty_flags ;
p = phys_ram_dirty + ( start >> TARGET_PAGE_BITS );
for ( i = 0 ; i < len ; i ++ )
p [ i ] &= mask ;
1468
1469
/* we modify the TLB cache so that the dirty bit will be set again
when accessing the range */
1470
start1 = start + ( unsigned long ) phys_ram_base ;
1471
1472
for ( env = first_cpu ; env != NULL ; env = env -> next_cpu ) {
for ( i = 0 ; i < CPU_TLB_SIZE ; i ++ )
1473
tlb_reset_dirty_range ( & env -> tlb_table [ 0 ][ i ], start1 , length );
1474
for ( i = 0 ; i < CPU_TLB_SIZE ; i ++ )
1475
tlb_reset_dirty_range ( & env -> tlb_table [ 1 ][ i ], start1 , length );
1476
1477
1478
1479
1480
1481
1482
1483
# if ( NB_MMU_MODES >= 3 )
for ( i = 0 ; i < CPU_TLB_SIZE ; i ++ )
tlb_reset_dirty_range ( & env -> tlb_table [ 2 ][ i ], start1 , length );
# if ( NB_MMU_MODES == 4 )
for ( i = 0 ; i < CPU_TLB_SIZE ; i ++ )
tlb_reset_dirty_range ( & env -> tlb_table [ 3 ][ i ], start1 , length );
# endif
# endif
1484
}
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
# if ! defined ( CONFIG_SOFTMMU )
/* XXX: this is expensive */
{
VirtPageDesc * p ;
int j ;
target_ulong addr ;
for ( i = 0 ; i < L1_SIZE ; i ++ ) {
p = l1_virt_map [ i ];
if ( p ) {
addr = i << ( TARGET_PAGE_BITS + L2_BITS );
for ( j = 0 ; j < L2_SIZE ; j ++ ) {
if ( p -> valid_tag == virt_valid_tag &&
p -> phys_addr >= start && p -> phys_addr < end &&
( p -> prot & PROT_WRITE )) {
if ( addr < MMAP_AREA_END ) {
mprotect (( void * ) addr , TARGET_PAGE_SIZE ,
p -> prot & ~ PROT_WRITE );
}
}
addr += TARGET_PAGE_SIZE ;
p ++ ;
}
}
}
}
# endif
1513
1514
}
1515
1516
1517
1518
static inline void tlb_update_dirty ( CPUTLBEntry * tlb_entry )
{
ram_addr_t ram_addr ;
1519
1520
if (( tlb_entry -> addr_write & ~ TARGET_PAGE_MASK ) == IO_MEM_RAM ) {
ram_addr = ( tlb_entry -> addr_write & TARGET_PAGE_MASK ) +
1521
1522
tlb_entry -> addend - ( unsigned long ) phys_ram_base ;
if ( ! cpu_physical_memory_is_dirty ( ram_addr )) {
1523
tlb_entry -> addr_write |= IO_MEM_NOTDIRTY ;
1524
1525
1526
1527
1528
1529
1530
1531
1532
}
}
}
/* update the TLB according to the current state of the dirty bits */
void cpu_tlb_update_dirty ( CPUState * env )
{
int i ;
for ( i = 0 ; i < CPU_TLB_SIZE ; i ++ )
1533
tlb_update_dirty ( & env -> tlb_table [ 0 ][ i ]);
1534
for ( i = 0 ; i < CPU_TLB_SIZE ; i ++ )
1535
tlb_update_dirty ( & env -> tlb_table [ 1 ][ i ]);
1536
1537
1538
1539
1540
1541
1542
1543
# if ( NB_MMU_MODES >= 3 )
for ( i = 0 ; i < CPU_TLB_SIZE ; i ++ )
tlb_update_dirty ( & env -> tlb_table [ 2 ][ i ]);
# if ( NB_MMU_MODES == 4 )
for ( i = 0 ; i < CPU_TLB_SIZE ; i ++ )
tlb_update_dirty ( & env -> tlb_table [ 3 ][ i ]);
# endif
# endif
1544
1545
}
1546
static inline void tlb_set_dirty1 ( CPUTLBEntry * tlb_entry ,
1547
unsigned long start )
1548
1549
{
unsigned long addr ;
1550
1551
if (( tlb_entry -> addr_write & ~ TARGET_PAGE_MASK ) == IO_MEM_NOTDIRTY ) {
addr = ( tlb_entry -> addr_write & TARGET_PAGE_MASK ) + tlb_entry -> addend ;
1552
if ( addr == start ) {
1553
tlb_entry -> addr_write = ( tlb_entry -> addr_write & TARGET_PAGE_MASK ) | IO_MEM_RAM ;
1554
1555
1556
1557
1558
1559
}
}
}
/* update the TLB corresponding to virtual page vaddr and phys addr
addr so that it is no longer dirty */
1560
1561
static inline void tlb_set_dirty ( CPUState * env ,
unsigned long addr , target_ulong vaddr )
1562
1563
1564
1565
1566
{
int i ;
addr &= TARGET_PAGE_MASK ;
i = ( vaddr >> TARGET_PAGE_BITS ) & ( CPU_TLB_SIZE - 1 );
1567
1568
tlb_set_dirty1 ( & env -> tlb_table [ 0 ][ i ], addr );
tlb_set_dirty1 ( & env -> tlb_table [ 1 ][ i ], addr );
1569
1570
1571
1572
1573
1574
# if ( NB_MMU_MODES >= 3 )
tlb_set_dirty1 ( & env -> tlb_table [ 2 ][ i ], addr );
# if ( NB_MMU_MODES == 4 )
tlb_set_dirty1 ( & env -> tlb_table [ 3 ][ i ], addr );
# endif
# endif
1575
1576
}
1577
1578
1579
1580
/* add a new TLB entry . At most one entry for a given virtual address
is permitted . Return 0 if OK or 2 if the page could not be mapped
( can only happen in non SOFTMMU mode for I / O pages or pages
conflicting with the host address space ). */
1581
1582
1583
int tlb_set_page_exec ( CPUState * env , target_ulong vaddr ,
target_phys_addr_t paddr , int prot ,
int is_user , int is_softmmu )
1584
{
1585
PhysPageDesc * p ;
1586
unsigned long pd ;
1587
unsigned int index ;
1588
target_ulong address ;
1589
target_phys_addr_t addend ;
1590
int ret ;
1591
CPUTLBEntry * te ;
1592
int i ;
1593
1594
p = phys_page_find ( paddr >> TARGET_PAGE_BITS );
1595
1596
1597
1598
1599
1600
if ( ! p ) {
pd = IO_MEM_UNASSIGNED ;
} else {
pd = p -> phys_offset ;
}
# if defined ( DEBUG_TLB )
1601
printf ( "tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x%08x prot=%x u=%d smmu=%d pd=0x%08lx \n " ,
1602
vaddr , ( int ) paddr , prot , is_user , is_softmmu , pd );
1603
1604
1605
1606
1607
1608
1609
# endif
ret = 0 ;
# if ! defined ( CONFIG_SOFTMMU )
if ( is_softmmu )
# endif
{
1610
if (( pd & ~ TARGET_PAGE_MASK ) > IO_MEM_ROM && ! ( pd & IO_MEM_ROMD )) {
1611
1612
1613
1614
1615
1616
1617
1618
/* IO memory case */
address = vaddr | pd ;
addend = paddr ;
} else {
/* standard memory */
address = vaddr ;
addend = ( unsigned long ) phys_ram_base + ( pd & TARGET_PAGE_MASK );
}
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
/* Make accesses to pages with watchpoints go via the
watchpoint trap routines . */
for ( i = 0 ; i < env -> nb_watchpoints ; i ++ ) {
if ( vaddr == ( env -> watchpoint [ i ]. vaddr & TARGET_PAGE_MASK )) {
if ( address & ~ TARGET_PAGE_MASK ) {
env -> watchpoint [ i ]. is_ram = 0 ;
address = vaddr | io_mem_watch ;
} else {
env -> watchpoint [ i ]. is_ram = 1 ;
/* TODO : Figure out how to make read watchpoints coexist
with code . */
pd = ( pd & TARGET_PAGE_MASK ) | io_mem_watch | IO_MEM_ROMD ;
}
}
}
1635
1636
index = ( vaddr >> TARGET_PAGE_BITS ) & ( CPU_TLB_SIZE - 1 );
1637
addend -= vaddr ;
1638
1639
te = & env -> tlb_table [ is_user ][ index ];
te -> addend = addend ;
1640
if ( prot & PAGE_READ ) {
1641
1642
1643
1644
1645
1646
te -> addr_read = address ;
} else {
te -> addr_read = - 1 ;
}
if ( prot & PAGE_EXEC ) {
te -> addr_code = address ;
1647
} else {
1648
te -> addr_code = - 1 ;
1649
}
1650
if ( prot & PAGE_WRITE ) {
1651
1652
1653
1654
1655
if (( pd & ~ TARGET_PAGE_MASK ) == IO_MEM_ROM ||
( pd & IO_MEM_ROMD )) {
/* write access calls the I/O callback */
te -> addr_write = vaddr |
( pd & ~ ( TARGET_PAGE_MASK | IO_MEM_ROMD ));
1656
} else if (( pd & ~ TARGET_PAGE_MASK ) == IO_MEM_RAM &&
1657
! cpu_physical_memory_is_dirty ( pd )) {
1658
te -> addr_write = vaddr | IO_MEM_NOTDIRTY ;
1659
} else {
1660
te -> addr_write = address ;
1661
1662
}
} else {
1663
te -> addr_write = - 1 ;
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
}
}
# if ! defined ( CONFIG_SOFTMMU )
else {
if (( pd & ~ TARGET_PAGE_MASK ) > IO_MEM_ROM ) {
/* IO access : no mapping is done as it will be handled by the
soft MMU */
if ( ! ( env -> hflags & HF_SOFTMMU_MASK ))
ret = 2 ;
} else {
void * map_addr ;
1675
1676
1677
1678
1679
1680
if ( vaddr >= MMAP_AREA_END ) {
ret = 2 ;
} else {
if ( prot & PROT_WRITE ) {
if (( pd & ~ TARGET_PAGE_MASK ) == IO_MEM_ROM ||
1681
# if defined ( TARGET_HAS_SMC ) || 1
1682
first_tb ||
1683
# endif
1684
1685
1686
1687
1688
1689
1690
(( pd & ~ TARGET_PAGE_MASK ) == IO_MEM_RAM &&
! cpu_physical_memory_is_dirty ( pd ))) {
/* ROM: we do as if code was inside */
/* if code is present , we only map as read only and save the
original mapping */
VirtPageDesc * vp ;
1691
vp = virt_page_find_alloc ( vaddr >> TARGET_PAGE_BITS , 1 );
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
vp -> phys_addr = pd ;
vp -> prot = prot ;
vp -> valid_tag = virt_valid_tag ;
prot &= ~ PAGE_WRITE ;
}
}
map_addr = mmap (( void * ) vaddr , TARGET_PAGE_SIZE , prot ,
MAP_SHARED | MAP_FIXED , phys_ram_fd , ( pd & TARGET_PAGE_MASK ));
if ( map_addr == MAP_FAILED ) {
cpu_abort ( env , "mmap failed when mapped physical address 0x%08x to virtual address 0x%08x \n " ,
paddr , vaddr );
1703
1704
1705
1706
1707
1708
1709
1710
1711
1712
}
}
}
}
# endif
return ret ;
}
/* called from signal handler : invalidate the code and unprotect the
page . Return TRUE if the fault was succesfully handled . */
1713
int page_unprotect ( target_ulong addr , unsigned long pc , void * puc )
1714
1715
1716
1717
1718
1719
1720
1721
{
# if ! defined ( CONFIG_SOFTMMU )
VirtPageDesc * vp ;
# if defined ( DEBUG_TLB )
printf ( "page_unprotect: addr=0x%08x \n " , addr );
# endif
addr &= TARGET_PAGE_MASK ;
1722
1723
1724
1725
/* if it is not mapped, no need to worry here */
if ( addr >= MMAP_AREA_END )
return 0 ;
1726
1727
1728
1729
1730
1731
1732
1733
1734
1735
1736
1737
1738
vp = virt_page_find ( addr >> TARGET_PAGE_BITS );
if ( ! vp )
return 0 ;
/* NOTE : in this case , validate_tag is _not_ tested as it
validates only the code TLB */
if ( vp -> valid_tag != virt_valid_tag )
return 0 ;
if ( ! ( vp -> prot & PAGE_WRITE ))
return 0 ;
# if defined ( DEBUG_TLB )
printf ( "page_unprotect: addr=0x%08x phys_addr=0x%08x prot=%x \n " ,
addr , vp -> phys_addr , vp -> prot ) ;
# endif
1739
1740
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if ( mprotect (( void * ) addr , TARGET_PAGE_SIZE , vp -> prot ) < 0 )
cpu_abort ( cpu_single_env , "error mprotect addr=0x%lx prot=%d \n " ,
( unsigned long ) addr , vp -> prot ) ;
1742
/* set the dirty bit */
1743
phys_ram_dirty [ vp -> phys_addr >> TARGET_PAGE_BITS ] = 0xff ;
1744
1745
/* flush the code inside */
tb_invalidate_phys_page ( vp -> phys_addr , pc , puc ) ;
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1749
return 1 ;
# else
return 0 ;
# endif
1750
1751
}
1752
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# else
1754
void tlb_flush ( CPUState * env , int flush_global )
1755
1756
1757
{
}
1758
void tlb_flush_page ( CPUState * env , target_ulong addr )
1759
1760
1761
{
}
1762
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1764
int tlb_set_page_exec ( CPUState * env , target_ulong vaddr ,
target_phys_addr_t paddr , int prot ,
int is_user , int is_softmmu )
1765
1766
1767
{
return 0 ;
}
1768
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1770
/* dump memory mappings */
void page_dump ( FILE * f )
1771
{
1772
1773
1774
unsigned long start , end ;
int i , j , prot , prot1 ;
PageDesc * p ;
1775
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fprintf ( f , "%-8s %-8s %-8s %s \n " ,
"start" , "end" , "size" , "prot" ) ;
start = - 1 ;
end = - 1 ;
prot = 0 ;
for ( i = 0 ; i <= L1_SIZE ; i ++ ) {
if ( i < L1_SIZE )
p = l1_map [ i ] ;
else
p = NULL ;
for ( j = 0 ; j < L2_SIZE ; j ++ ) {
if ( ! p )
prot1 = 0 ;
else
prot1 = p [ j ]. flags ;
if ( prot1 != prot ) {
end = ( i << ( 32 - L1_BITS )) | ( j << TARGET_PAGE_BITS ) ;
if ( start != - 1 ) {
fprintf ( f , "%08lx-%08lx %08lx %c%c%c \n " ,
start , end , end - start ,
prot & PAGE_READ ? 'r' : '-' ,
prot & PAGE_WRITE ? 'w' : '-' ,
prot & PAGE_EXEC ? 'x' : '-' );
}
if ( prot1 != 0 )
start = end ;
else
start = - 1 ;
prot = prot1 ;
}
if ( ! p )
break ;
}
1809
1810
1811
}
}
1812
int page_get_flags ( target_ulong address )
1813
{
1814
1815
1816
PageDesc * p ;
p = page_find ( address >> TARGET_PAGE_BITS );
1817
if ( ! p )
1818
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1820
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1824
return 0 ;
return p -> flags ;
}
/* modify the flags of a page and invalidate the code if
necessary . The flag PAGE_WRITE_ORG is positionned automatically
depending on PAGE_WRITE */
1825
void page_set_flags ( target_ulong start , target_ulong end , int flags )
1826
1827
{
PageDesc * p ;
1828
target_ulong addr ;
1829
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start = start & TARGET_PAGE_MASK ;
end = TARGET_PAGE_ALIGN ( end );
if ( flags & PAGE_WRITE )
flags |= PAGE_WRITE_ORG ;
spin_lock ( & tb_lock );
for ( addr = start ; addr < end ; addr += TARGET_PAGE_SIZE ) {
p = page_find_alloc ( addr >> TARGET_PAGE_BITS );
/* if the write protection is set , then we invalidate the code
inside */
if ( ! ( p -> flags & PAGE_WRITE ) &&
( flags & PAGE_WRITE ) &&
p -> first_tb ) {
1842
tb_invalidate_phys_page ( addr , 0 , NULL );
1843
1844
1845
1846
}
p -> flags = flags ;
}
spin_unlock ( & tb_lock );
1847
1848
}
1849
1850
/* called from signal handler : invalidate the code and unprotect the
page . Return TRUE if the fault was succesfully handled . */
1851
int page_unprotect ( target_ulong address , unsigned long pc , void * puc )
1852
1853
1854
{
unsigned int page_index , prot , pindex ;
PageDesc * p , * p1 ;
1855
target_ulong host_start , host_end , addr ;
1856
1857
host_start = address & qemu_host_page_mask ;
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page_index = host_start >> TARGET_PAGE_BITS ;
p1 = page_find ( page_index );
if ( ! p1 )
return 0 ;
1862
host_end = host_start + qemu_host_page_size ;
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p = p1 ;
prot = 0 ;
for ( addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE ) {
prot |= p -> flags ;
p ++ ;
}
/* if the page was really writable , then we change its
protection back to writable */
if ( prot & PAGE_WRITE_ORG ) {
pindex = ( address - host_start ) >> TARGET_PAGE_BITS ;
if ( ! ( p1 [ pindex ]. flags & PAGE_WRITE )) {
1874
mprotect (( void * ) g2h ( host_start ), qemu_host_page_size ,
1875
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1877
1878
( prot & PAGE_BITS ) | PAGE_WRITE );
p1 [ pindex ]. flags |= PAGE_WRITE ;
/* and since the content will be modified , we must invalidate
the corresponding translated code . */
1879
tb_invalidate_phys_page ( address , pc , puc );
1880
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1889
# ifdef DEBUG_TB_CHECK
tb_invalidate_check ( address );
# endif
return 1 ;
}
}
return 0 ;
}
/* call this function when system calls directly modify a memory area */
1890
1891
/* ??? This should be redundant now we have lock_user. */
void page_unprotect_range ( target_ulong data , target_ulong data_size )
1892
{
1893
target_ulong start , end , addr ;
1894
1895
start = data ;
1896
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1899
end = start + data_size ;
start &= TARGET_PAGE_MASK ;
end = TARGET_PAGE_ALIGN ( end );
for ( addr = start ; addr < end ; addr += TARGET_PAGE_SIZE ) {
1900
page_unprotect ( addr , 0 , NULL );
1901
1902
1903
}
}
1904
1905
static inline void tlb_set_dirty ( CPUState * env ,
unsigned long addr , target_ulong vaddr )
1906
1907
{
}
1908
1909
# endif /* defined(CONFIG_USER_ONLY) */
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static int subpage_register ( subpage_t * mmio , uint32_t start , uint32_t end ,
int memory );
static void * subpage_init ( target_phys_addr_t base , uint32_t * phys ,
int orig_memory );
# define CHECK_SUBPAGE ( addr , start_addr , start_addr2 , end_addr , end_addr2 , \
need_subpage ) \
do { \
if ( addr > start_addr ) \
start_addr2 = 0 ; \
else { \
start_addr2 = start_addr & ~ TARGET_PAGE_MASK ; \
if ( start_addr2 > 0 ) \
need_subpage = 1 ; \
} \
\
if ( end_addr - addr > TARGET_PAGE_SIZE ) \
end_addr2 = TARGET_PAGE_SIZE - 1 ; \
else { \
end_addr2 = ( start_addr + orig_size - 1 ) & ~ TARGET_PAGE_MASK ; \
if ( end_addr2 < TARGET_PAGE_SIZE - 1 ) \
need_subpage = 1 ; \
} \
} while ( 0 )
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/* register physical memory . ' size ' must be a multiple of the target
page size . If ( phys_offset & ~ TARGET_PAGE_MASK ) != 0 , then it is an
io memory page */
1937
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1939
void cpu_register_physical_memory ( target_phys_addr_t start_addr ,
unsigned long size ,
unsigned long phys_offset )
1940
{
1941
target_phys_addr_t addr , end_addr ;
1942
PhysPageDesc * p ;
1943
CPUState * env ;
1944
1945
unsigned long orig_size = size ;
void * subpage ;
1946
1947
end_addr = start_addr + ( target_phys_addr_t ) size ;
1948
size = ( size + TARGET_PAGE_SIZE - 1 ) & TARGET_PAGE_MASK ;
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for ( addr = start_addr ; addr < end_addr ; addr += TARGET_PAGE_SIZE ) {
p = phys_page_find ( addr >> TARGET_PAGE_BITS );
if ( p && p -> phys_offset != IO_MEM_UNASSIGNED ) {
unsigned long orig_memory = p -> phys_offset ;
target_phys_addr_t start_addr2 , end_addr2 ;
int need_subpage = 0 ;
CHECK_SUBPAGE ( addr , start_addr , start_addr2 , end_addr , end_addr2 ,
need_subpage );
if ( need_subpage ) {
if ( ! ( orig_memory & IO_MEM_SUBPAGE )) {
subpage = subpage_init (( addr & TARGET_PAGE_MASK ),
& p -> phys_offset , orig_memory );
} else {
subpage = io_mem_opaque [( orig_memory & ~ TARGET_PAGE_MASK )
>> IO_MEM_SHIFT ];
}
subpage_register ( subpage , start_addr2 , end_addr2 , phys_offset );
} else {
p -> phys_offset = phys_offset ;
if (( phys_offset & ~ TARGET_PAGE_MASK ) <= IO_MEM_ROM ||
( phys_offset & IO_MEM_ROMD ))
phys_offset += TARGET_PAGE_SIZE ;
}
} else {
p = phys_page_find_alloc ( addr >> TARGET_PAGE_BITS , 1 );
p -> phys_offset = phys_offset ;
if (( phys_offset & ~ TARGET_PAGE_MASK ) <= IO_MEM_ROM ||
( phys_offset & IO_MEM_ROMD ))
phys_offset += TARGET_PAGE_SIZE ;
else {
target_phys_addr_t start_addr2 , end_addr2 ;
int need_subpage = 0 ;
CHECK_SUBPAGE ( addr , start_addr , start_addr2 , end_addr ,
end_addr2 , need_subpage );
if ( need_subpage ) {
subpage = subpage_init (( addr & TARGET_PAGE_MASK ),
& p -> phys_offset , IO_MEM_UNASSIGNED );
subpage_register ( subpage , start_addr2 , end_addr2 ,
phys_offset );
}
}
}
1994
}
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2001
/* since each CPU stores ram addresses in its TLB cache , we must
reset the modified entries */
/* XXX: slow ! */
for ( env = first_cpu ; env != NULL ; env = env -> next_cpu ) {
tlb_flush ( env , 1 );
}
2002
2003
}
2004
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2011
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2013
2014
/* XXX: temporary until new memory mapping API */
uint32_t cpu_get_physical_page_desc ( target_phys_addr_t addr )
{
PhysPageDesc * p ;
p = phys_page_find ( addr >> TARGET_PAGE_BITS );
if ( ! p )
return IO_MEM_UNASSIGNED ;
return p -> phys_offset ;
}
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2032
/* XXX: better than nothing */
ram_addr_t qemu_ram_alloc ( unsigned int size )
{
ram_addr_t addr ;
if (( phys_ram_alloc_offset + size ) >= phys_ram_size ) {
fprintf ( stderr , "Not enough memory (requested_size = %u, max memory = %d) \n " ,
size , phys_ram_size );
abort ();
}
addr = phys_ram_alloc_offset ;
phys_ram_alloc_offset = TARGET_PAGE_ALIGN ( phys_ram_alloc_offset + size );
return addr ;
}
void qemu_ram_free ( ram_addr_t addr )
{
}
2033
static uint32_t unassigned_mem_readb ( void * opaque , target_phys_addr_t addr )
2034
{
2035
# ifdef DEBUG_UNASSIGNED
2036
printf ( "Unassigned mem read " TARGET_FMT_lx " \n " , addr );
2037
# endif
2038
# ifdef TARGET_SPARC
2039
do_unassigned_access ( addr , 0 , 0 , 0 );
2040
# endif
2041
2042
2043
return 0 ;
}
2044
static void unassigned_mem_writeb ( void * opaque , target_phys_addr_t addr , uint32_t val )
2045
{
2046
# ifdef DEBUG_UNASSIGNED
2047
printf ( "Unassigned mem write " TARGET_FMT_lx " = 0x%x \n " , addr , val );
2048
# endif
2049
# ifdef TARGET_SPARC
2050
do_unassigned_access ( addr , 1 , 0 , 0 );
2051
# endif
2052
2053
2054
2055
2056
2057
2058
2059
2060
2061
2062
2063
2064
2065
}
static CPUReadMemoryFunc * unassigned_mem_read [ 3 ] = {
unassigned_mem_readb ,
unassigned_mem_readb ,
unassigned_mem_readb ,
};
static CPUWriteMemoryFunc * unassigned_mem_write [ 3 ] = {
unassigned_mem_writeb ,
unassigned_mem_writeb ,
unassigned_mem_writeb ,
};
2066
static void notdirty_mem_writeb ( void * opaque , target_phys_addr_t addr , uint32_t val )
2067
{
2068
2069
2070
2071
2072
unsigned long ram_addr ;
int dirty_flags ;
ram_addr = addr - ( unsigned long ) phys_ram_base ;
dirty_flags = phys_ram_dirty [ ram_addr >> TARGET_PAGE_BITS ];
if ( ! ( dirty_flags & CODE_DIRTY_FLAG )) {
2073
# if ! defined ( CONFIG_USER_ONLY )
2074
2075
tb_invalidate_phys_page_fast ( ram_addr , 1 );
dirty_flags = phys_ram_dirty [ ram_addr >> TARGET_PAGE_BITS ];
2076
# endif
2077
}
2078
stb_p (( uint8_t * )( long ) addr , val );
2079
2080
2081
2082
2083
# ifdef USE_KQEMU
if ( cpu_single_env -> kqemu_enabled &&
( dirty_flags & KQEMU_MODIFY_PAGE_MASK ) != KQEMU_MODIFY_PAGE_MASK )
kqemu_modify_page ( cpu_single_env , ram_addr );
# endif
2084
2085
2086
2087
2088
dirty_flags |= ( 0xff & ~ CODE_DIRTY_FLAG );
phys_ram_dirty [ ram_addr >> TARGET_PAGE_BITS ] = dirty_flags ;
/* we remove the notdirty callback only if the code has been
flushed */
if ( dirty_flags == 0xff )
2089
tlb_set_dirty ( cpu_single_env , addr , cpu_single_env -> mem_write_vaddr );
2090
2091
}
2092
static void notdirty_mem_writew ( void * opaque , target_phys_addr_t addr , uint32_t val )
2093
{
2094
2095
2096
2097
2098
unsigned long ram_addr ;
int dirty_flags ;
ram_addr = addr - ( unsigned long ) phys_ram_base ;
dirty_flags = phys_ram_dirty [ ram_addr >> TARGET_PAGE_BITS ];
if ( ! ( dirty_flags & CODE_DIRTY_FLAG )) {
2099
# if ! defined ( CONFIG_USER_ONLY )
2100
2101
tb_invalidate_phys_page_fast ( ram_addr , 2 );
dirty_flags = phys_ram_dirty [ ram_addr >> TARGET_PAGE_BITS ];
2102
# endif
2103
}
2104
stw_p (( uint8_t * )( long ) addr , val );
2105
2106
2107
2108
2109
# ifdef USE_KQEMU
if ( cpu_single_env -> kqemu_enabled &&
( dirty_flags & KQEMU_MODIFY_PAGE_MASK ) != KQEMU_MODIFY_PAGE_MASK )
kqemu_modify_page ( cpu_single_env , ram_addr );
# endif
2110
2111
2112
2113
2114
dirty_flags |= ( 0xff & ~ CODE_DIRTY_FLAG );
phys_ram_dirty [ ram_addr >> TARGET_PAGE_BITS ] = dirty_flags ;
/* we remove the notdirty callback only if the code has been
flushed */
if ( dirty_flags == 0xff )
2115
tlb_set_dirty ( cpu_single_env , addr , cpu_single_env -> mem_write_vaddr );
2116
2117
}
2118
static void notdirty_mem_writel ( void * opaque , target_phys_addr_t addr , uint32_t val )
2119
{
2120
2121
2122
2123
2124
unsigned long ram_addr ;
int dirty_flags ;
ram_addr = addr - ( unsigned long ) phys_ram_base ;
dirty_flags = phys_ram_dirty [ ram_addr >> TARGET_PAGE_BITS ];
if ( ! ( dirty_flags & CODE_DIRTY_FLAG )) {
2125
# if ! defined ( CONFIG_USER_ONLY )
2126
2127
tb_invalidate_phys_page_fast ( ram_addr , 4 );
dirty_flags = phys_ram_dirty [ ram_addr >> TARGET_PAGE_BITS ];
2128
# endif
2129
}
2130
stl_p (( uint8_t * )( long ) addr , val );
2131
2132
2133
2134
2135
# ifdef USE_KQEMU
if ( cpu_single_env -> kqemu_enabled &&
( dirty_flags & KQEMU_MODIFY_PAGE_MASK ) != KQEMU_MODIFY_PAGE_MASK )
kqemu_modify_page ( cpu_single_env , ram_addr );
# endif
2136
2137
2138
2139
2140
dirty_flags |= ( 0xff & ~ CODE_DIRTY_FLAG );
phys_ram_dirty [ ram_addr >> TARGET_PAGE_BITS ] = dirty_flags ;
/* we remove the notdirty callback only if the code has been
flushed */
if ( dirty_flags == 0xff )
2141
tlb_set_dirty ( cpu_single_env , addr , cpu_single_env -> mem_write_vaddr );
2142
2143
}
2144
static CPUReadMemoryFunc * error_mem_read [ 3 ] = {
2145
2146
2147
2148
2149
NULL , /* never used */
NULL , /* never used */
NULL , /* never used */
};
2150
2151
2152
2153
2154
2155
static CPUWriteMemoryFunc * notdirty_mem_write [ 3 ] = {
notdirty_mem_writeb ,
notdirty_mem_writew ,
notdirty_mem_writel ,
};
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166
2167
2168
2169
2170
2171
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2173
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2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
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2190
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2199
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2201
2202
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2204
2205
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2209
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2219
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2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
# if defined ( CONFIG_SOFTMMU )
/* Watchpoint access routines . Watchpoints are inserted using TLB tricks ,
so these check for a hit then pass through to the normal out - of - line
phys routines . */
static uint32_t watch_mem_readb ( void * opaque , target_phys_addr_t addr )
{
return ldub_phys ( addr );
}
static uint32_t watch_mem_readw ( void * opaque , target_phys_addr_t addr )
{
return lduw_phys ( addr );
}
static uint32_t watch_mem_readl ( void * opaque , target_phys_addr_t addr )
{
return ldl_phys ( addr );
}
/* Generate a debug exception if a watchpoint has been hit .
Returns the real physical address of the access . addr will be a host
address in the is_ram case . */
static target_ulong check_watchpoint ( target_phys_addr_t addr )
{
CPUState * env = cpu_single_env ;
target_ulong watch ;
target_ulong retaddr ;
int i ;
retaddr = addr ;
for ( i = 0 ; i < env -> nb_watchpoints ; i ++ ) {
watch = env -> watchpoint [ i ]. vaddr ;
if ((( env -> mem_write_vaddr ^ watch ) & TARGET_PAGE_MASK ) == 0 ) {
if ( env -> watchpoint [ i ]. is_ram )
retaddr = addr - ( unsigned long ) phys_ram_base ;
if ((( addr ^ watch ) & ~ TARGET_PAGE_MASK ) == 0 ) {
cpu_single_env -> watchpoint_hit = i + 1 ;
cpu_interrupt ( cpu_single_env , CPU_INTERRUPT_DEBUG ) ;
break ;
}
}
}
return retaddr ;
}
static void watch_mem_writeb ( void * opaque , target_phys_addr_t addr ,
uint32_t val )
{
addr = check_watchpoint ( addr ) ;
stb_phys ( addr , val ) ;
}
static void watch_mem_writew ( void * opaque , target_phys_addr_t addr ,
uint32_t val )
{
addr = check_watchpoint ( addr ) ;
stw_phys ( addr , val ) ;
}
static void watch_mem_writel ( void * opaque , target_phys_addr_t addr ,
uint32_t val )
{
addr = check_watchpoint ( addr ) ;
stl_phys ( addr , val ) ;
}
static CPUReadMemoryFunc * watch_mem_read [ 3 ] = {
watch_mem_readb ,
watch_mem_readw ,
watch_mem_readl ,
};
static CPUWriteMemoryFunc * watch_mem_write [ 3 ] = {
watch_mem_writeb ,
watch_mem_writew ,
watch_mem_writel ,
};
# endif
2235
2236
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2372
2373
2374
2375
2376
2377
static inline uint32_t subpage_readlen ( subpage_t * mmio , target_phys_addr_t addr ,
unsigned int len )
{
CPUReadMemoryFunc ** mem_read ;
uint32_t ret ;
unsigned int idx ;
idx = SUBPAGE_IDX ( addr - mmio -> base ) ;
# if defined ( DEBUG_SUBPAGE )
printf ( "%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d \n " , __func__ ,
mmio , len , addr , idx ) ;
# endif
mem_read = mmio -> mem_read [ idx ] ;
ret = ( * mem_read [ len ])( mmio -> opaque [ idx ], addr ) ;
return ret ;
}
static inline void subpage_writelen ( subpage_t * mmio , target_phys_addr_t addr ,
uint32_t value , unsigned int len )
{
CPUWriteMemoryFunc ** mem_write ;
unsigned int idx ;
idx = SUBPAGE_IDX ( addr - mmio -> base ) ;
# if defined ( DEBUG_SUBPAGE )
printf ( "%s: subpage %p len %d addr " TARGET_FMT_plx " idx %d value %08x \n " , __func__ ,
mmio , len , addr , idx , value ) ;
# endif
mem_write = mmio -> mem_write [ idx ] ;
( * mem_write [ len ])( mmio -> opaque [ idx ], addr , value ) ;
}
static uint32_t subpage_readb ( void * opaque , target_phys_addr_t addr )
{
# if defined ( DEBUG_SUBPAGE )
printf ( "%s: addr " TARGET_FMT_plx " \n " , __func__ , addr ) ;
# endif
return subpage_readlen ( opaque , addr , 0 ) ;
}
static void subpage_writeb ( void * opaque , target_phys_addr_t addr ,
uint32_t value )
{
# if defined ( DEBUG_SUBPAGE )
printf ( "%s: addr " TARGET_FMT_plx " val %08x \n " , __func__ , addr , value ) ;
# endif
subpage_writelen ( opaque , addr , value , 0 ) ;
}
static uint32_t subpage_readw ( void * opaque , target_phys_addr_t addr )
{
# if defined ( DEBUG_SUBPAGE )
printf ( "%s: addr " TARGET_FMT_plx " \n " , __func__ , addr ) ;
# endif
return subpage_readlen ( opaque , addr , 1 ) ;
}
static void subpage_writew ( void * opaque , target_phys_addr_t addr ,
uint32_t value )
{
# if defined ( DEBUG_SUBPAGE )
printf ( "%s: addr " TARGET_FMT_plx " val %08x \n " , __func__ , addr , value ) ;
# endif
subpage_writelen ( opaque , addr , value , 1 ) ;
}
static uint32_t subpage_readl ( void * opaque , target_phys_addr_t addr )
{
# if defined ( DEBUG_SUBPAGE )
printf ( "%s: addr " TARGET_FMT_plx " \n " , __func__ , addr ) ;
# endif
return subpage_readlen ( opaque , addr , 2 ) ;
}
static void subpage_writel ( void * opaque ,
target_phys_addr_t addr , uint32_t value )
{
# if defined ( DEBUG_SUBPAGE )
printf ( "%s: addr " TARGET_FMT_plx " val %08x \n " , __func__ , addr , value ) ;
# endif
subpage_writelen ( opaque , addr , value , 2 ) ;
}
static CPUReadMemoryFunc * subpage_read [] = {
& subpage_readb ,
& subpage_readw ,
& subpage_readl ,
};
static CPUWriteMemoryFunc * subpage_write [] = {
& subpage_writeb ,
& subpage_writew ,
& subpage_writel ,
};
static int subpage_register ( subpage_t * mmio , uint32_t start , uint32_t end ,
int memory )
{
int idx , eidx ;
if ( start >= TARGET_PAGE_SIZE || end >= TARGET_PAGE_SIZE )
return - 1 ;
idx = SUBPAGE_IDX ( start ) ;
eidx = SUBPAGE_IDX ( end ) ;
# if defined ( DEBUG_SUBPAGE )
printf ( "%s: %p start %08x end %08x idx %08x eidx %08x mem %d \n " , __func__ ,
mmio , start , end , idx , eidx , memory ) ;
# endif
memory >>= IO_MEM_SHIFT ;
for ( ; idx <= eidx ; idx ++ ) {
mmio -> mem_read [ idx ] = io_mem_read [ memory ] ;
mmio -> mem_write [ idx ] = io_mem_write [ memory ] ;
mmio -> opaque [ idx ] = io_mem_opaque [ memory ] ;
}
return 0 ;
}
static void * subpage_init ( target_phys_addr_t base , uint32_t * phys ,
int orig_memory )
{
subpage_t * mmio ;
int subpage_memory ;
mmio = qemu_mallocz ( sizeof ( subpage_t )) ;
if ( mmio != NULL ) {
mmio -> base = base ;
subpage_memory = cpu_register_io_memory ( 0 , subpage_read , subpage_write , mmio ) ;
# if defined ( DEBUG_SUBPAGE )
printf ( "%s: %p base " TARGET_FMT_plx " len %08x %d \n " , __func__ ,
mmio , base , TARGET_PAGE_SIZE , subpage_memory ) ;
# endif
* phys = subpage_memory | IO_MEM_SUBPAGE ;
subpage_register ( mmio , 0 , TARGET_PAGE_SIZE - 1 , orig_memory ) ;
}
return mmio ;
}
2378
2379
static void io_mem_init ( void )
{
2380
cpu_register_io_memory ( IO_MEM_ROM >> IO_MEM_SHIFT , error_mem_read , unassigned_mem_write , NULL ) ;
2381
cpu_register_io_memory ( IO_MEM_UNASSIGNED >> IO_MEM_SHIFT , unassigned_mem_read , unassigned_mem_write , NULL ) ;
2382
cpu_register_io_memory ( IO_MEM_NOTDIRTY >> IO_MEM_SHIFT , error_mem_read , notdirty_mem_write , NULL ) ;
2383
2384
io_mem_nb = 5 ;
2385
2386
2387
2388
# if defined ( CONFIG_SOFTMMU )
io_mem_watch = cpu_register_io_memory ( - 1 , watch_mem_read ,
watch_mem_write , NULL ) ;
# endif
2389
/* alloc dirty bits array */
2390
phys_ram_dirty = qemu_vmalloc ( phys_ram_size >> TARGET_PAGE_BITS ) ;
2391
memset ( phys_ram_dirty , 0xff , phys_ram_size >> TARGET_PAGE_BITS ) ;
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
}
/* mem_read and mem_write are arrays of functions containing the
function to access byte ( index 0 ), word ( index 1 ) and dword ( index
2 ). All functions must be supplied . If io_index is non zero , the
corresponding io zone is modified . If it is zero , a new io zone is
allocated . The return value can be used with
cpu_register_physical_memory (). ( - 1 ) is returned if error . */
int cpu_register_io_memory ( int io_index ,
CPUReadMemoryFunc ** mem_read ,
2402
2403
CPUWriteMemoryFunc ** mem_write ,
void * opaque )
2404
2405
2406
2407
{
int i ;
if ( io_index <= 0 ) {
2408
if ( io_mem_nb >= IO_MEM_NB_ENTRIES )
2409
2410
2411
2412
2413
2414
return - 1 ;
io_index = io_mem_nb ++ ;
} else {
if ( io_index >= IO_MEM_NB_ENTRIES )
return - 1 ;
}
2415
2416
2417
2418
2419
for ( i = 0 ; i < 3 ; i ++ ) {
io_mem_read [ io_index ][ i ] = mem_read [ i ] ;
io_mem_write [ io_index ][ i ] = mem_write [ i ] ;
}
2420
io_mem_opaque [ io_index ] = opaque ;
2421
2422
return io_index << IO_MEM_SHIFT ;
}
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
CPUWriteMemoryFunc ** cpu_get_io_memory_write ( int io_index )
{
return io_mem_write [ io_index >> IO_MEM_SHIFT ] ;
}
CPUReadMemoryFunc ** cpu_get_io_memory_read ( int io_index )
{
return io_mem_read [ io_index >> IO_MEM_SHIFT ] ;
}
2434
2435
/* physical memory access (slow version, mainly for debug) */
# if defined ( CONFIG_USER_ONLY )
2436
void cpu_physical_memory_rw ( target_phys_addr_t addr , uint8_t * buf ,
2437
2438
2439
2440
int len , int is_write )
{
int l , flags ;
target_ulong page ;
2441
void * p ;
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
while ( len > 0 ) {
page = addr & TARGET_PAGE_MASK ;
l = ( page + TARGET_PAGE_SIZE ) - addr ;
if ( l > len )
l = len ;
flags = page_get_flags ( page ) ;
if ( ! ( flags & PAGE_VALID ))
return ;
if ( is_write ) {
if ( ! ( flags & PAGE_WRITE ))
return ;
2454
2455
2456
p = lock_user ( addr , len , 0 ) ;
memcpy ( p , buf , len ) ;
unlock_user ( p , addr , len ) ;
2457
2458
2459
} else {
if ( ! ( flags & PAGE_READ ))
return ;
2460
2461
2462
p = lock_user ( addr , len , 1 ) ;
memcpy ( buf , p , len ) ;
unlock_user ( p , addr , 0 ) ;
2463
2464
2465
2466
2467
2468
}
len -= l ;
buf += l ;
addr += l ;
}
}
2469
2470
# else
2471
void cpu_physical_memory_rw ( target_phys_addr_t addr , uint8_t * buf ,
2472
2473
2474
2475
2476
int len , int is_write )
{
int l , io_index ;
uint8_t * ptr ;
uint32_t val ;
2477
2478
target_phys_addr_t page ;
unsigned long pd ;
2479
PhysPageDesc * p ;
2480
2481
2482
2483
2484
2485
while ( len > 0 ) {
page = addr & TARGET_PAGE_MASK ;
l = ( page + TARGET_PAGE_SIZE ) - addr ;
if ( l > len )
l = len ;
2486
p = phys_page_find ( page >> TARGET_PAGE_BITS ) ;
2487
2488
2489
2490
2491
2492
2493
if ( ! p ) {
pd = IO_MEM_UNASSIGNED ;
} else {
pd = p -> phys_offset ;
}
if ( is_write ) {
2494
if (( pd & ~ TARGET_PAGE_MASK ) != IO_MEM_RAM ) {
2495
io_index = ( pd >> IO_MEM_SHIFT ) & ( IO_MEM_NB_ENTRIES - 1 ) ;
2496
2497
/* XXX : could force cpu_single_env to NULL to avoid
potential bugs */
2498
if ( l >= 4 && (( addr & 3 ) == 0 )) {
2499
/* 32 bit write access */
2500
val = ldl_p ( buf );
2501
io_mem_write [ io_index ][ 2 ]( io_mem_opaque [ io_index ], addr , val );
2502
2503
l = 4 ;
} else if ( l >= 2 && (( addr & 1 ) == 0 )) {
2504
/* 16 bit write access */
2505
val = lduw_p ( buf );
2506
io_mem_write [ io_index ][ 1 ]( io_mem_opaque [ io_index ], addr , val );
2507
2508
l = 2 ;
} else {
2509
/* 8 bit write access */
2510
val = ldub_p ( buf );
2511
io_mem_write [ io_index ][ 0 ]( io_mem_opaque [ io_index ], addr , val );
2512
2513
2514
l = 1 ;
}
} else {
2515
2516
unsigned long addr1 ;
addr1 = ( pd & TARGET_PAGE_MASK ) + ( addr & ~ TARGET_PAGE_MASK );
2517
/* RAM case */
2518
ptr = phys_ram_base + addr1 ;
2519
memcpy ( ptr , buf , l );
2520
2521
2522
2523
if ( ! cpu_physical_memory_is_dirty ( addr1 )) {
/* invalidate code */
tb_invalidate_phys_page_range ( addr1 , addr1 + l , 0 );
/* set dirty bit */
2524
2525
phys_ram_dirty [ addr1 >> TARGET_PAGE_BITS ] |=
( 0xff & ~ CODE_DIRTY_FLAG );
2526
}
2527
2528
}
} else {
2529
2530
if (( pd & ~ TARGET_PAGE_MASK ) > IO_MEM_ROM &&
! ( pd & IO_MEM_ROMD )) {
2531
2532
2533
2534
/* I/O case */
io_index = ( pd >> IO_MEM_SHIFT ) & ( IO_MEM_NB_ENTRIES - 1 );
if ( l >= 4 && (( addr & 3 ) == 0 )) {
/* 32 bit read access */
2535
val = io_mem_read [ io_index ][ 2 ]( io_mem_opaque [ io_index ], addr );
2536
stl_p ( buf , val );
2537
2538
2539
l = 4 ;
} else if ( l >= 2 && (( addr & 1 ) == 0 )) {
/* 16 bit read access */
2540
val = io_mem_read [ io_index ][ 1 ]( io_mem_opaque [ io_index ], addr );
2541
stw_p ( buf , val );
2542
2543
l = 2 ;
} else {
2544
/* 8 bit read access */
2545
val = io_mem_read [ io_index ][ 0 ]( io_mem_opaque [ io_index ], addr );
2546
stb_p ( buf , val );
2547
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
l = 1 ;
}
} else {
/* RAM case */
ptr = phys_ram_base + ( pd & TARGET_PAGE_MASK ) +
( addr & ~ TARGET_PAGE_MASK );
memcpy ( buf , ptr , l );
}
}
len -= l ;
buf += l ;
addr += l ;
}
}
2561
2562
2563
2564
2565
2566
2567
2568
2569
2570
2571
2572
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
/* used for ROM loading : can write in RAM and ROM */
void cpu_physical_memory_write_rom ( target_phys_addr_t addr ,
const uint8_t * buf , int len )
{
int l ;
uint8_t * ptr ;
target_phys_addr_t page ;
unsigned long pd ;
PhysPageDesc * p ;
while ( len > 0 ) {
page = addr & TARGET_PAGE_MASK ;
l = ( page + TARGET_PAGE_SIZE ) - addr ;
if ( l > len )
l = len ;
p = phys_page_find ( page >> TARGET_PAGE_BITS );
if ( ! p ) {
pd = IO_MEM_UNASSIGNED ;
} else {
pd = p -> phys_offset ;
}
if (( pd & ~ TARGET_PAGE_MASK ) != IO_MEM_RAM &&
2585
2586
( pd & ~ TARGET_PAGE_MASK ) != IO_MEM_ROM &&
! ( pd & IO_MEM_ROMD )) {
2587
2588
2589
2590
2591
2592
2593
2594
2595
2596
2597
2598
2599
2600
2601
/* do nothing */
} else {
unsigned long addr1 ;
addr1 = ( pd & TARGET_PAGE_MASK ) + ( addr & ~ TARGET_PAGE_MASK );
/* ROM/RAM case */
ptr = phys_ram_base + addr1 ;
memcpy ( ptr , buf , l );
}
len -= l ;
buf += l ;
addr += l ;
}
}
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
/* warning: addr must be aligned */
uint32_t ldl_phys ( target_phys_addr_t addr )
{
int io_index ;
uint8_t * ptr ;
uint32_t val ;
unsigned long pd ;
PhysPageDesc * p ;
p = phys_page_find ( addr >> TARGET_PAGE_BITS );
if ( ! p ) {
pd = IO_MEM_UNASSIGNED ;
} else {
pd = p -> phys_offset ;
}
2618
2619
if (( pd & ~ TARGET_PAGE_MASK ) > IO_MEM_ROM &&
! ( pd & IO_MEM_ROMD )) {
2620
2621
2622
2623
2624
2625
2626
2627
2628
2629
2630
2631
/* I/O case */
io_index = ( pd >> IO_MEM_SHIFT ) & ( IO_MEM_NB_ENTRIES - 1 );
val = io_mem_read [ io_index ][ 2 ]( io_mem_opaque [ io_index ], addr );
} else {
/* RAM case */
ptr = phys_ram_base + ( pd & TARGET_PAGE_MASK ) +
( addr & ~ TARGET_PAGE_MASK );
val = ldl_p ( ptr );
}
return val ;
}
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642
2643
2644
2645
2646
2647
/* warning: addr must be aligned */
uint64_t ldq_phys ( target_phys_addr_t addr )
{
int io_index ;
uint8_t * ptr ;
uint64_t val ;
unsigned long pd ;
PhysPageDesc * p ;
p = phys_page_find ( addr >> TARGET_PAGE_BITS );
if ( ! p ) {
pd = IO_MEM_UNASSIGNED ;
} else {
pd = p -> phys_offset ;
}
2648
2649
if (( pd & ~ TARGET_PAGE_MASK ) > IO_MEM_ROM &&
! ( pd & IO_MEM_ROMD )) {
2650
2651
2652
2653
2654
2655
2656
2657
2658
2659
2660
2661
2662
2663
2664
2665
2666
2667
/* I/O case */
io_index = ( pd >> IO_MEM_SHIFT ) & ( IO_MEM_NB_ENTRIES - 1 );
# ifdef TARGET_WORDS_BIGENDIAN
val = ( uint64_t ) io_mem_read [ io_index ][ 2 ]( io_mem_opaque [ io_index ], addr ) << 32 ;
val |= io_mem_read [ io_index ][ 2 ]( io_mem_opaque [ io_index ], addr + 4 );
# else
val = io_mem_read [ io_index ][ 2 ]( io_mem_opaque [ io_index ], addr );
val |= ( uint64_t ) io_mem_read [ io_index ][ 2 ]( io_mem_opaque [ io_index ], addr + 4 ) << 32 ;
# endif
} else {
/* RAM case */
ptr = phys_ram_base + ( pd & TARGET_PAGE_MASK ) +
( addr & ~ TARGET_PAGE_MASK );
val = ldq_p ( ptr );
}
return val ;
}
2668
2669
2670
2671
2672
2673
2674
2675
2676
2677
2678
2679
2680
2681
2682
2683
/* XXX: optimize */
uint32_t ldub_phys ( target_phys_addr_t addr )
{
uint8_t val ;
cpu_physical_memory_read ( addr , & val , 1 );
return val ;
}
/* XXX: optimize */
uint32_t lduw_phys ( target_phys_addr_t addr )
{
uint16_t val ;
cpu_physical_memory_read ( addr , ( uint8_t * ) & val , 2 );
return tswap16 ( val );
}
2684
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695
2696
2697
2698
2699
2700
/* warning : addr must be aligned . The ram page is not masked as dirty
and the code inside is not invalidated . It is useful if the dirty
bits are used to track modified PTEs */
void stl_phys_notdirty ( target_phys_addr_t addr , uint32_t val )
{
int io_index ;
uint8_t * ptr ;
unsigned long pd ;
PhysPageDesc * p ;
p = phys_page_find ( addr >> TARGET_PAGE_BITS );
if ( ! p ) {
pd = IO_MEM_UNASSIGNED ;
} else {
pd = p -> phys_offset ;
}
2701
if (( pd & ~ TARGET_PAGE_MASK ) != IO_MEM_RAM ) {
2702
2703
2704
2705
2706
2707
2708
2709
2710
io_index = ( pd >> IO_MEM_SHIFT ) & ( IO_MEM_NB_ENTRIES - 1 );
io_mem_write [ io_index ][ 2 ]( io_mem_opaque [ io_index ], addr , val );
} else {
ptr = phys_ram_base + ( pd & TARGET_PAGE_MASK ) +
( addr & ~ TARGET_PAGE_MASK );
stl_p ( ptr , val );
}
}
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
void stq_phys_notdirty ( target_phys_addr_t addr , uint64_t val )
{
int io_index ;
uint8_t * ptr ;
unsigned long pd ;
PhysPageDesc * p ;
p = phys_page_find ( addr >> TARGET_PAGE_BITS );
if ( ! p ) {
pd = IO_MEM_UNASSIGNED ;
} else {
pd = p -> phys_offset ;
}
if (( pd & ~ TARGET_PAGE_MASK ) != IO_MEM_RAM ) {
io_index = ( pd >> IO_MEM_SHIFT ) & ( IO_MEM_NB_ENTRIES - 1 );
# ifdef TARGET_WORDS_BIGENDIAN
io_mem_write [ io_index ][ 2 ]( io_mem_opaque [ io_index ], addr , val >> 32 );
io_mem_write [ io_index ][ 2 ]( io_mem_opaque [ io_index ], addr + 4 , val );
# else
io_mem_write [ io_index ][ 2 ]( io_mem_opaque [ io_index ], addr , val );
io_mem_write [ io_index ][ 2 ]( io_mem_opaque [ io_index ], addr + 4 , val >> 32 );
# endif
} else {
ptr = phys_ram_base + ( pd & TARGET_PAGE_MASK ) +
( addr & ~ TARGET_PAGE_MASK );
stq_p ( ptr , val );
}
}
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
/* warning: addr must be aligned */
void stl_phys ( target_phys_addr_t addr , uint32_t val )
{
int io_index ;
uint8_t * ptr ;
unsigned long pd ;
PhysPageDesc * p ;
p = phys_page_find ( addr >> TARGET_PAGE_BITS );
if ( ! p ) {
pd = IO_MEM_UNASSIGNED ;
} else {
pd = p -> phys_offset ;
}
2756
if (( pd & ~ TARGET_PAGE_MASK ) != IO_MEM_RAM ) {
2757
2758
2759
2760
2761
2762
2763
2764
io_index = ( pd >> IO_MEM_SHIFT ) & ( IO_MEM_NB_ENTRIES - 1 );
io_mem_write [ io_index ][ 2 ]( io_mem_opaque [ io_index ], addr , val );
} else {
unsigned long addr1 ;
addr1 = ( pd & TARGET_PAGE_MASK ) + ( addr & ~ TARGET_PAGE_MASK );
/* RAM case */
ptr = phys_ram_base + addr1 ;
stl_p ( ptr , val );
2765
2766
2767
2768
if ( ! cpu_physical_memory_is_dirty ( addr1 )) {
/* invalidate code */
tb_invalidate_phys_page_range ( addr1 , addr1 + 4 , 0 );
/* set dirty bit */
2769
2770
phys_ram_dirty [ addr1 >> TARGET_PAGE_BITS ] |=
( 0xff & ~ CODE_DIRTY_FLAG );
2771
}
2772
2773
2774
}
}
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
/* XXX: optimize */
void stb_phys ( target_phys_addr_t addr , uint32_t val )
{
uint8_t v = val ;
cpu_physical_memory_write ( addr , & v , 1 );
}
/* XXX: optimize */
void stw_phys ( target_phys_addr_t addr , uint32_t val )
{
uint16_t v = tswap16 ( val );
cpu_physical_memory_write ( addr , ( const uint8_t * ) & v , 2 );
}
/* XXX: optimize */
void stq_phys ( target_phys_addr_t addr , uint64_t val )
{
val = tswap64 ( val );
cpu_physical_memory_write ( addr , ( const uint8_t * ) & val , 8 );
}
2796
2797
2798
# endif
/* virtual memory access for debug */
2799
2800
int cpu_memory_rw_debug ( CPUState * env , target_ulong addr ,
uint8_t * buf , int len , int is_write )
2801
2802
{
int l ;
2803
2804
target_phys_addr_t phys_addr ;
target_ulong page ;
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
while ( len > 0 ) {
page = addr & TARGET_PAGE_MASK ;
phys_addr = cpu_get_phys_page_debug ( env , page );
/* if no physical page mapped, return an error */
if ( phys_addr == - 1 )
return - 1 ;
l = ( page + TARGET_PAGE_SIZE ) - addr ;
if ( l > len )
l = len ;
2815
2816
cpu_physical_memory_rw ( phys_addr + ( addr & ~ TARGET_PAGE_MASK ),
buf , l , is_write );
2817
2818
2819
2820
2821
2822
2823
len -= l ;
buf += l ;
addr += l ;
}
return 0 ;
}
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
void dump_exec_info ( FILE * f ,
int ( * cpu_fprintf )( FILE * f , const char * fmt , ...))
{
int i , target_code_size , max_target_code_size ;
int direct_jmp_count , direct_jmp2_count , cross_page ;
TranslationBlock * tb ;
target_code_size = 0 ;
max_target_code_size = 0 ;
cross_page = 0 ;
direct_jmp_count = 0 ;
direct_jmp2_count = 0 ;
for ( i = 0 ; i < nb_tbs ; i ++ ) {
tb = & tbs [ i ];
target_code_size += tb -> size ;
if ( tb -> size > max_target_code_size )
max_target_code_size = tb -> size ;
if ( tb -> page_addr [ 1 ] != - 1 )
cross_page ++ ;
if ( tb -> tb_next_offset [ 0 ] != 0xffff ) {
direct_jmp_count ++ ;
if ( tb -> tb_next_offset [ 1 ] != 0xffff ) {
direct_jmp2_count ++ ;
}
}
}
/* XXX: avoid using doubles ? */
cpu_fprintf ( f , "TB count %d \n " , nb_tbs );
cpu_fprintf ( f , "TB avg target size %d max=%d bytes \n " ,
nb_tbs ? target_code_size / nb_tbs : 0 ,
max_target_code_size );
cpu_fprintf ( f , "TB avg host size %d bytes (expansion ratio: %0.1f) \n " ,
nb_tbs ? ( code_gen_ptr - code_gen_buffer ) / nb_tbs : 0 ,
target_code_size ? ( double ) ( code_gen_ptr - code_gen_buffer ) / target_code_size : 0 );
cpu_fprintf ( f , "cross page TB count %d (%d%%) \n " ,
cross_page ,
nb_tbs ? ( cross_page * 100 ) / nb_tbs : 0 );
cpu_fprintf ( f , "direct jump count %d (%d%%) (2 jumps=%d %d%%) \n " ,
direct_jmp_count ,
nb_tbs ? ( direct_jmp_count * 100 ) / nb_tbs : 0 ,
direct_jmp2_count ,
nb_tbs ? ( direct_jmp2_count * 100 ) / nb_tbs : 0 );
cpu_fprintf ( f , "TB flush count %d \n " , tb_flush_count );
cpu_fprintf ( f , "TB invalidate count %d \n " , tb_phys_invalidate_count );
cpu_fprintf ( f , "TLB flush count %d \n " , tlb_flush_count );
}
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# if ! defined ( CONFIG_USER_ONLY )
# define MMUSUFFIX _cmmu
# define GETPC () NULL
# define env cpu_single_env
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# define SOFTMMU_CODE_ACCESS
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# define SHIFT 0
# include "softmmu_template.h"
# define SHIFT 1
# include "softmmu_template.h"
# define SHIFT 2
# include "softmmu_template.h"
# define SHIFT 3
# include "softmmu_template.h"
# undef env
# endif