gwj / at91sam9263 · Commits

Commit 2e12669a4c06c7d26351b0c250db9b1ad72ba76f

Authored by bellard
1 parent 52c00a5f

consistent use of target_ulong and target_phys_addr_t 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@758 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 5 changed files with 67 additions and 62 deletions
cpu-all.h
  View file @2e12669
... ... @@ -620,8 +620,8 @@ extern int code_copy_enabled;
620 620 #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
621 621 void cpu_interrupt(CPUState *s, int mask);
622 622  
623   -int cpu_breakpoint_insert(CPUState *env, uint32_t pc);
624   -int cpu_breakpoint_remove(CPUState *env, uint32_t pc);
  623 +int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
  624 +int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
625 625 void cpu_single_step(CPUState *env, int enabled);
626 626  
627 627 /* Return the physical page corresponding to a virtual one. Use it
... ... @@ -681,24 +681,25 @@ extern uint8_t *phys_ram_dirty;
681 681 #define IO_MEM_CODE (3 << IO_MEM_SHIFT) /* used internally, never use directly */
682 682 #define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */
683 683  
684   -typedef void CPUWriteMemoryFunc(uint32_t addr, uint32_t value);
685   -typedef uint32_t CPUReadMemoryFunc(uint32_t addr);
  684 +typedef void CPUWriteMemoryFunc(target_phys_addr_t addr, uint32_t value);
  685 +typedef uint32_t CPUReadMemoryFunc(target_phys_addr_t addr);
686 686  
687   -void cpu_register_physical_memory(unsigned long start_addr, unsigned long size,
688   - long phys_offset);
  687 +void cpu_register_physical_memory(target_phys_addr_t start_addr,
  688 + unsigned long size,
  689 + unsigned long phys_offset);
689 690 int cpu_register_io_memory(int io_index,
690 691 CPUReadMemoryFunc **mem_read,
691 692 CPUWriteMemoryFunc **mem_write);
692 693  
693   -void cpu_physical_memory_rw(target_ulong addr, uint8_t *buf,
  694 +void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
694 695 int len, int is_write);
695   -static inline void cpu_physical_memory_read(target_ulong addr, uint8_t *buf,
696   - int len)
  696 +static inline void cpu_physical_memory_read(target_phys_addr_t addr,
  697 + uint8_t *buf, int len)
697 698 {
698 699 cpu_physical_memory_rw(addr, buf, len, 0);
699 700 }
700   -static inline void cpu_physical_memory_write(target_ulong addr, const uint8_t *buf,
701   - int len)
  701 +static inline void cpu_physical_memory_write(target_phys_addr_t addr,
  702 + const uint8_t *buf, int len)
702 703 {
703 704 cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
704 705 }
... ...
exec-all.h
  View file @2e12669
... ... @@ -86,13 +86,16 @@ int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
86 86 int cpu_restore_state_copy(struct TranslationBlock *tb,
87 87 CPUState *env, unsigned long searched_pc,
88 88 void *puc);
  89 +void cpu_resume_from_signal(CPUState *env1, void *puc);
89 90 void cpu_exec_init(void);
90   -int page_unprotect(unsigned long address);
  91 +int page_unprotect(unsigned long address, unsigned long pc, void *puc);
  92 +void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
  93 + int is_cpu_write_access);
91 94 void tb_invalidate_page_range(target_ulong start, target_ulong end);
92   -void tlb_flush_page(CPUState *env, uint32_t addr);
93   -void tlb_flush_page_write(CPUState *env, uint32_t addr);
  95 +void tlb_flush_page(CPUState *env, target_ulong addr);
94 96 void tlb_flush(CPUState *env, int flush_global);
95   -int tlb_set_page(CPUState *env, uint32_t vaddr, uint32_t paddr, int prot,
  97 +int tlb_set_page(CPUState *env, target_ulong vaddr,
  98 + target_phys_addr_t paddr, int prot,
96 99 int is_user, int is_softmmu);
97 100  
98 101 #define CODE_GEN_MAX_SIZE 65536
... ... @@ -146,8 +149,8 @@ int tlb_set_page(CPUState *env, uint32_t vaddr, uint32_t paddr, int prot,
146 149 #endif
147 150  
148 151 typedef struct TranslationBlock {
149   - unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */
150   - unsigned long cs_base; /* CS base for this block */
  152 + target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
  153 + target_ulong cs_base; /* CS base for this block */
151 154 unsigned int flags; /* flags defining in which context the code was generated */
152 155 uint16_t size; /* size of target code for this block (1 <=
153 156 size <= TARGET_PAGE_SIZE) */
... ... @@ -155,6 +158,7 @@ typedef struct TranslationBlock {
155 158 #define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */
156 159 #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */
157 160 #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */
  161 +#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
158 162  
159 163 uint8_t *tc_ptr; /* pointer to the translated code */
160 164 struct TranslationBlock *hash_next; /* next matching tb for virtual address */
... ... @@ -206,8 +210,8 @@ extern uint8_t *code_gen_ptr;
206 210 /* find a translation block in the translation cache. If not found,
207 211 return NULL and the pointer to the last element of the list in pptb */
208 212 static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
209   - unsigned long pc,
210   - unsigned long cs_base,
  213 + target_ulong pc,
  214 + target_ulong cs_base,
211 215 unsigned int flags)
212 216 {
213 217 TranslationBlock **ptb, *tb;
... ...
... ... @@ -64,7 +64,7 @@ uint8_t *phys_ram_base;
64 64 uint8_t *phys_ram_dirty;
65 65  
66 66 typedef struct PageDesc {
67   - /* offset in memory of the page + io_index in the low 12 bits */
  67 + /* offset in host memory of the page + io_index in the low 12 bits */
68 68 unsigned long phys_offset;
69 69 /* list of TBs intersecting this physical page */
70 70 TranslationBlock *first_tb;
... ... @@ -1011,7 +1011,7 @@ static void breakpoint_invalidate(CPUState *env, target_ulong pc)
1011 1011  
1012 1012 /* add a breakpoint. EXCP_DEBUG is returned by the CPU loop if a
1013 1013 breakpoint is reached */
1014   -int cpu_breakpoint_insert(CPUState *env, uint32_t pc)
  1014 +int cpu_breakpoint_insert(CPUState *env, target_ulong pc)
1015 1015 {
1016 1016 #if defined(TARGET_I386) || defined(TARGET_PPC)
1017 1017 int i;
... ... @@ -1033,7 +1033,7 @@ int cpu_breakpoint_insert(CPUState *env, uint32_t pc)
1033 1033 }
1034 1034  
1035 1035 /* remove a breakpoint */
1036   -int cpu_breakpoint_remove(CPUState *env, uint32_t pc)
  1036 +int cpu_breakpoint_remove(CPUState *env, target_ulong pc)
1037 1037 {
1038 1038 #if defined(TARGET_I386) || defined(TARGET_PPC)
1039 1039 int i;
... ... @@ -1221,7 +1221,7 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, uint32_t addr)
1221 1221 tlb_entry->address = -1;
1222 1222 }
1223 1223  
1224   -void tlb_flush_page(CPUState *env, uint32_t addr)
  1224 +void tlb_flush_page(CPUState *env, target_ulong addr)
1225 1225 {
1226 1226 int i, n;
1227 1227 VirtPageDesc *vp;
... ... @@ -1415,7 +1415,8 @@ static inline void tlb_set_dirty(unsigned long addr, target_ulong vaddr)
1415 1415 is permitted. Return 0 if OK or 2 if the page could not be mapped
1416 1416 (can only happen in non SOFTMMU mode for I/O pages or pages
1417 1417 conflicting with the host address space). */
1418   -int tlb_set_page(CPUState *env, uint32_t vaddr, uint32_t paddr, int prot,
  1418 +int tlb_set_page(CPUState *env, target_ulong vaddr,
  1419 + target_phys_addr_t paddr, int prot,
1419 1420 int is_user, int is_softmmu)
1420 1421 {
1421 1422 PageDesc *p;
... ... @@ -1583,15 +1584,12 @@ void tlb_flush(CPUState *env, int flush_global)
1583 1584 {
1584 1585 }
1585 1586  
1586   -void tlb_flush_page(CPUState *env, uint32_t addr)
  1587 +void tlb_flush_page(CPUState *env, target_ulong addr)
1587 1588 {
1588 1589 }
1589 1590  
1590   -void tlb_flush_page_write(CPUState *env, uint32_t addr)
1591   -{
1592   -}
1593   -
1594   -int tlb_set_page(CPUState *env, uint32_t vaddr, uint32_t paddr, int prot,
  1591 +int tlb_set_page(CPUState *env, target_ulong vaddr,
  1592 + target_phys_addr_t paddr, int prot,
1595 1593 int is_user, int is_softmmu)
1596 1594 {
1597 1595 return 0;
... ... @@ -1739,8 +1737,9 @@ static inline void tlb_set_dirty(unsigned long addr, target_ulong vaddr)
1739 1737 /* register physical memory. 'size' must be a multiple of the target
1740 1738 page size. If (phys_offset & ~TARGET_PAGE_MASK) != 0, then it is an
1741 1739 io memory page */
1742   -void cpu_register_physical_memory(unsigned long start_addr, unsigned long size,
1743   - long phys_offset)
  1740 +void cpu_register_physical_memory(target_phys_addr_t start_addr,
  1741 + unsigned long size,
  1742 + unsigned long phys_offset)
1744 1743 {
1745 1744 unsigned long addr, end_addr;
1746 1745 PageDesc *p;
... ... @@ -1754,12 +1753,12 @@ void cpu_register_physical_memory(unsigned long start_addr, unsigned long size,
1754 1753 }
1755 1754 }
1756 1755  
1757   -static uint32_t unassigned_mem_readb(uint32_t addr)
  1756 +static uint32_t unassigned_mem_readb(target_phys_addr_t addr)
1758 1757 {
1759 1758 return 0;
1760 1759 }
1761 1760  
1762   -static void unassigned_mem_writeb(uint32_t addr, uint32_t val)
  1761 +static void unassigned_mem_writeb(target_phys_addr_t addr, uint32_t val)
1763 1762 {
1764 1763 }
1765 1764  
... ... @@ -1778,7 +1777,7 @@ static CPUWriteMemoryFunc *unassigned_mem_write[3] = {
1778 1777 /* self modifying code support in soft mmu mode : writing to a page
1779 1778 containing code comes to these functions */
1780 1779  
1781   -static void code_mem_writeb(uint32_t addr, uint32_t val)
  1780 +static void code_mem_writeb(target_phys_addr_t addr, uint32_t val)
1782 1781 {
1783 1782 unsigned long phys_addr;
1784 1783  
... ... @@ -1790,7 +1789,7 @@ static void code_mem_writeb(uint32_t addr, uint32_t val)
1790 1789 phys_ram_dirty[phys_addr >> TARGET_PAGE_BITS] = 1;
1791 1790 }
1792 1791  
1793   -static void code_mem_writew(uint32_t addr, uint32_t val)
  1792 +static void code_mem_writew(target_phys_addr_t addr, uint32_t val)
1794 1793 {
1795 1794 unsigned long phys_addr;
1796 1795  
... ... @@ -1802,7 +1801,7 @@ static void code_mem_writew(uint32_t addr, uint32_t val)
1802 1801 phys_ram_dirty[phys_addr >> TARGET_PAGE_BITS] = 1;
1803 1802 }
1804 1803  
1805   -static void code_mem_writel(uint32_t addr, uint32_t val)
  1804 +static void code_mem_writel(target_phys_addr_t addr, uint32_t val)
1806 1805 {
1807 1806 unsigned long phys_addr;
1808 1807  
... ... @@ -1892,7 +1891,7 @@ int cpu_register_io_memory(int io_index,
1892 1891  
1893 1892 /* physical memory access (slow version, mainly for debug) */
1894 1893 #if defined(CONFIG_USER_ONLY)
1895   -void cpu_physical_memory_rw(target_ulong addr, uint8_t *buf,
  1894 +void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
1896 1895 int len, int is_write)
1897 1896 {
1898 1897 int l, flags;
... ... @@ -1921,13 +1920,14 @@ void cpu_physical_memory_rw(target_ulong addr, uint8_t *buf,
1921 1920 }
1922 1921 }
1923 1922 #else
1924   -void cpu_physical_memory_rw(target_ulong addr, uint8_t *buf,
  1923 +void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
1925 1924 int len, int is_write)
1926 1925 {
1927 1926 int l, io_index;
1928 1927 uint8_t *ptr;
1929 1928 uint32_t val;
1930   - target_ulong page, pd;
  1929 + target_phys_addr_t page;
  1930 + unsigned long pd;
1931 1931 PageDesc *p;
1932 1932  
1933 1933 while (len > 0) {
... ...
hw/ppc_prep.c
  View file @2e12669
... ... @@ -104,7 +104,7 @@ static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
104 104 /* IO ports emulation */
105 105 #define PPC_IO_BASE 0x80000000
106 106  
107   -static void PPC_io_writeb (uint32_t addr, uint32_t value, uint32_t vaddr)
  107 +static void PPC_io_writeb (target_phys_addr_t addr, uint32_t value)
108 108 {
109 109 /* Don't polute serial port output */
110 110 #if 0
... ... @@ -121,7 +121,7 @@ static void PPC_io_writeb (uint32_t addr, uint32_t value, uint32_t vaddr)
121 121 cpu_outb(NULL, addr - PPC_IO_BASE, value);
122 122 }
123 123  
124   -static uint32_t PPC_io_readb (uint32_t addr)
  124 +static uint32_t PPC_io_readb (target_phys_addr_t addr)
125 125 {
126 126 uint32_t ret = cpu_inb(NULL, addr - PPC_IO_BASE);
127 127  
... ... @@ -141,7 +141,7 @@ static uint32_t PPC_io_readb (uint32_t addr)
141 141 return ret;
142 142 }
143 143  
144   -static void PPC_io_writew (uint32_t addr, uint32_t value, uint32_t vaddr)
  144 +static void PPC_io_writew (target_phys_addr_t addr, uint32_t value)
145 145 {
146 146 if ((addr < 0x800001f0 || addr > 0x800001f7) &&
147 147 (addr < 0x80000170 || addr > 0x80000177)) {
... ... @@ -150,7 +150,7 @@ static void PPC_io_writew (uint32_t addr, uint32_t value, uint32_t vaddr)
150 150 cpu_outw(NULL, addr - PPC_IO_BASE, value);
151 151 }
152 152  
153   -static uint32_t PPC_io_readw (uint32_t addr)
  153 +static uint32_t PPC_io_readw (target_phys_addr_t addr)
154 154 {
155 155 uint32_t ret = cpu_inw(NULL, addr - PPC_IO_BASE);
156 156  
... ... @@ -162,13 +162,13 @@ static uint32_t PPC_io_readw (uint32_t addr)
162 162 return ret;
163 163 }
164 164  
165   -static void PPC_io_writel (uint32_t addr, uint32_t value, uint32_t vaddr)
  165 +static void PPC_io_writel (target_phys_addr_t addr, uint32_t value)
166 166 {
167 167 PPC_IO_DPRINTF("0x%08x => 0x%08x\n", addr - PPC_IO_BASE, value);
168 168 cpu_outl(NULL, addr - PPC_IO_BASE, value);
169 169 }
170 170  
171   -static uint32_t PPC_io_readl (uint32_t addr)
  171 +static uint32_t PPC_io_readl (target_phys_addr_t addr)
172 172 {
173 173 uint32_t ret = cpu_inl(NULL, addr - PPC_IO_BASE);
174 174  
... ... @@ -190,12 +190,12 @@ static CPUReadMemoryFunc *PPC_io_read[] = {
190 190 };
191 191  
192 192 /* Read-only register (?) */
193   -static void _PPC_ioB_write (uint32_t addr, uint32_t value, uint32_t vaddr)
  193 +static void _PPC_ioB_write (target_phys_addr_t addr, uint32_t value)
194 194 {
195 195 // printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
196 196 }
197 197  
198   -static uint32_t _PPC_ioB_read (uint32_t addr)
  198 +static uint32_t _PPC_ioB_read (target_phys_addr_t addr)
199 199 {
200 200 uint32_t retval = 0;
201 201  
... ... @@ -636,9 +636,9 @@ static void VGA_printf (uint8_t *s)
636 636 for (i = 0; i < format_width; i++) {
637 637 nibble = (arg >> (4 * digit)) & 0x000f;
638 638 if (nibble <= 9)
639   - PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + '0', 0);
  639 + PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + '0');
640 640 else
641   - PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + 'A', 0);
  641 + PPC_io_writeb(PPC_IO_BASE + 0x500, nibble + 'A');
642 642 digit--;
643 643 }
644 644 in_format = 0;
... ... @@ -647,7 +647,7 @@ static void VGA_printf (uint8_t *s)
647 647 // in_format = 0;
648 648 // }
649 649 } else {
650   - PPC_io_writeb(PPC_IO_BASE + 0x500, c, 0);
  650 + PPC_io_writeb(PPC_IO_BASE + 0x500, c);
651 651 }
652 652 s++;
653 653 }
... ... @@ -659,10 +659,10 @@ static void VGA_init (void)
659 659 printf("Init VGA...\n");
660 660 #if 1
661 661 /* switch to color mode and enable CPU access 480 lines */
662   - PPC_io_writeb(PPC_IO_BASE + 0x3C2, 0xC3, 0);
  662 + PPC_io_writeb(PPC_IO_BASE + 0x3C2, 0xC3);
663 663 /* more than 64k 3C4/04 */
664   - PPC_io_writeb(PPC_IO_BASE + 0x3C4, 0x04, 0);
665   - PPC_io_writeb(PPC_IO_BASE + 0x3C5, 0x02, 0);
  664 + PPC_io_writeb(PPC_IO_BASE + 0x3C4, 0x04);
  665 + PPC_io_writeb(PPC_IO_BASE + 0x3C5, 0x02);
666 666 #endif
667 667 VGA_printf("PPC VGA BIOS...\n");
668 668 }
... ... @@ -690,7 +690,7 @@ void PPC_init_hw (/*CPUPPCState *env,*/ uint32_t mem_size,
690 690 {
691 691 #if 1
692 692 uint32_t offset =
693   - *((uint32_t *)((uint32_t)phys_ram_base + kernel_addr));
  693 + *((uint32_t *)(phys_ram_base + kernel_addr));
694 694 #else
695 695 uint32_t offset = 12;
696 696 #endif
... ... @@ -816,7 +816,7 @@ void PPC_init_hw (/*CPUPPCState *env,*/ uint32_t mem_size,
816 816 {
817 817 #if 0
818 818 uint32_t offset =
819   - *((uint32_t *)((uint32_t)phys_ram_base + kernel_addr));
  819 + *((uint32_t *)(phys_ram_base + kernel_addr));
820 820 #else
821 821 uint32_t offset = 12;
822 822 #endif
... ...
hw/vga.c
  View file @2e12669
... ... @@ -648,7 +648,7 @@ static void vbe_ioport_write(void *opaque, uint32_t addr, uint32_t val)
648 648 #endif
649 649  
650 650 /* called for accesses between 0xa0000 and 0xc0000 */
651   -static uint32_t vga_mem_readb(uint32_t addr)
  651 +static uint32_t vga_mem_readb(target_phys_addr_t addr)
652 652 {
653 653 VGAState *s = &vga_state;
654 654 int memory_map_mode, plane;
... ... @@ -704,7 +704,7 @@ static uint32_t vga_mem_readb(uint32_t addr)
704 704 return ret;
705 705 }
706 706  
707   -static uint32_t vga_mem_readw(uint32_t addr)
  707 +static uint32_t vga_mem_readw(target_phys_addr_t addr)
708 708 {
709 709 uint32_t v;
710 710 v = vga_mem_readb(addr);
... ... @@ -712,7 +712,7 @@ static uint32_t vga_mem_readw(uint32_t addr)
712 712 return v;
713 713 }
714 714  
715   -static uint32_t vga_mem_readl(uint32_t addr)
  715 +static uint32_t vga_mem_readl(target_phys_addr_t addr)
716 716 {
717 717 uint32_t v;
718 718 v = vga_mem_readb(addr);
... ... @@ -723,7 +723,7 @@ static uint32_t vga_mem_readl(uint32_t addr)
723 723 }
724 724  
725 725 /* called for accesses between 0xa0000 and 0xc0000 */
726   -static void vga_mem_writeb(uint32_t addr, uint32_t val)
  726 +static void vga_mem_writeb(target_phys_addr_t addr, uint32_t val)
727 727 {
728 728 VGAState *s = &vga_state;
729 729 int memory_map_mode, plane, write_mode, b, func_select;
... ... @@ -851,13 +851,13 @@ static void vga_mem_writeb(uint32_t addr, uint32_t val)
851 851 }
852 852 }
853 853  
854   -static void vga_mem_writew(uint32_t addr, uint32_t val)
  854 +static void vga_mem_writew(target_phys_addr_t addr, uint32_t val)
855 855 {
856 856 vga_mem_writeb(addr, val & 0xff);
857 857 vga_mem_writeb(addr + 1, (val >> 8) & 0xff);
858 858 }
859 859  
860   -static void vga_mem_writel(uint32_t addr, uint32_t val)
  860 +static void vga_mem_writel(target_phys_addr_t addr, uint32_t val)
861 861 {
862 862 vga_mem_writeb(addr, val & 0xff);
863 863 vga_mem_writeb(addr + 1, (val >> 8) & 0xff);
... ...