Commit 9d42037b1d75c8f1b187d0b3187bd7891b909a56
1 parent
2a4188a3
support for dynamic address space changes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2021 c046a42c-6fe2-441c-8c8c-71466251a162
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exec.c
... | ... | @@ -1779,6 +1779,7 @@ void cpu_register_physical_memory(target_phys_addr_t start_addr, |
1779 | 1779 | { |
1780 | 1780 | target_phys_addr_t addr, end_addr; |
1781 | 1781 | PhysPageDesc *p; |
1782 | + CPUState *env; | |
1782 | 1783 | |
1783 | 1784 | size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
1784 | 1785 | end_addr = start_addr + size; |
... | ... | @@ -1789,6 +1790,13 @@ void cpu_register_physical_memory(target_phys_addr_t start_addr, |
1789 | 1790 | (phys_offset & IO_MEM_ROMD)) |
1790 | 1791 | phys_offset += TARGET_PAGE_SIZE; |
1791 | 1792 | } |
1793 | + | |
1794 | + /* since each CPU stores ram addresses in its TLB cache, we must | |
1795 | + reset the modified entries */ | |
1796 | + /* XXX: slow ! */ | |
1797 | + for(env = first_cpu; env != NULL; env = env->next_cpu) { | |
1798 | + tlb_flush(env, 1); | |
1799 | + } | |
1792 | 1800 | } |
1793 | 1801 | |
1794 | 1802 | static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr) | ... | ... |