gwj / at91sam9263 · Commits

Commit a4193c8a4bb36f64311d7d706e343ffabd9eb076

Authored by bellard
1 parent 170c6f87

support for opaque data on memory I/Os 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@874 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 7 changed files with 93 additions and 86 deletions
exec-all.h
  View file @a4193c8
... ... @@ -377,6 +377,7 @@ do {\
377 377  
378 378 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
379 379 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
  380 +extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
380 381  
381 382 #ifdef __powerpc__
382 383 static inline int testandset (int *p)
... ...
... ... @@ -117,6 +117,7 @@ static unsigned int virt_valid_tag;
117 117 /* io memory support */
118 118 CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
119 119 CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
  120 +void *io_mem_opaque[IO_MEM_NB_ENTRIES];
120 121 static int io_mem_nb;
121 122  
122 123 /* log support */
... ... @@ -711,10 +712,13 @@ static inline void tb_invalidate_phys_page_fast(target_ulong start, int len)
711 712 PageDesc *p;
712 713 int offset, b;
713 714 #if 0
714   - if (cpu_single_env->cr[0] & CR0_PE_MASK) {
715   - printf("modifying code at 0x%x size=%d EIP=%x\n",
716   - (vaddr & TARGET_PAGE_MASK) | (start & ~TARGET_PAGE_MASK), len,
717   - cpu_single_env->eip);
  715 + if (1) {
  716 + if (loglevel) {
  717 + fprintf(logfile, "modifying code at 0x%x size=%d EIP=%x PC=%08x\n",
  718 + cpu_single_env->mem_write_vaddr, len,
  719 + cpu_single_env->eip,
  720 + cpu_single_env->eip + (long)cpu_single_env->segs[R_CS].base);
  721 + }
718 722 }
719 723 #endif
720 724 p = page_find(start >> TARGET_PAGE_BITS);
... ... @@ -1799,12 +1803,12 @@ void cpu_register_physical_memory(target_phys_addr_t start_addr,
1799 1803 }
1800 1804 }
1801 1805  
1802   -static uint32_t unassigned_mem_readb(target_phys_addr_t addr)
  1806 +static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
1803 1807 {
1804 1808 return 0;
1805 1809 }
1806 1810  
1807   -static void unassigned_mem_writeb(target_phys_addr_t addr, uint32_t val)
  1811 +static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1808 1812 {
1809 1813 }
1810 1814  
... ... @@ -1823,7 +1827,7 @@ static CPUWriteMemoryFunc *unassigned_mem_write[3] = {
1823 1827 /* self modifying code support in soft mmu mode : writing to a page
1824 1828 containing code comes to these functions */
1825 1829  
1826   -static void code_mem_writeb(target_phys_addr_t addr, uint32_t val)
  1830 +static void code_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1827 1831 {
1828 1832 unsigned long phys_addr;
1829 1833  
... ... @@ -1835,7 +1839,7 @@ static void code_mem_writeb(target_phys_addr_t addr, uint32_t val)
1835 1839 phys_ram_dirty[phys_addr >> TARGET_PAGE_BITS] = 1;
1836 1840 }
1837 1841  
1838   -static void code_mem_writew(target_phys_addr_t addr, uint32_t val)
  1842 +static void code_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1839 1843 {
1840 1844 unsigned long phys_addr;
1841 1845  
... ... @@ -1847,7 +1851,7 @@ static void code_mem_writew(target_phys_addr_t addr, uint32_t val)
1847 1851 phys_ram_dirty[phys_addr >> TARGET_PAGE_BITS] = 1;
1848 1852 }
1849 1853  
1850   -static void code_mem_writel(target_phys_addr_t addr, uint32_t val)
  1854 +static void code_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1851 1855 {
1852 1856 unsigned long phys_addr;
1853 1857  
... ... @@ -1871,19 +1875,19 @@ static CPUWriteMemoryFunc *code_mem_write[3] = {
1871 1875 code_mem_writel,
1872 1876 };
1873 1877  
1874   -static void notdirty_mem_writeb(target_phys_addr_t addr, uint32_t val)
  1878 +static void notdirty_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1875 1879 {
1876 1880 stb_raw((uint8_t *)addr, val);
1877 1881 tlb_set_dirty(addr, cpu_single_env->mem_write_vaddr);
1878 1882 }
1879 1883  
1880   -static void notdirty_mem_writew(target_phys_addr_t addr, uint32_t val)
  1884 +static void notdirty_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1881 1885 {
1882 1886 stw_raw((uint8_t *)addr, val);
1883 1887 tlb_set_dirty(addr, cpu_single_env->mem_write_vaddr);
1884 1888 }
1885 1889  
1886   -static void notdirty_mem_writel(target_phys_addr_t addr, uint32_t val)
  1890 +static void notdirty_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1887 1891 {
1888 1892 stl_raw((uint8_t *)addr, val);
1889 1893 tlb_set_dirty(addr, cpu_single_env->mem_write_vaddr);
... ... @@ -1897,10 +1901,10 @@ static CPUWriteMemoryFunc *notdirty_mem_write[3] = {
1897 1901  
1898 1902 static void io_mem_init(void)
1899 1903 {
1900   - cpu_register_io_memory(IO_MEM_ROM >> IO_MEM_SHIFT, code_mem_read, unassigned_mem_write);
1901   - cpu_register_io_memory(IO_MEM_UNASSIGNED >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write);
1902   - cpu_register_io_memory(IO_MEM_CODE >> IO_MEM_SHIFT, code_mem_read, code_mem_write);
1903   - cpu_register_io_memory(IO_MEM_NOTDIRTY >> IO_MEM_SHIFT, code_mem_read, notdirty_mem_write);
  1904 + cpu_register_io_memory(IO_MEM_ROM >> IO_MEM_SHIFT, code_mem_read, unassigned_mem_write, NULL);
  1905 + cpu_register_io_memory(IO_MEM_UNASSIGNED >> IO_MEM_SHIFT, unassigned_mem_read, unassigned_mem_write, NULL);
  1906 + cpu_register_io_memory(IO_MEM_CODE >> IO_MEM_SHIFT, code_mem_read, code_mem_write, NULL);
  1907 + cpu_register_io_memory(IO_MEM_NOTDIRTY >> IO_MEM_SHIFT, code_mem_read, notdirty_mem_write, NULL);
1904 1908 io_mem_nb = 5;
1905 1909  
1906 1910 /* alloc dirty bits array */
... ... @@ -1915,7 +1919,8 @@ static void io_mem_init(void)
1915 1919 cpu_register_physical_memory(). (-1) is returned if error. */
1916 1920 int cpu_register_io_memory(int io_index,
1917 1921 CPUReadMemoryFunc **mem_read,
1918   - CPUWriteMemoryFunc **mem_write)
  1922 + CPUWriteMemoryFunc **mem_write,
  1923 + void *opaque)
1919 1924 {
1920 1925 int i;
1921 1926  
... ... @@ -1932,6 +1937,7 @@ int cpu_register_io_memory(int io_index,
1932 1937 io_mem_read[io_index][i] = mem_read[i];
1933 1938 io_mem_write[io_index][i] = mem_write[i];
1934 1939 }
  1940 + io_mem_opaque[io_index] = opaque;
1935 1941 return io_index << IO_MEM_SHIFT;
1936 1942 }
1937 1943  
... ... @@ -1994,17 +2000,17 @@ void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
1994 2000 if (l >= 4 && ((addr & 3) == 0)) {
1995 2001 /* 32 bit read access */
1996 2002 val = ldl_raw(buf);
1997   - io_mem_write[io_index][2](addr, val);
  2003 + io_mem_write[io_index][2](io_mem_opaque[io_index], addr, val);
1998 2004 l = 4;
1999 2005 } else if (l >= 2 && ((addr & 1) == 0)) {
2000 2006 /* 16 bit read access */
2001 2007 val = lduw_raw(buf);
2002   - io_mem_write[io_index][1](addr, val);
  2008 + io_mem_write[io_index][1](io_mem_opaque[io_index], addr, val);
2003 2009 l = 2;
2004 2010 } else {
2005 2011 /* 8 bit access */
2006 2012 val = ldub_raw(buf);
2007   - io_mem_write[io_index][0](addr, val);
  2013 + io_mem_write[io_index][0](io_mem_opaque[io_index], addr, val);
2008 2014 l = 1;
2009 2015 }
2010 2016 } else {
... ... @@ -2025,17 +2031,17 @@ void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
2025 2031 io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
2026 2032 if (l >= 4 && ((addr & 3) == 0)) {
2027 2033 /* 32 bit read access */
2028   - val = io_mem_read[io_index][2](addr);
  2034 + val = io_mem_read[io_index][2](io_mem_opaque[io_index], addr);
2029 2035 stl_raw(buf, val);
2030 2036 l = 4;
2031 2037 } else if (l >= 2 && ((addr & 1) == 0)) {
2032 2038 /* 16 bit read access */
2033   - val = io_mem_read[io_index][1](addr);
  2039 + val = io_mem_read[io_index][1](io_mem_opaque[io_index], addr);
2034 2040 stw_raw(buf, val);
2035 2041 l = 2;
2036 2042 } else {
2037 2043 /* 8 bit access */
2038   - val = io_mem_read[io_index][0](addr);
  2044 + val = io_mem_read[io_index][0](io_mem_opaque[io_index], addr);
2039 2045 stb_raw(buf, val);
2040 2046 l = 1;
2041 2047 }
... ...
hw/ppc.c
  View file @a4193c8
... ... @@ -197,18 +197,18 @@ void cpu_ppc_reset (CPUState *env)
197 197 }
198 198 #endif
199 199  
200   -static void PPC_io_writeb (target_phys_addr_t addr, uint32_t value)
  200 +static void PPC_io_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
201 201 {
202 202 cpu_outb(NULL, addr & 0xffff, value);
203 203 }
204 204  
205   -static uint32_t PPC_io_readb (target_phys_addr_t addr)
  205 +static uint32_t PPC_io_readb (void *opaque, target_phys_addr_t addr)
206 206 {
207 207 uint32_t ret = cpu_inb(NULL, addr & 0xffff);
208 208 return ret;
209 209 }
210 210  
211   -static void PPC_io_writew (target_phys_addr_t addr, uint32_t value)
  211 +static void PPC_io_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
212 212 {
213 213 #ifdef TARGET_WORDS_BIGENDIAN
214 214 value = bswap16(value);
... ... @@ -216,7 +216,7 @@ static void PPC_io_writew (target_phys_addr_t addr, uint32_t value)
216 216 cpu_outw(NULL, addr & 0xffff, value);
217 217 }
218 218  
219   -static uint32_t PPC_io_readw (target_phys_addr_t addr)
  219 +static uint32_t PPC_io_readw (void *opaque, target_phys_addr_t addr)
220 220 {
221 221 uint32_t ret = cpu_inw(NULL, addr & 0xffff);
222 222 #ifdef TARGET_WORDS_BIGENDIAN
... ... @@ -225,7 +225,7 @@ static uint32_t PPC_io_readw (target_phys_addr_t addr)
225 225 return ret;
226 226 }
227 227  
228   -static void PPC_io_writel (target_phys_addr_t addr, uint32_t value)
  228 +static void PPC_io_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
229 229 {
230 230 #ifdef TARGET_WORDS_BIGENDIAN
231 231 value = bswap32(value);
... ... @@ -233,7 +233,7 @@ static void PPC_io_writel (target_phys_addr_t addr, uint32_t value)
233 233 cpu_outl(NULL, addr & 0xffff, value);
234 234 }
235 235  
236   -static uint32_t PPC_io_readl (target_phys_addr_t addr)
  236 +static uint32_t PPC_io_readl (void *opaque, target_phys_addr_t addr)
237 237 {
238 238 uint32_t ret = cpu_inl(NULL, addr & 0xffff);
239 239  
... ...
hw/ppc_chrp.c
  View file @a4193c8
... ... @@ -64,7 +64,7 @@ void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
64 64 pci_pmac_init();
65 65  
66 66 /* Register 64 KB of ISA IO space */
67   - PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write);
  67 + PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
68 68 cpu_register_physical_memory(0x80000000, 0x10000, PPC_io_memory);
69 69 // cpu_register_physical_memory(0xfe000000, 0xfe010000, PPC_io_memory);
70 70  
... ...
hw/ppc_prep.c
  View file @a4193c8
... ... @@ -98,7 +98,7 @@ static uint32_t speaker_ioport_read(void *opaque, uint32_t addr)
98 98  
99 99 /* PCI intack register */
100 100 /* Read-only register (?) */
101   -static void _PPC_intack_write (target_phys_addr_t addr, uint32_t value)
  101 +static void _PPC_intack_write (void *opaque, target_phys_addr_t addr, uint32_t value)
102 102 {
103 103 // printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
104 104 }
... ... @@ -114,12 +114,12 @@ static inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
114 114 return retval;
115 115 }
116 116  
117   -static uint32_t PPC_intack_readb (target_phys_addr_t addr)
  117 +static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
118 118 {
119 119 return _PPC_intack_read(addr);
120 120 }
121 121  
122   -static uint32_t PPC_intack_readw (target_phys_addr_t addr)
  122 +static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
123 123 {
124 124 #ifdef TARGET_WORDS_BIGENDIAN
125 125 return bswap16(_PPC_intack_read(addr));
... ... @@ -128,7 +128,7 @@ static uint32_t PPC_intack_readw (target_phys_addr_t addr)
128 128 #endif
129 129 }
130 130  
131   -static uint32_t PPC_intack_readl (target_phys_addr_t addr)
  131 +static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
132 132 {
133 133 #ifdef TARGET_WORDS_BIGENDIAN
134 134 return bswap32(_PPC_intack_read(addr));
... ... @@ -177,12 +177,12 @@ static struct {
177 177 } XCSR;
178 178 #endif
179 179  
180   -static void PPC_XCSR_writeb (target_phys_addr_t addr, uint32_t value)
  180 +static void PPC_XCSR_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
181 181 {
182 182 printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
183 183 }
184 184  
185   -static void PPC_XCSR_writew (target_phys_addr_t addr, uint32_t value)
  185 +static void PPC_XCSR_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
186 186 {
187 187 #ifdef TARGET_WORDS_BIGENDIAN
188 188 value = bswap16(value);
... ... @@ -190,7 +190,7 @@ static void PPC_XCSR_writew (target_phys_addr_t addr, uint32_t value)
190 190 printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
191 191 }
192 192  
193   -static void PPC_XCSR_writel (target_phys_addr_t addr, uint32_t value)
  193 +static void PPC_XCSR_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
194 194 {
195 195 #ifdef TARGET_WORDS_BIGENDIAN
196 196 value = bswap32(value);
... ... @@ -198,7 +198,7 @@ static void PPC_XCSR_writel (target_phys_addr_t addr, uint32_t value)
198 198 printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
199 199 }
200 200  
201   -static uint32_t PPC_XCSR_readb (target_phys_addr_t addr)
  201 +static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
202 202 {
203 203 uint32_t retval = 0;
204 204  
... ... @@ -207,7 +207,7 @@ static uint32_t PPC_XCSR_readb (target_phys_addr_t addr)
207 207 return retval;
208 208 }
209 209  
210   -static uint32_t PPC_XCSR_readw (target_phys_addr_t addr)
  210 +static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
211 211 {
212 212 uint32_t retval = 0;
213 213  
... ... @@ -219,7 +219,7 @@ static uint32_t PPC_XCSR_readw (target_phys_addr_t addr)
219 219 return retval;
220 220 }
221 221  
222   -static uint32_t PPC_XCSR_readl (target_phys_addr_t addr)
  222 +static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
223 223 {
224 224 uint32_t retval = 0;
225 225  
... ... @@ -480,7 +480,7 @@ void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device,
480 480 isa_mem_base = 0xc0000000;
481 481 pci_prep_init();
482 482 /* Register 64 KB of ISA IO space */
483   - PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write);
  483 + PPC_io_memory = cpu_register_io_memory(0, PPC_io_read, PPC_io_write, NULL);
484 484 cpu_register_physical_memory(0x80000000, 0x00010000, PPC_io_memory);
485 485  
486 486 /* init basic PC hardware */
... ... @@ -525,10 +525,10 @@ void ppc_prep_init(int ram_size, int vga_ram_size, int boot_device,
525 525 register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
526 526 /* PCI intack location */
527 527 PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
528   - PPC_intack_write);
  528 + PPC_intack_write, NULL);
529 529 cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
530 530 /* PowerPC control and status register group */
531   - PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write);
  531 + PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write, NULL);
532 532 cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
533 533  
534 534 nvram = m48t59_init(8, 0x0074, NVRAM_SIZE);
... ...
hw/vga.c
  View file @a4193c8
... ... @@ -656,9 +656,9 @@ static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
656 656 #endif
657 657  
658 658 /* called for accesses between 0xa0000 and 0xc0000 */
659   -static uint32_t vga_mem_readb(target_phys_addr_t addr)
  659 +static uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
660 660 {
661   - VGAState *s = &vga_state;
  661 + VGAState *s = opaque;
662 662 int memory_map_mode, plane;
663 663 uint32_t ret;
664 664  
... ... @@ -712,40 +712,40 @@ static uint32_t vga_mem_readb(target_phys_addr_t addr)
712 712 return ret;
713 713 }
714 714  
715   -static uint32_t vga_mem_readw(target_phys_addr_t addr)
  715 +static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
716 716 {
717 717 uint32_t v;
718 718 #ifdef TARGET_WORDS_BIGENDIAN
719   - v = vga_mem_readb(addr) << 8;
720   - v |= vga_mem_readb(addr + 1);
  719 + v = vga_mem_readb(opaque, addr) << 8;
  720 + v |= vga_mem_readb(opaque, addr + 1);
721 721 #else
722   - v = vga_mem_readb(addr);
723   - v |= vga_mem_readb(addr + 1) << 8;
  722 + v = vga_mem_readb(opaque, addr);
  723 + v |= vga_mem_readb(opaque, addr + 1) << 8;
724 724 #endif
725 725 return v;
726 726 }
727 727  
728   -static uint32_t vga_mem_readl(target_phys_addr_t addr)
  728 +static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
729 729 {
730 730 uint32_t v;
731 731 #ifdef TARGET_WORDS_BIGENDIAN
732   - v = vga_mem_readb(addr) << 24;
733   - v |= vga_mem_readb(addr + 1) << 16;
734   - v |= vga_mem_readb(addr + 2) << 8;
735   - v |= vga_mem_readb(addr + 3);
  732 + v = vga_mem_readb(opaque, addr) << 24;
  733 + v |= vga_mem_readb(opaque, addr + 1) << 16;
  734 + v |= vga_mem_readb(opaque, addr + 2) << 8;
  735 + v |= vga_mem_readb(opaque, addr + 3);
736 736 #else
737   - v = vga_mem_readb(addr);
738   - v |= vga_mem_readb(addr + 1) << 8;
739   - v |= vga_mem_readb(addr + 2) << 16;
740   - v |= vga_mem_readb(addr + 3) << 24;
  737 + v = vga_mem_readb(opaque, addr);
  738 + v |= vga_mem_readb(opaque, addr + 1) << 8;
  739 + v |= vga_mem_readb(opaque, addr + 2) << 16;
  740 + v |= vga_mem_readb(opaque, addr + 3) << 24;
741 741 #endif
742 742 return v;
743 743 }
744 744  
745 745 /* called for accesses between 0xa0000 and 0xc0000 */
746   -static void vga_mem_writeb(target_phys_addr_t addr, uint32_t val)
  746 +static void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
747 747 {
748   - VGAState *s = &vga_state;
  748 + VGAState *s = opaque;
749 749 int memory_map_mode, plane, write_mode, b, func_select;
750 750 uint32_t write_mask, bit_mask, set_mask;
751 751  
... ... @@ -871,29 +871,29 @@ static void vga_mem_writeb(target_phys_addr_t addr, uint32_t val)
871 871 }
872 872 }
873 873  
874   -static void vga_mem_writew(target_phys_addr_t addr, uint32_t val)
  874 +static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
875 875 {
876 876 #ifdef TARGET_WORDS_BIGENDIAN
877   - vga_mem_writeb(addr, (val >> 8) & 0xff);
878   - vga_mem_writeb(addr + 1, val & 0xff);
  877 + vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
  878 + vga_mem_writeb(opaque, addr + 1, val & 0xff);
879 879 #else
880   - vga_mem_writeb(addr, val & 0xff);
881   - vga_mem_writeb(addr + 1, (val >> 8) & 0xff);
  880 + vga_mem_writeb(opaque, addr, val & 0xff);
  881 + vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
882 882 #endif
883 883 }
884 884  
885   -static void vga_mem_writel(target_phys_addr_t addr, uint32_t val)
  885 +static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
886 886 {
887 887 #ifdef TARGET_WORDS_BIGENDIAN
888   - vga_mem_writeb(addr, (val >> 24) & 0xff);
889   - vga_mem_writeb(addr + 1, (val >> 16) & 0xff);
890   - vga_mem_writeb(addr + 2, (val >> 8) & 0xff);
891   - vga_mem_writeb(addr + 3, val & 0xff);
  888 + vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
  889 + vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
  890 + vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
  891 + vga_mem_writeb(opaque, addr + 3, val & 0xff);
892 892 #else
893   - vga_mem_writeb(addr, val & 0xff);
894   - vga_mem_writeb(addr + 1, (val >> 8) & 0xff);
895   - vga_mem_writeb(addr + 2, (val >> 16) & 0xff);
896   - vga_mem_writeb(addr + 3, (val >> 24) & 0xff);
  893 + vga_mem_writeb(opaque, addr, val & 0xff);
  894 + vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
  895 + vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
  896 + vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
897 897 #endif
898 898 }
899 899  
... ... @@ -1826,7 +1826,7 @@ int vga_initialize(DisplayState *ds, uint8_t *vga_ram_base,
1826 1826 #endif
1827 1827 #endif /* CONFIG_BOCHS_VBE */
1828 1828  
1829   - vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write);
  1829 + vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
1830 1830 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
1831 1831 vga_io_memory);
1832 1832  
... ...
softmmu_template.h
  View file @a4193c8
... ... @@ -55,14 +55,14 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(unsigned long physaddr,
55 55  
56 56 index = (tlb_addr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
57 57 #if SHIFT <= 2
58   - res = io_mem_read[index][SHIFT](physaddr);
  58 + res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
59 59 #else
60 60 #ifdef TARGET_WORDS_BIGENDIAN
61   - res = (uint64_t)io_mem_read[index][2](physaddr) << 32;
62   - res |= io_mem_read[index][2](physaddr + 4);
  61 + res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
  62 + res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
63 63 #else
64   - res = io_mem_read[index][2](physaddr);
65   - res |= (uint64_t)io_mem_read[index][2](physaddr + 4) << 32;
  64 + res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
  65 + res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
66 66 #endif
67 67 #endif /* SHIFT > 2 */
68 68 return res;
... ... @@ -79,14 +79,14 @@ static inline void glue(io_write, SUFFIX)(unsigned long physaddr,
79 79 env->mem_write_vaddr = tlb_addr;
80 80 env->mem_write_pc = (unsigned long)retaddr;
81 81 #if SHIFT <= 2
82   - io_mem_write[index][SHIFT](physaddr, val);
  82 + io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
83 83 #else
84 84 #ifdef TARGET_WORDS_BIGENDIAN
85   - io_mem_write[index][2](physaddr, val >> 32);
86   - io_mem_write[index][2](physaddr + 4, val);
  85 + io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
  86 + io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
87 87 #else
88   - io_mem_write[index][2](physaddr, val);
89   - io_mem_write[index][2](physaddr + 4, val >> 32);
  88 + io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
  89 + io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
90 90 #endif
91 91 #endif /* SHIFT > 2 */
92 92 }
... ...