gwj / at91sam9263 · Commits

  • gdb-xml: fix hacks in powerpc register numbering ...
    22555301 
    The powerpc xml files contained a hack--an empty, non-existent
register--for getting the register numbers to line up for
newer (XML-aware) and older (non-XML-aware) GDB.  While this hack worked
in some cases, it didn't work in all cases, notably when the user used
`finish' or `continue': GDB would attempt to read the non-existent
register and QEMU would complain.

This patch fixes things up properly.  Instead of inserting a fake
register, we explicitly declare the floating-point and SPE registers to
start at 71.  This action accomplishes the same thing as the nasty hack,
except that now GDB never tries to fetch the non-existant register 70.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
    Nathan Froyd authored
     
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  • target-ppc: fix evmergelo and evmergelohi ...
    33890b3e 
    For 32-bit PPC targets, we translated:

evmergelo rX, rX, rY

as:

rX-lo = rY-lo
rX-hi = rX-lo

which is wrong, because we should be transferring rX-lo first.  This
problem is fixed by swapping the order in which we write the parts of
rX.

Similarly, we translated:

evmergelohi rX, rX, rY

as:

rX-lo = rY-hi
rX-hi = rX-lo

In this case, we can't swap the assignment statements, because that
would just cause problems for:

evmergelohi rX, rY, rX

Instead, we detect the first case and save rX-lo in a temporary
variable:

tmp = rX-lo
rX-lo = rY-hi
rX-hi = tmp

These problems don't occur on PPC64 targets because we don't split the
SPE registers into hi/lo parts for such targets.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
    Nathan Froyd authored
     
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  • target-ppc: fix typo in _cpu_ppc_load_decr ...
    f55e9d9a 
    Use parameter 'next' to fix the hdecr case.
Also pass 'next' by value instead of pointer (more easy to read and no
performance issue for an always_inline function).

Signed-off-by: Tristan Gingold <gingold@adacore.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
    Tristan Gingold authored
     
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  • Sparc32/Sparc64/PPC: convert m48txx to qdev ...
    d27cf0ae 
    Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
    Blue Swirl authored
     
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  • Sparc32: convert tcx to qdev ...
    f40070c3 
    Also increase QDEV_MAX_MMIO.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
    Blue Swirl authored
     
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  • Sparc32: use the OpenFirmware name for ecc ...
    798b721e 
    Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
    Blue Swirl authored
     
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  • target-mips: remove useless code in gen_st_cond() ...
    344b983d 
    Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
    Aurelien Jarno authored
     
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  • Fix MIPS SC ...
    feeb3b6a 
    Fix botched merge of op_ldst_sc calls to match actual implementation.
Thanks to Aurelien Jarno for diagnosing this.

Signed-off-by: Paul Brook <paul@codesourcery.com>
    Paul Brook authored
     
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  • Sparc64: convert ebus to qdev ...
    53e3c4f9 
    Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
    Blue Swirl authored
     
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  • sparc64: trap handling corrections ...
    5210977a 
    On Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl<blauwirbel@gmail.com> wrote:
> On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote:
>> Good trap handling is required to process interrupts.
>>  This patch fixes the following:
>>
>>  - sparc64 has no wim register
>>  - sparc64 has no psret register, use IE bit of pstate
>>   extract IE checking code to cpu_interrupts_enabled
>>  - alternate globals are not available if cpu has GL feature
>>   in this case bit AG of pstate is constant zero
>>  - write to pstate must actually write pstate
>>   even if cpu has GL feature
>>
>>  Also timer interrupt is handled using do_interrupt.
>
> A bit too much for one patch. Please also remove the code instead of
> commenting out.

I now excluded timer interrupt related part.
To my mind other changes are essentially tied together.

> PUT_PSR for Sparc64 needs CC_OP = CC_OP_FLAGS; like Sparc32.

Fixed, please find attached the updated version.

--
Kind regards,
Igor V. Kovalenko
    Igor Kovalenko authored
     
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  • Sparc32: convert eccmemctl to qdev ...
    49e66373 
    Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
    Blue Swirl authored
     
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  • sparc64: fix helper_st_asi little endian case typo ...
    5b0f0bec 
    On Sun, Jul 12, 2009 at 12:43 AM, Stuart Brady<sdbrady@ntlworld.com> wrote:
> On Sat, Jul 11, 2009 at 10:22:18PM +0400, Igor Kovalenko wrote:
>> It is clear that intention is to byte-swap value to be written, not
>> the target address.
>
> @@ -1949,13 +1949,13 @@ void helper_st_asi(target_ulong addr, ta
>     case 0x89: // Secondary LE
>         switch(size) {
>         case 2:
> -            addr = bswap16(addr);
> +            addr = bswap16(val);
>             ^^^^
> Shouldn't that be 'val = bswap16(val)' (and likewise for the 32-bit and
> 64-bit cases)?  Also needs a 'signed-off-by:'...
>
> Cheers,
> --
> Stuart Brady
>

Thanks, that part I did not runtime-tested.
Not sure if those asi stores are of any use for user-mode emulator.

Please find attached the corrected version.

Signed-off-by: igor.v.kovalenko@gmail.com

--
Kind regards,
Igor V. Kovalenko
    Igor Kovalenko authored
     
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  • sparc64: really initialize irq ...
    7d55273f 
    Allocate irq just before passing it to pci bridge initialization
and actually use it to initialize pci bridge.

Signed-off-by: igor.v.kovalenko@gmail.com

--
Kind regards,
Igor V. Kovalenko
    Igor Kovalenko authored
     
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  • sparc64: unify mmu tag matching code ...
    536ba015 
    This patch extracts common part of sparc64 tag
matching code used by IMMU and DMMU lookups.

Signed-off-by: igor.v.kovalenko@gmail.com

--
Kind regards,
Igor V. Kovalenko
    Igor Kovalenko authored
     
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  • sparc64: mmu bypass mode correction ...
    e8807b14 
    This Implement physical address truncation in mmu bypass mode.
IMMU bypass is also active when cpu enters RED_STATE

Signed-off-by: igor.v.kovalenko@gmail.com

--
Kind regards,
Igor V. Kovalenko
    Igor Kovalenko authored
     
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