gwj / at91sam9263 · Commits

Commit 33890b3e0deb8891d5b1241671eb3979f8896bf3

Authored by Nathan Froyd
Committed by Aurelien Jarno
1 parent f55e9d9a

target-ppc: fix evmergelo and evmergelohi 

For 32-bit PPC targets, we translated:

evmergelo rX, rX, rY

as:

rX-lo = rY-lo
rX-hi = rX-lo

which is wrong, because we should be transferring rX-lo first.  This
problem is fixed by swapping the order in which we write the parts of
rX.

Similarly, we translated:

evmergelohi rX, rX, rY

as:

rX-lo = rY-hi
rX-hi = rX-lo

In this case, we can't swap the assignment statements, because that
would just cause problems for:

evmergelohi rX, rY, rX

Instead, we detect the first case and save rX-lo in a temporary
variable:

tmp = rX-lo
rX-lo = rY-hi
rX-hi = tmp

These problems don't occur on PPC64 targets because we don't split the
SPE registers into hi/lo parts for such targets.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Inline Side-by-side
Showing 1 changed file with 11 additions and 3 deletions
target-ppc/translate.c
  View file @33890b3
... ... @@ -6908,8 +6908,8 @@ static always_inline void gen_evmergelo (DisasContext *ctx)
6908 6908 tcg_temp_free(t0);
6909 6909 tcg_temp_free(t1);
6910 6910 #else
6911   - tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6912 6911 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
  6912 + tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
6913 6913 #endif
6914 6914 }
6915 6915 static always_inline void gen_evmergehilo (DisasContext *ctx)
... ... @@ -6946,8 +6946,16 @@ static always_inline void gen_evmergelohi (DisasContext *ctx)
6946 6946 tcg_temp_free(t0);
6947 6947 tcg_temp_free(t1);
6948 6948 #else
6949   - tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
6950   - tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
  6949 + if (rD(ctx->opcode) == rA(ctx->opcode)) {
  6950 + TCGv_i32 tmp = tcg_temp_new_i32();
  6951 + tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
  6952 + tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
  6953 + tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
  6954 + tcg_temp_free_i32(tmp);
  6955 + } else {
  6956 + tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
  6957 + tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
  6958 + }
6951 6959 #endif
6952 6960 }
6953 6961 static always_inline void gen_evsplati (DisasContext *ctx)
... ...