Blame view

cpu-all.h 28.5 KB
bellard authored
1
2
/*
 * defines common to all virtual CPUs
3
 *
bellard authored
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#ifndef CPU_ALL_H
#define CPU_ALL_H
aurel32 authored
23
#if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__)
bellard authored
24
25
26
#define WORDS_ALIGNED
#endif
27
28
/* some important defines:
 *
bellard authored
29
30
 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
 * memory accesses.
31
 *
bellard authored
32
33
 * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
 * otherwise little endian.
34
 *
bellard authored
35
 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
36
 *
bellard authored
37
38
39
 * TARGET_WORDS_BIGENDIAN : same for target cpu
 */
40
#include "bswap.h"
41
#include "softfloat.h"
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112

#if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
#define BSWAP_NEEDED
#endif

#ifdef BSWAP_NEEDED

static inline uint16_t tswap16(uint16_t s)
{
    return bswap16(s);
}

static inline uint32_t tswap32(uint32_t s)
{
    return bswap32(s);
}

static inline uint64_t tswap64(uint64_t s)
{
    return bswap64(s);
}

static inline void tswap16s(uint16_t *s)
{
    *s = bswap16(*s);
}

static inline void tswap32s(uint32_t *s)
{
    *s = bswap32(*s);
}

static inline void tswap64s(uint64_t *s)
{
    *s = bswap64(*s);
}

#else

static inline uint16_t tswap16(uint16_t s)
{
    return s;
}

static inline uint32_t tswap32(uint32_t s)
{
    return s;
}

static inline uint64_t tswap64(uint64_t s)
{
    return s;
}

static inline void tswap16s(uint16_t *s)
{
}

static inline void tswap32s(uint32_t *s)
{
}

static inline void tswap64s(uint64_t *s)
{
}

#endif

#if TARGET_LONG_SIZE == 4
#define tswapl(s) tswap32(s)
#define tswapls(s) tswap32s((uint32_t *)(s))
bellard authored
113
#define bswaptls(s) bswap32s(s)
114
115
116
#else
#define tswapl(s) tswap64(s)
#define tswapls(s) tswap64s((uint64_t *)(s))
bellard authored
117
#define bswaptls(s) bswap64s(s)
118
119
#endif
120
121
122
123
124
typedef union {
    float32 f;
    uint32_t l;
} CPU_FloatU;
bellard authored
125
126
/* NOTE: arm FPA is horrible as double 32 bit words are stored in big
   endian ! */
bellard authored
127
typedef union {
bellard authored
128
    float64 d;
129
130
#if defined(WORDS_BIGENDIAN) \
    || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
bellard authored
131
132
    struct {
        uint32_t upper;
bellard authored
133
        uint32_t lower;
bellard authored
134
135
136
137
    } l;
#else
    struct {
        uint32_t lower;
bellard authored
138
        uint32_t upper;
bellard authored
139
140
141
142
143
    } l;
#endif
    uint64_t ll;
} CPU_DoubleU;
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
#ifdef TARGET_SPARC
typedef union {
    float128 q;
#if defined(WORDS_BIGENDIAN) \
    || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
    struct {
        uint32_t upmost;
        uint32_t upper;
        uint32_t lower;
        uint32_t lowest;
    } l;
    struct {
        uint64_t upper;
        uint64_t lower;
    } ll;
#else
    struct {
        uint32_t lowest;
        uint32_t lower;
        uint32_t upper;
        uint32_t upmost;
    } l;
    struct {
        uint64_t lower;
        uint64_t upper;
    } ll;
#endif
} CPU_QuadU;
#endif
bellard authored
174
175
/* CPU memory access without any memory or io remapping */
176
177
178
179
180
181
182
183
184
185
/*
 * the generic syntax for the memory accesses is:
 *
 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
 *
 * store: st{type}{size}{endian}_{access_type}(ptr, val)
 *
 * type is:
 * (empty): integer access
 *   f    : float access
186
 *
187
188
189
190
191
192
193
194
195
196
 * sign is:
 * (empty): for floats or 32 bit size
 *   u    : unsigned
 *   s    : signed
 *
 * size is:
 *   b: 8 bits
 *   w: 16 bits
 *   l: 32 bits
 *   q: 64 bits
197
 *
198
199
200
201
202
203
204
205
206
207
208
 * endian is:
 * (empty): target cpu endianness or 8 bit access
 *   r    : reversed target cpu endianness (not implemented yet)
 *   be   : big endian (not implemented yet)
 *   le   : little endian (not implemented yet)
 *
 * access_type is:
 *   raw    : host memory access
 *   user   : user mode access using soft MMU
 *   kernel : kernel mode access using soft MMU
 */
209
static inline int ldub_p(const void *ptr)
bellard authored
210
211
212
213
{
    return *(uint8_t *)ptr;
}
214
static inline int ldsb_p(const void *ptr)
bellard authored
215
216
217
218
{
    return *(int8_t *)ptr;
}
bellard authored
219
static inline void stb_p(void *ptr, int v)
bellard authored
220
221
222
223
224
225
226
{
    *(uint8_t *)ptr = v;
}

/* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
   kernel handles unaligned load/stores may give better results, but
   it is a system wide setting : bad */
227
#if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
bellard authored
228
229

/* conservative code for little endian unaligned accesses */
230
static inline int lduw_le_p(const void *ptr)
bellard authored
231
232
233
234
235
236
{
#ifdef __powerpc__
    int val;
    __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
    return val;
#else
237
    const uint8_t *p = ptr;
bellard authored
238
239
240
241
    return p[0] | (p[1] << 8);
#endif
}
242
static inline int ldsw_le_p(const void *ptr)
bellard authored
243
244
245
246
247
248
{
#ifdef __powerpc__
    int val;
    __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
    return (int16_t)val;
#else
249
    const uint8_t *p = ptr;
bellard authored
250
251
252
253
    return (int16_t)(p[0] | (p[1] << 8));
#endif
}
254
static inline int ldl_le_p(const void *ptr)
bellard authored
255
256
257
258
259
260
{
#ifdef __powerpc__
    int val;
    __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
    return val;
#else
261
    const uint8_t *p = ptr;
bellard authored
262
263
264
265
    return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
#endif
}
266
static inline uint64_t ldq_le_p(const void *ptr)
bellard authored
267
{
268
    const uint8_t *p = ptr;
bellard authored
269
    uint32_t v1, v2;
270
271
    v1 = ldl_le_p(p);
    v2 = ldl_le_p(p + 4);
bellard authored
272
273
274
    return v1 | ((uint64_t)v2 << 32);
}
275
static inline void stw_le_p(void *ptr, int v)
bellard authored
276
277
278
279
280
281
282
283
284
285
{
#ifdef __powerpc__
    __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
#else
    uint8_t *p = ptr;
    p[0] = v;
    p[1] = v >> 8;
#endif
}
286
static inline void stl_le_p(void *ptr, int v)
bellard authored
287
288
289
290
291
292
293
294
295
296
297
298
{
#ifdef __powerpc__
    __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
#else
    uint8_t *p = ptr;
    p[0] = v;
    p[1] = v >> 8;
    p[2] = v >> 16;
    p[3] = v >> 24;
#endif
}
299
static inline void stq_le_p(void *ptr, uint64_t v)
bellard authored
300
301
{
    uint8_t *p = ptr;
302
303
    stl_le_p(p, (uint32_t)v);
    stl_le_p(p + 4, v >> 32);
bellard authored
304
305
306
307
}

/* float access */
308
static inline float32 ldfl_le_p(const void *ptr)
bellard authored
309
310
{
    union {
bellard authored
311
        float32 f;
bellard authored
312
313
        uint32_t i;
    } u;
314
    u.i = ldl_le_p(ptr);
bellard authored
315
316
317
    return u.f;
}
318
static inline void stfl_le_p(void *ptr, float32 v)
bellard authored
319
320
{
    union {
bellard authored
321
        float32 f;
bellard authored
322
323
324
        uint32_t i;
    } u;
    u.f = v;
325
    stl_le_p(ptr, u.i);
bellard authored
326
327
}
328
static inline float64 ldfq_le_p(const void *ptr)
bellard authored
329
{
bellard authored
330
    CPU_DoubleU u;
331
332
    u.l.lower = ldl_le_p(ptr);
    u.l.upper = ldl_le_p(ptr + 4);
bellard authored
333
334
335
    return u.d;
}
336
static inline void stfq_le_p(void *ptr, float64 v)
bellard authored
337
{
bellard authored
338
    CPU_DoubleU u;
bellard authored
339
    u.d = v;
340
341
    stl_le_p(ptr, u.l.lower);
    stl_le_p(ptr + 4, u.l.upper);
bellard authored
342
343
}
344
345
#else
346
static inline int lduw_le_p(const void *ptr)
347
348
349
350
{
    return *(uint16_t *)ptr;
}
351
static inline int ldsw_le_p(const void *ptr)
352
353
354
{
    return *(int16_t *)ptr;
}
355
356
static inline int ldl_le_p(const void *ptr)
357
358
359
360
{
    return *(uint32_t *)ptr;
}
361
static inline uint64_t ldq_le_p(const void *ptr)
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
{
    return *(uint64_t *)ptr;
}

static inline void stw_le_p(void *ptr, int v)
{
    *(uint16_t *)ptr = v;
}

static inline void stl_le_p(void *ptr, int v)
{
    *(uint32_t *)ptr = v;
}

static inline void stq_le_p(void *ptr, uint64_t v)
{
    *(uint64_t *)ptr = v;
}

/* float access */
383
static inline float32 ldfl_le_p(const void *ptr)
384
385
386
387
{
    return *(float32 *)ptr;
}
388
static inline float64 ldfq_le_p(const void *ptr)
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
{
    return *(float64 *)ptr;
}

static inline void stfl_le_p(void *ptr, float32 v)
{
    *(float32 *)ptr = v;
}

static inline void stfq_le_p(void *ptr, float64 v)
{
    *(float64 *)ptr = v;
}
#endif

#if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
406
static inline int lduw_be_p(const void *ptr)
407
{
408
409
410
411
412
413
414
415
#if defined(__i386__)
    int val;
    asm volatile ("movzwl %1, %0\n"
                  "xchgb %b0, %h0\n"
                  : "=q" (val)
                  : "m" (*(uint16_t *)ptr));
    return val;
#else
416
    const uint8_t *b = ptr;
417
418
    return ((b[0] << 8) | b[1]);
#endif
419
420
}
421
static inline int ldsw_be_p(const void *ptr)
422
{
423
424
425
426
427
428
429
430
#if defined(__i386__)
    int val;
    asm volatile ("movzwl %1, %0\n"
                  "xchgb %b0, %h0\n"
                  : "=q" (val)
                  : "m" (*(uint16_t *)ptr));
    return (int16_t)val;
#else
431
    const uint8_t *b = ptr;
432
433
    return (int16_t)((b[0] << 8) | b[1]);
#endif
434
435
}
436
static inline int ldl_be_p(const void *ptr)
437
{
bellard authored
438
#if defined(__i386__) || defined(__x86_64__)
439
440
441
442
443
444
445
    int val;
    asm volatile ("movl %1, %0\n"
                  "bswap %0\n"
                  : "=r" (val)
                  : "m" (*(uint32_t *)ptr));
    return val;
#else
446
    const uint8_t *b = ptr;
447
448
    return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
#endif
449
450
}
451
static inline uint64_t ldq_be_p(const void *ptr)
452
453
{
    uint32_t a,b;
454
    a = ldl_be_p(ptr);
455
    b = ldl_be_p((uint8_t *)ptr + 4);
456
457
458
    return (((uint64_t)a<<32)|b);
}
459
static inline void stw_be_p(void *ptr, int v)
460
{
461
462
463
464
465
466
#if defined(__i386__)
    asm volatile ("xchgb %b0, %h0\n"
                  "movw %w0, %1\n"
                  : "=q" (v)
                  : "m" (*(uint16_t *)ptr), "0" (v));
#else
467
468
469
    uint8_t *d = (uint8_t *) ptr;
    d[0] = v >> 8;
    d[1] = v;
470
#endif
471
472
}
473
static inline void stl_be_p(void *ptr, int v)
474
{
bellard authored
475
#if defined(__i386__) || defined(__x86_64__)
476
477
478
479
480
    asm volatile ("bswap %0\n"
                  "movl %0, %1\n"
                  : "=r" (v)
                  : "m" (*(uint32_t *)ptr), "0" (v));
#else
481
482
483
484
485
    uint8_t *d = (uint8_t *) ptr;
    d[0] = v >> 24;
    d[1] = v >> 16;
    d[2] = v >> 8;
    d[3] = v;
486
#endif
487
488
}
489
static inline void stq_be_p(void *ptr, uint64_t v)
490
{
491
    stl_be_p(ptr, v >> 32);
492
    stl_be_p((uint8_t *)ptr + 4, v);
bellard authored
493
494
495
496
}

/* float access */
497
static inline float32 ldfl_be_p(const void *ptr)
bellard authored
498
499
{
    union {
bellard authored
500
        float32 f;
bellard authored
501
502
        uint32_t i;
    } u;
503
    u.i = ldl_be_p(ptr);
bellard authored
504
505
506
    return u.f;
}
507
static inline void stfl_be_p(void *ptr, float32 v)
bellard authored
508
509
{
    union {
bellard authored
510
        float32 f;
bellard authored
511
512
513
        uint32_t i;
    } u;
    u.f = v;
514
    stl_be_p(ptr, u.i);
bellard authored
515
516
}
517
static inline float64 ldfq_be_p(const void *ptr)
bellard authored
518
519
{
    CPU_DoubleU u;
520
    u.l.upper = ldl_be_p(ptr);
521
    u.l.lower = ldl_be_p((uint8_t *)ptr + 4);
bellard authored
522
523
524
    return u.d;
}
525
static inline void stfq_be_p(void *ptr, float64 v)
bellard authored
526
527
528
{
    CPU_DoubleU u;
    u.d = v;
529
    stl_be_p(ptr, u.l.upper);
530
    stl_be_p((uint8_t *)ptr + 4, u.l.lower);
531
532
}
bellard authored
533
534
#else
535
static inline int lduw_be_p(const void *ptr)
bellard authored
536
537
538
539
{
    return *(uint16_t *)ptr;
}
540
static inline int ldsw_be_p(const void *ptr)
bellard authored
541
542
543
544
{
    return *(int16_t *)ptr;
}
545
static inline int ldl_be_p(const void *ptr)
bellard authored
546
547
548
549
{
    return *(uint32_t *)ptr;
}
550
static inline uint64_t ldq_be_p(const void *ptr)
bellard authored
551
552
553
554
{
    return *(uint64_t *)ptr;
}
555
static inline void stw_be_p(void *ptr, int v)
bellard authored
556
557
558
559
{
    *(uint16_t *)ptr = v;
}
560
static inline void stl_be_p(void *ptr, int v)
bellard authored
561
562
563
564
{
    *(uint32_t *)ptr = v;
}
565
static inline void stq_be_p(void *ptr, uint64_t v)
bellard authored
566
567
568
569
570
571
{
    *(uint64_t *)ptr = v;
}

/* float access */
572
static inline float32 ldfl_be_p(const void *ptr)
bellard authored
573
{
bellard authored
574
    return *(float32 *)ptr;
bellard authored
575
576
}
577
static inline float64 ldfq_be_p(const void *ptr)
bellard authored
578
{
bellard authored
579
    return *(float64 *)ptr;
bellard authored
580
581
}
582
static inline void stfl_be_p(void *ptr, float32 v)
bellard authored
583
{
bellard authored
584
    *(float32 *)ptr = v;
bellard authored
585
586
}
587
static inline void stfq_be_p(void *ptr, float64 v)
bellard authored
588
{
bellard authored
589
    *(float64 *)ptr = v;
bellard authored
590
}
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618

#endif

/* target CPU memory access functions */
#if defined(TARGET_WORDS_BIGENDIAN)
#define lduw_p(p) lduw_be_p(p)
#define ldsw_p(p) ldsw_be_p(p)
#define ldl_p(p) ldl_be_p(p)
#define ldq_p(p) ldq_be_p(p)
#define ldfl_p(p) ldfl_be_p(p)
#define ldfq_p(p) ldfq_be_p(p)
#define stw_p(p, v) stw_be_p(p, v)
#define stl_p(p, v) stl_be_p(p, v)
#define stq_p(p, v) stq_be_p(p, v)
#define stfl_p(p, v) stfl_be_p(p, v)
#define stfq_p(p, v) stfq_be_p(p, v)
#else
#define lduw_p(p) lduw_le_p(p)
#define ldsw_p(p) ldsw_le_p(p)
#define ldl_p(p) ldl_le_p(p)
#define ldq_p(p) ldq_le_p(p)
#define ldfl_p(p) ldfl_le_p(p)
#define ldfq_p(p) ldfq_le_p(p)
#define stw_p(p, v) stw_le_p(p, v)
#define stl_p(p, v) stl_le_p(p, v)
#define stq_p(p, v) stq_le_p(p, v)
#define stfl_p(p, v) stfl_le_p(p, v)
#define stfq_p(p, v) stfq_le_p(p, v)
bellard authored
619
620
#endif
bellard authored
621
622
/* MMU memory access macros */
623
#if defined(CONFIG_USER_ONLY)
624
625
626
#include <assert.h>
#include "qemu-types.h"
627
628
629
630
631
632
633
634
/* On some host systems the guest address space is reserved on the host.
 * This allows the guest address space to be offset to a convenient location.
 */
//#define GUEST_BASE 0x20000000
#define GUEST_BASE 0

/* All direct uses of g2h and h2g need to go away for usermode softmmu.  */
#define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
635
636
637
638
639
640
#define h2g(x) ({ \
    unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
    /* Check if given address fits target address space */ \
    assert(__ret == (abi_ulong)__ret); \
    (abi_ulong)__ret; \
})
641
642
643
644
#define h2g_valid(x) ({ \
    unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
    (__guest == (abi_ulong)__guest); \
})
645
646
647
648
649

#define saddr(x) g2h(x)
#define laddr(x) g2h(x)

#else /* !CONFIG_USER_ONLY */
bellard authored
650
651
/* NOTE: we use double casts if pointers and target_ulong have
   different sizes */
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
#define saddr(x) (uint8_t *)(long)(x)
#define laddr(x) (uint8_t *)(long)(x)
#endif

#define ldub_raw(p) ldub_p(laddr((p)))
#define ldsb_raw(p) ldsb_p(laddr((p)))
#define lduw_raw(p) lduw_p(laddr((p)))
#define ldsw_raw(p) ldsw_p(laddr((p)))
#define ldl_raw(p) ldl_p(laddr((p)))
#define ldq_raw(p) ldq_p(laddr((p)))
#define ldfl_raw(p) ldfl_p(laddr((p)))
#define ldfq_raw(p) ldfq_p(laddr((p)))
#define stb_raw(p, v) stb_p(saddr((p)), v)
#define stw_raw(p, v) stw_p(saddr((p)), v)
#define stl_raw(p, v) stl_p(saddr((p)), v)
#define stq_raw(p, v) stq_p(saddr((p)), v)
#define stfl_raw(p, v) stfl_p(saddr((p)), v)
#define stfq_raw(p, v) stfq_p(saddr((p)), v)
bellard authored
670
671
672
#if defined(CONFIG_USER_ONLY)
bellard authored
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694

/* if user mode, no other memory access functions */
#define ldub(p) ldub_raw(p)
#define ldsb(p) ldsb_raw(p)
#define lduw(p) lduw_raw(p)
#define ldsw(p) ldsw_raw(p)
#define ldl(p) ldl_raw(p)
#define ldq(p) ldq_raw(p)
#define ldfl(p) ldfl_raw(p)
#define ldfq(p) ldfq_raw(p)
#define stb(p, v) stb_raw(p, v)
#define stw(p, v) stw_raw(p, v)
#define stl(p, v) stl_raw(p, v)
#define stq(p, v) stq_raw(p, v)
#define stfl(p, v) stfl_raw(p, v)
#define stfq(p, v) stfq_raw(p, v)

#define ldub_code(p) ldub_raw(p)
#define ldsb_code(p) ldsb_raw(p)
#define lduw_code(p) lduw_raw(p)
#define ldsw_code(p) ldsw_raw(p)
#define ldl_code(p) ldl_raw(p)
695
#define ldq_code(p) ldq_raw(p)
bellard authored
696
697
698
699
700
701

#define ldub_kernel(p) ldub_raw(p)
#define ldsb_kernel(p) ldsb_raw(p)
#define lduw_kernel(p) lduw_raw(p)
#define ldsw_kernel(p) ldsw_raw(p)
#define ldl_kernel(p) ldl_raw(p)
702
#define ldq_kernel(p) ldq_raw(p)
bellard authored
703
704
#define ldfl_kernel(p) ldfl_raw(p)
#define ldfq_kernel(p) ldfq_raw(p)
bellard authored
705
706
707
708
#define stb_kernel(p, v) stb_raw(p, v)
#define stw_kernel(p, v) stw_raw(p, v)
#define stl_kernel(p, v) stl_raw(p, v)
#define stq_kernel(p, v) stq_raw(p, v)
bellard authored
709
710
#define stfl_kernel(p, v) stfl_raw(p, v)
#define stfq_kernel(p, vt) stfq_raw(p, v)
bellard authored
711
712
713

#endif /* defined(CONFIG_USER_ONLY) */
bellard authored
714
715
/* page related stuff */
716
#define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
bellard authored
717
718
719
#define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
#define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
720
/* ??? These should be the larger of unsigned long and target_ulong.  */
721
722
723
724
extern unsigned long qemu_real_host_page_size;
extern unsigned long qemu_host_page_bits;
extern unsigned long qemu_host_page_size;
extern unsigned long qemu_host_page_mask;
bellard authored
725
726
#define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
bellard authored
727
728
729
730
731
732
733
734
735

/* same as PROT_xxx */
#define PAGE_READ      0x0001
#define PAGE_WRITE     0x0002
#define PAGE_EXEC      0x0004
#define PAGE_BITS      (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
#define PAGE_VALID     0x0008
/* original state of the write flag (used when tracking self-modifying
   code */
736
#define PAGE_WRITE_ORG 0x0010
737
#define PAGE_RESERVED  0x0020
bellard authored
738
739

void page_dump(FILE *f);
740
741
int page_get_flags(target_ulong address);
void page_set_flags(target_ulong start, target_ulong end, int flags);
742
int page_check_range(target_ulong start, target_ulong len, int flags);
bellard authored
743
744
void cpu_exec_init_all(unsigned long tb_size);
745
746
CPUState *cpu_copy(CPUState *env);
747
void cpu_dump_state(CPUState *env, FILE *f,
bellard authored
748
749
                    int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
                    int flags);
750
751
752
void cpu_dump_statistics (CPUState *env, FILE *f,
                          int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
                          int flags);
bellard authored
753
754
void cpu_abort(CPUState *env, const char *fmt, ...)
755
756
    __attribute__ ((__format__ (__printf__, 2, 3)))
    __attribute__ ((__noreturn__));
757
extern CPUState *first_cpu;
bellard authored
758
extern CPUState *cpu_single_env;
pbrook authored
759
760
extern int64_t qemu_icount;
extern int use_icount;
bellard authored
761
762
763
764
#define CPU_INTERRUPT_EXIT   0x01 /* wants exit from main loop */
#define CPU_INTERRUPT_HARD   0x02 /* hardware interrupt pending */
#define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
bellard authored
765
#define CPU_INTERRUPT_TIMER  0x08 /* internal timer exception pending */
766
#define CPU_INTERRUPT_FIQ    0x10 /* Fast interrupt pending.  */
767
#define CPU_INTERRUPT_HALT   0x20 /* CPU halt wanted */
bellard authored
768
#define CPU_INTERRUPT_SMI    0x40 /* (x86 only) SMI interrupt pending */
769
#define CPU_INTERRUPT_DEBUG  0x80 /* Debug event occured.  */
ths authored
770
#define CPU_INTERRUPT_VIRQ   0x100 /* virtual interrupt pending.  */
771
#define CPU_INTERRUPT_NMI    0x200 /* NMI pending. */
772
bellard authored
773
void cpu_interrupt(CPUState *s, int mask);
774
void cpu_reset_interrupt(CPUState *env, int mask);
bellard authored
775
776
777
778
779
/* Breakpoint/watchpoint flags */
#define BP_MEM_READ           0x01
#define BP_MEM_WRITE          0x02
#define BP_MEM_ACCESS         (BP_MEM_READ | BP_MEM_WRITE)
780
#define BP_STOP_BEFORE_ACCESS 0x04
781
#define BP_WATCHPOINT_HIT     0x08
782
#define BP_GDB                0x10
783
#define BP_CPU                0x20
784
785
786
787
788
789
790
791
792
793
794
795

int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
                          CPUBreakpoint **breakpoint);
int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags);
void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint);
void cpu_breakpoint_remove_all(CPUState *env, int mask);
int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
                          int flags, CPUWatchpoint **watchpoint);
int cpu_watchpoint_remove(CPUState *env, target_ulong addr,
                          target_ulong len, int flags);
void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint);
void cpu_watchpoint_remove_all(CPUState *env, int mask);
796
797
798
799
800

#define SSTEP_ENABLE  0x1  /* Enable simulated HW single stepping */
#define SSTEP_NOIRQ   0x2  /* Do not use IRQ while single stepping */
#define SSTEP_NOTIMER 0x4  /* Do not Timers while single stepping */
801
void cpu_single_step(CPUState *env, int enabled);
bellard authored
802
void cpu_reset(CPUState *s);
bellard authored
803
804
805
806
/* Return the physical page corresponding to a virtual one. Use it
   only for debugging because no protection checks are done. Return -1
   if no page found. */
807
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
808
809
#define CPU_LOG_TB_OUT_ASM (1 << 0)
810
#define CPU_LOG_TB_IN_ASM  (1 << 1)
811
812
813
814
815
#define CPU_LOG_TB_OP      (1 << 2)
#define CPU_LOG_TB_OP_OPT  (1 << 3)
#define CPU_LOG_INT        (1 << 4)
#define CPU_LOG_EXEC       (1 << 5)
#define CPU_LOG_PCALL      (1 << 6)
816
#define CPU_LOG_IOPORT     (1 << 7)
817
#define CPU_LOG_TB_CPU     (1 << 8)
818
819
820
821
822
823
824
825

/* define log items */
typedef struct CPULogItem {
    int mask;
    const char *name;
    const char *help;
} CPULogItem;
826
extern const CPULogItem cpu_log_items[];
827
828
829
void cpu_set_log(int log_flags);
void cpu_set_log_filename(const char *filename);
830
int cpu_str_to_log_mask(const char *str);
831
832
833
834
835
836
837
838
839
840
841
842
843
844
/* IO ports API */

/* NOTE: as these functions may be even used when there is an isa
   brige on non x86 targets, we always defined them */
#ifndef NO_CPU_IO_DEFS
void cpu_outb(CPUState *env, int addr, int val);
void cpu_outw(CPUState *env, int addr, int val);
void cpu_outl(CPUState *env, int addr, int val);
int cpu_inb(CPUState *env, int addr);
int cpu_inw(CPUState *env, int addr);
int cpu_inl(CPUState *env, int addr);
#endif
845
846
847
848
849
850
851
/* address in the RAM (different from a physical address) */
#ifdef USE_KQEMU
typedef uint32_t ram_addr_t;
#else
typedef unsigned long ram_addr_t;
#endif
852
853
/* memory API */
854
extern ram_addr_t phys_ram_size;
bellard authored
855
856
extern int phys_ram_fd;
extern uint8_t *phys_ram_base;
857
extern uint8_t *phys_ram_dirty;
858
extern ram_addr_t ram_size;
bellard authored
859
860

/* physical memory access */
pbrook authored
861
862
863
864
865
866

/* MMIO pages are identified by a combination of an IO device index and
   3 flags.  The ROMD code stores the page ram offset in iotlb entry, 
   so only a limited number of ids are avaiable.  */

#define IO_MEM_SHIFT       3
867
#define IO_MEM_NB_ENTRIES  (1 << (TARGET_PAGE_BITS  - IO_MEM_SHIFT))
bellard authored
868
869
870
871

#define IO_MEM_RAM         (0 << IO_MEM_SHIFT) /* hardcoded offset */
#define IO_MEM_ROM         (1 << IO_MEM_SHIFT) /* hardcoded offset */
#define IO_MEM_UNASSIGNED  (2 << IO_MEM_SHIFT)
pbrook authored
872
873
874
#define IO_MEM_NOTDIRTY    (3 << IO_MEM_SHIFT)

/* Acts like a ROM when read and like a device when written.  */
875
#define IO_MEM_ROMD        (1)
876
#define IO_MEM_SUBPAGE     (2)
877
#define IO_MEM_SUBWIDTH    (4)
bellard authored
878
pbrook authored
879
880
881
882
883
884
885
886
887
888
/* Flags stored in the low bits of the TLB virtual address.  These are
   defined so that fast path ram access is all zeros.  */
/* Zero if TLB entry is valid.  */
#define TLB_INVALID_MASK   (1 << 3)
/* Set if TLB entry references a clean RAM page.  The iotlb entry will
   contain the page physical address.  */
#define TLB_NOTDIRTY    (1 << 4)
/* Set if TLB entry is an IO callback.  */
#define TLB_MMIO        (1 << 5)
889
890
typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
891
892
893
894
895
896
897
898
899
900
901
902
void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
                                         ram_addr_t size,
                                         ram_addr_t phys_offset,
                                         ram_addr_t region_offset);
static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
                                                ram_addr_t size,
                                                ram_addr_t phys_offset)
{
    cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
}
903
904
ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
ram_addr_t qemu_ram_alloc(ram_addr_t);
bellard authored
905
void qemu_ram_free(ram_addr_t addr);
906
907
int cpu_register_io_memory(int io_index,
                           CPUReadMemoryFunc **mem_read,
908
909
                           CPUWriteMemoryFunc **mem_write,
                           void *opaque);
910
911
CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
912
913
void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
914
                            int len, int is_write);
915
static inline void cpu_physical_memory_read(target_phys_addr_t addr,
916
                                            uint8_t *buf, int len)
917
918
919
{
    cpu_physical_memory_rw(addr, buf, len, 0);
}
920
static inline void cpu_physical_memory_write(target_phys_addr_t addr,
921
                                             const uint8_t *buf, int len)
922
923
924
{
    cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
}
925
926
uint32_t ldub_phys(target_phys_addr_t addr);
uint32_t lduw_phys(target_phys_addr_t addr);
927
uint32_t ldl_phys(target_phys_addr_t addr);
928
uint64_t ldq_phys(target_phys_addr_t addr);
929
void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
930
void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
931
932
void stb_phys(target_phys_addr_t addr, uint32_t val);
void stw_phys(target_phys_addr_t addr, uint32_t val);
933
void stl_phys(target_phys_addr_t addr, uint32_t val);
934
void stq_phys(target_phys_addr_t addr, uint64_t val);
935
936
void cpu_physical_memory_write_rom(target_phys_addr_t addr,
937
                                   const uint8_t *buf, int len);
938
int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
939
                        uint8_t *buf, int len, int is_write);
940
941
942
943
944
#define VGA_DIRTY_FLAG       0x01
#define CODE_DIRTY_FLAG      0x02
#define KQEMU_DIRTY_FLAG     0x04
#define MIGRATION_DIRTY_FLAG 0x08
bellard authored
945
946
/* read dirty bit (return 0 or 1) */
bellard authored
947
static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
948
{
bellard authored
949
950
951
    return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
}
952
static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
bellard authored
953
954
955
                                                int dirty_flags)
{
    return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
956
957
}
bellard authored
958
static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
959
{
bellard authored
960
    phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
961
962
}
bellard authored
963
void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
bellard authored
964
                                     int dirty_flags);
bellard authored
965
void cpu_tlb_update_dirty(CPUState *env);
966
967
968
969
970
int cpu_physical_memory_set_dirty_tracking(int enable);

int cpu_physical_memory_get_dirty_tracking(void);
971
972
void cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, target_phys_addr_t end_addr);
bellard authored
973
974
975
void dump_exec_info(FILE *f,
                    int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
aliguori authored
976
977
978
979
980
981
982
983
984
/* Coalesced MMIO regions are areas where write operations can be reordered.
 * This usually implies that write operations are side-effect free.  This allows
 * batching which can make a major impact on performance when using
 * virtualization.
 */
void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);

void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
bellard authored
985
986
987
988
989
/*******************************************/
/* host CPU ticks (if available) */

#if defined(__powerpc__)
990
static inline uint32_t get_tbl(void)
bellard authored
991
992
993
994
995
996
{
    uint32_t tbl;
    asm volatile("mftb %0" : "=r" (tbl));
    return tbl;
}
997
static inline uint32_t get_tbu(void)
bellard authored
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
{
	uint32_t tbl;
	asm volatile("mftbu %0" : "=r" (tbl));
	return tbl;
}

static inline int64_t cpu_get_real_ticks(void)
{
    uint32_t l, h, h1;
    /* NOTE: we test if wrapping has occurred */
    do {
        h = get_tbu();
        l = get_tbl();
        h1 = get_tbu();
    } while (h != h1);
    return ((int64_t)h << 32) | l;
}

#elif defined(__i386__)

static inline int64_t cpu_get_real_ticks(void)
bellard authored
1019
1020
1021
1022
1023
1024
{
    int64_t val;
    asm volatile ("rdtsc" : "=A" (val));
    return val;
}
bellard authored
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
#elif defined(__x86_64__)

static inline int64_t cpu_get_real_ticks(void)
{
    uint32_t low,high;
    int64_t val;
    asm volatile("rdtsc" : "=a" (low), "=d" (high));
    val = high;
    val <<= 32;
    val |= low;
    return val;
}
aurel32 authored
1038
1039
1040
1041
1042
1043
1044
1045
1046
#elif defined(__hppa__)

static inline int64_t cpu_get_real_ticks(void)
{
    int val;
    asm volatile ("mfctl %%cr16, %0" : "=r"(val));
    return val;
}
bellard authored
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
#elif defined(__ia64)

static inline int64_t cpu_get_real_ticks(void)
{
	int64_t val;
	asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory");
	return val;
}

#elif defined(__s390__)

static inline int64_t cpu_get_real_ticks(void)
{
    int64_t val;
    asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc");
    return val;
}
1065
#elif defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
bellard authored
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085

static inline int64_t cpu_get_real_ticks (void)
{
#if     defined(_LP64)
        uint64_t        rval;
        asm volatile("rd %%tick,%0" : "=r"(rval));
        return rval;
#else
        union {
                uint64_t i64;
                struct {
                        uint32_t high;
                        uint32_t low;
                }       i32;
        } rval;
        asm volatile("rd %%tick,%1; srlx %1,32,%0"
                : "=r"(rval.i32.high), "=r"(rval.i32.low));
        return rval.i64;
#endif
}
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106

#elif defined(__mips__)

static inline int64_t cpu_get_real_ticks(void)
{
#if __mips_isa_rev >= 2
    uint32_t count;
    static uint32_t cyc_per_count = 0;

    if (!cyc_per_count)
        __asm__ __volatile__("rdhwr %0, $3" : "=r" (cyc_per_count));

    __asm__ __volatile__("rdhwr %1, $2" : "=r" (count));
    return (int64_t)(count * cyc_per_count);
#else
    /* FIXME */
    static int64_t ticks = 0;
    return ticks++;
#endif
}
pbrook authored
1107
1108
#else
/* The host CPU doesn't have an easily accessible cycle counter.
ths authored
1109
1110
   Just return a monotonically increasing value.  This will be
   totally wrong, but hopefully better than nothing.  */
pbrook authored
1111
1112
1113
1114
1115
static inline int64_t cpu_get_real_ticks (void)
{
    static int64_t ticks = 0;
    return ticks++;
}
bellard authored
1116
1117
1118
1119
1120
1121
1122
1123
1124
#endif

/* profiling */
#ifdef CONFIG_PROFILER
static inline int64_t profile_getclock(void)
{
    return cpu_get_real_ticks();
}
bellard authored
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
extern int64_t kqemu_time, kqemu_time_start;
extern int64_t qemu_time, qemu_time_start;
extern int64_t tlb_flush_time;
extern int64_t kqemu_exec_count;
extern int64_t dev_time;
extern int64_t kqemu_ret_int_count;
extern int64_t kqemu_ret_excp_count;
extern int64_t kqemu_ret_intr_count;
#endif
bellard authored
1135
#endif /* CPU_ALL_H */