gwj / at91sam9263 · Commits

Commit c3d2689d88159291ef8af338b5f01cfbe5551d2c

Authored by balrog
1 parent a5236105

Basic OMAP310 support. Basic Palm Tungsten|E machine emulation. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3091 c046a42c-6fe2-441c-8c8c-71466251a162
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Makefile.target
  View file @c3d2689
... ... @@ -463,6 +463,7 @@ VL_OBJS+= arm-semi.o
463 463 VL_OBJS+= pxa2xx.o pxa2xx_pic.o pxa2xx_gpio.o pxa2xx_timer.o pxa2xx_dma.o
464 464 VL_OBJS+= pxa2xx_lcd.o pxa2xx_mmci.o pxa2xx_pcmcia.o max111x.o max7310.o
465 465 VL_OBJS+= spitz.o ads7846.o ide.o serial.o nand.o $(AUDIODRV) wm8750.o
  466 +VL_OBJS+= omap.o omap_lcdc.o omap1_clk.o palm.o
466 467 CPPFLAGS += -DHAS_AUDIO
467 468 endif
468 469 ifeq ($(TARGET_BASE_ARCH), sh4)
... ...
cpu-all.h
  View file @c3d2689
... ... @@ -702,7 +702,8 @@ void cpu_dump_statistics (CPUState *env, FILE *f,
702 702 int flags);
703 703  
704 704 void cpu_abort(CPUState *env, const char *fmt, ...)
705   - __attribute__ ((__format__ (__printf__, 2, 3)));
  705 + __attribute__ ((__format__ (__printf__, 2, 3)))
  706 + __attribute__ ((__noreturn__));
706 707 extern CPUState *first_cpu;
707 708 extern CPUState *cpu_single_env;
708 709 extern int code_copy_enabled;
... ...
hw/omap.c 0 → 100644
  View file @c3d2689
  1 +/*
  2 + * TI OMAP processors emulation.
  3 + *
  4 + * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
  5 + *
  6 + * This program is free software; you can redistribute it and/or
  7 + * modify it under the terms of the GNU General Public License as
  8 + * published by the Free Software Foundation; either version 2 of
  9 + * the License, or (at your option) any later version.
  10 + *
  11 + * This program is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 + * GNU General Public License for more details.
  15 + *
  16 + * You should have received a copy of the GNU General Public License
  17 + * along with this program; if not, write to the Free Software
  18 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19 + * MA 02111-1307 USA
  20 + */
  21 +#include "vl.h"
  22 +#include "arm_pic.h"
  23 +
  24 +/* Should signal the TCMI */
  25 +static uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
  26 +{
  27 + OMAP_16B_REG(addr);
  28 + return 0;
  29 +}
  30 +
  31 +static void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
  32 + uint32_t value)
  33 +{
  34 + OMAP_16B_REG(addr);
  35 +}
  36 +
  37 +static uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
  38 +{
  39 + OMAP_32B_REG(addr);
  40 + return 0;
  41 +}
  42 +
  43 +static void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
  44 + uint32_t value)
  45 +{
  46 + OMAP_32B_REG(addr);
  47 +}
  48 +
  49 +#define likely
  50 +#define unlikely
  51 +
  52 +/* Interrupt Handlers */
  53 +struct omap_intr_handler_s {
  54 + qemu_irq *pins;
  55 + qemu_irq *parent_pic;
  56 + target_phys_addr_t base;
  57 +
  58 + /* state */
  59 + uint32_t irqs;
  60 + uint32_t mask;
  61 + uint32_t sens_edge;
  62 + uint32_t fiq;
  63 + int priority[32];
  64 + uint32_t new_irq_agr;
  65 + uint32_t new_fiq_agr;
  66 + int sir_irq;
  67 + int sir_fiq;
  68 + int stats[32];
  69 +};
  70 +
  71 +static void omap_inth_update(struct omap_intr_handler_s *s)
  72 +{
  73 + uint32_t irq = s->new_irq_agr & s->irqs & ~s->mask & ~s->fiq;
  74 + uint32_t fiq = s->new_fiq_agr & s->irqs & ~s->mask & s->fiq;
  75 +
  76 + qemu_set_irq(s->parent_pic[ARM_PIC_CPU_IRQ], irq);
  77 + if (irq)
  78 + s->new_irq_agr = 0;
  79 +
  80 + qemu_set_irq(s->parent_pic[ARM_PIC_CPU_FIQ], fiq);
  81 + if (fiq)
  82 + s->new_fiq_agr = 0;
  83 +}
  84 +
  85 +static void omap_inth_sir_update(struct omap_intr_handler_s *s)
  86 +{
  87 + int i, intr_irq, intr_fiq, p_irq, p_fiq, p, f;
  88 + uint32_t level = s->irqs & ~s->mask;
  89 +
  90 + intr_irq = 0;
  91 + intr_fiq = 0;
  92 + p_irq = -1;
  93 + p_fiq = -1;
  94 + /* Find the interrupt line with the highest dynamic priority */
  95 + for (f = ffs(level), i = f - 1, level >>= f - 1; f; i += f, level >>= f) {
  96 + p = s->priority[i];
  97 + if (s->fiq & (1 << i)) {
  98 + if (p > p_fiq) {
  99 + p_fiq = p;
  100 + intr_fiq = i;
  101 + }
  102 + } else {
  103 + if (p > p_irq) {
  104 + p_irq = p;
  105 + intr_irq = i;
  106 + }
  107 + }
  108 +
  109 + f = ffs(level >> 1);
  110 + }
  111 +
  112 + s->sir_irq = intr_irq;
  113 + s->sir_fiq = intr_fiq;
  114 +}
  115 +
  116 +#define INT_FALLING_EDGE 0
  117 +#define INT_LOW_LEVEL 1
  118 +
  119 +static void omap_set_intr(void *opaque, int irq, int req)
  120 +{
  121 + struct omap_intr_handler_s *ih = (struct omap_intr_handler_s *) opaque;
  122 + uint32_t rise;
  123 +
  124 + if (req) {
  125 + rise = ~ih->irqs & (1 << irq);
  126 + ih->irqs |= rise;
  127 + ih->stats[irq] ++;
  128 + } else {
  129 + rise = ih->sens_edge & ih->irqs & (1 << irq);
  130 + ih->irqs &= ~rise;
  131 + }
  132 +
  133 + if (rise & ~ih->mask) {
  134 + omap_inth_sir_update(ih);
  135 +
  136 + omap_inth_update(ih);
  137 + }
  138 +}
  139 +
  140 +static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
  141 +{
  142 + struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
  143 + int i, offset = addr - s->base;
  144 +
  145 + switch (offset) {
  146 + case 0x00: /* ITR */
  147 + return s->irqs;
  148 +
  149 + case 0x04: /* MIR */
  150 + return s->mask;
  151 +
  152 + case 0x10: /* SIR_IRQ_CODE */
  153 + i = s->sir_irq;
  154 + if (((s->sens_edge >> i) & 1) == INT_FALLING_EDGE && i) {
  155 + s->irqs &= ~(1 << i);
  156 + omap_inth_sir_update(s);
  157 + omap_inth_update(s);
  158 + }
  159 + return i;
  160 +
  161 + case 0x14: /* SIR_FIQ_CODE */
  162 + i = s->sir_fiq;
  163 + if (((s->sens_edge >> i) & 1) == INT_FALLING_EDGE && i) {
  164 + s->irqs &= ~(1 << i);
  165 + omap_inth_sir_update(s);
  166 + omap_inth_update(s);
  167 + }
  168 + return i;
  169 +
  170 + case 0x18: /* CONTROL_REG */
  171 + return 0;
  172 +
  173 + case 0x1c: /* ILR0 */
  174 + case 0x20: /* ILR1 */
  175 + case 0x24: /* ILR2 */
  176 + case 0x28: /* ILR3 */
  177 + case 0x2c: /* ILR4 */
  178 + case 0x30: /* ILR5 */
  179 + case 0x34: /* ILR6 */
  180 + case 0x38: /* ILR7 */
  181 + case 0x3c: /* ILR8 */
  182 + case 0x40: /* ILR9 */
  183 + case 0x44: /* ILR10 */
  184 + case 0x48: /* ILR11 */
  185 + case 0x4c: /* ILR12 */
  186 + case 0x50: /* ILR13 */
  187 + case 0x54: /* ILR14 */
  188 + case 0x58: /* ILR15 */
  189 + case 0x5c: /* ILR16 */
  190 + case 0x60: /* ILR17 */
  191 + case 0x64: /* ILR18 */
  192 + case 0x68: /* ILR19 */
  193 + case 0x6c: /* ILR20 */
  194 + case 0x70: /* ILR21 */
  195 + case 0x74: /* ILR22 */
  196 + case 0x78: /* ILR23 */
  197 + case 0x7c: /* ILR24 */
  198 + case 0x80: /* ILR25 */
  199 + case 0x84: /* ILR26 */
  200 + case 0x88: /* ILR27 */
  201 + case 0x8c: /* ILR28 */
  202 + case 0x90: /* ILR29 */
  203 + case 0x94: /* ILR30 */
  204 + case 0x98: /* ILR31 */
  205 + i = (offset - 0x1c) >> 2;
  206 + return (s->priority[i] << 2) |
  207 + (((s->sens_edge >> i) & 1) << 1) |
  208 + ((s->fiq >> i) & 1);
  209 +
  210 + case 0x9c: /* ISR */
  211 + return 0x00000000;
  212 +
  213 + default:
  214 + OMAP_BAD_REG(addr);
  215 + break;
  216 + }
  217 + return 0;
  218 +}
  219 +
  220 +static void omap_inth_write(void *opaque, target_phys_addr_t addr,
  221 + uint32_t value)
  222 +{
  223 + struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
  224 + int i, offset = addr - s->base;
  225 +
  226 + switch (offset) {
  227 + case 0x00: /* ITR */
  228 + s->irqs &= value;
  229 + omap_inth_sir_update(s);
  230 + omap_inth_update(s);
  231 + return;
  232 +
  233 + case 0x04: /* MIR */
  234 + s->mask = value;
  235 + omap_inth_sir_update(s);
  236 + omap_inth_update(s);
  237 + return;
  238 +
  239 + case 0x10: /* SIR_IRQ_CODE */
  240 + case 0x14: /* SIR_FIQ_CODE */
  241 + OMAP_RO_REG(addr);
  242 + break;
  243 +
  244 + case 0x18: /* CONTROL_REG */
  245 + if (value & 2)
  246 + s->new_fiq_agr = ~0;
  247 + if (value & 1)
  248 + s->new_irq_agr = ~0;
  249 + omap_inth_update(s);
  250 + return;
  251 +
  252 + case 0x1c: /* ILR0 */
  253 + case 0x20: /* ILR1 */
  254 + case 0x24: /* ILR2 */
  255 + case 0x28: /* ILR3 */
  256 + case 0x2c: /* ILR4 */
  257 + case 0x30: /* ILR5 */
  258 + case 0x34: /* ILR6 */
  259 + case 0x38: /* ILR7 */
  260 + case 0x3c: /* ILR8 */
  261 + case 0x40: /* ILR9 */
  262 + case 0x44: /* ILR10 */
  263 + case 0x48: /* ILR11 */
  264 + case 0x4c: /* ILR12 */
  265 + case 0x50: /* ILR13 */
  266 + case 0x54: /* ILR14 */
  267 + case 0x58: /* ILR15 */
  268 + case 0x5c: /* ILR16 */
  269 + case 0x60: /* ILR17 */
  270 + case 0x64: /* ILR18 */
  271 + case 0x68: /* ILR19 */
  272 + case 0x6c: /* ILR20 */
  273 + case 0x70: /* ILR21 */
  274 + case 0x74: /* ILR22 */
  275 + case 0x78: /* ILR23 */
  276 + case 0x7c: /* ILR24 */
  277 + case 0x80: /* ILR25 */
  278 + case 0x84: /* ILR26 */
  279 + case 0x88: /* ILR27 */
  280 + case 0x8c: /* ILR28 */
  281 + case 0x90: /* ILR29 */
  282 + case 0x94: /* ILR30 */
  283 + case 0x98: /* ILR31 */
  284 + i = (offset - 0x1c) >> 2;
  285 + s->priority[i] = (value >> 2) & 0x1f;
  286 + s->sens_edge &= ~(1 << i);
  287 + s->sens_edge |= ((value >> 1) & 1) << i;
  288 + s->fiq &= ~(1 << i);
  289 + s->fiq |= (value & 1) << i;
  290 + return;
  291 +
  292 + case 0x9c: /* ISR */
  293 + for (i = 0; i < 32; i ++)
  294 + if (value & (1 << i)) {
  295 + omap_set_intr(s, i, 1);
  296 + return;
  297 + }
  298 + return;
  299 +
  300 + default:
  301 + OMAP_BAD_REG(addr);
  302 + }
  303 +}
  304 +
  305 +static CPUReadMemoryFunc *omap_inth_readfn[] = {
  306 + omap_badwidth_read32,
  307 + omap_badwidth_read32,
  308 + omap_inth_read,
  309 +};
  310 +
  311 +static CPUWriteMemoryFunc *omap_inth_writefn[] = {
  312 + omap_inth_write,
  313 + omap_inth_write,
  314 + omap_inth_write,
  315 +};
  316 +
  317 +static void omap_inth_reset(struct omap_intr_handler_s *s)
  318 +{
  319 + s->irqs = 0x00000000;
  320 + s->mask = 0xffffffff;
  321 + s->sens_edge = 0x00000000;
  322 + s->fiq = 0x00000000;
  323 + memset(s->priority, 0, sizeof(s->priority));
  324 + s->new_irq_agr = ~0;
  325 + s->new_fiq_agr = ~0;
  326 + s->sir_irq = 0;
  327 + s->sir_fiq = 0;
  328 +
  329 + omap_inth_update(s);
  330 +}
  331 +
  332 +struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
  333 + unsigned long size, qemu_irq parent[2], omap_clk clk)
  334 +{
  335 + int iomemtype;
  336 + struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
  337 + qemu_mallocz(sizeof(struct omap_intr_handler_s));
  338 +
  339 + s->parent_pic = parent;
  340 + s->base = base;
  341 + s->pins = qemu_allocate_irqs(omap_set_intr, s, 32);
  342 + omap_inth_reset(s);
  343 +
  344 + iomemtype = cpu_register_io_memory(0, omap_inth_readfn,
  345 + omap_inth_writefn, s);
  346 + cpu_register_physical_memory(s->base, size, iomemtype);
  347 +
  348 + return s;
  349 +}
  350 +
  351 +/* OMAP1 DMA module */
  352 +typedef enum {
  353 + constant = 0,
  354 + post_incremented,
  355 + single_index,
  356 + double_index,
  357 +} omap_dma_addressing_t;
  358 +
  359 +struct omap_dma_channel_s {
  360 + int burst[2];
  361 + int pack[2];
  362 + enum omap_dma_port port[2];
  363 + target_phys_addr_t addr[2];
  364 + omap_dma_addressing_t mode[2];
  365 + int data_type;
  366 + int end_prog;
  367 + int repeat;
  368 + int auto_init;
  369 + int priority;
  370 + int fs;
  371 + int sync;
  372 + int running;
  373 + int interrupts;
  374 + int status;
  375 + int signalled;
  376 + int post_sync;
  377 + int transfer;
  378 + uint16_t elements;
  379 + uint16_t frames;
  380 + uint16_t frame_index;
  381 + uint16_t element_index;
  382 + uint16_t cpc;
  383 +
  384 + struct omap_dma_reg_set_s {
  385 + target_phys_addr_t src, dest;
  386 + int frame;
  387 + int element;
  388 + int frame_delta[2];
  389 + int elem_delta[2];
  390 + int frames;
  391 + int elements;
  392 + } active_set;
  393 +};
  394 +
  395 +struct omap_dma_s {
  396 + qemu_irq *ih;
  397 + QEMUTimer *tm;
  398 + struct omap_mpu_state_s *mpu;
  399 + target_phys_addr_t base;
  400 + omap_clk clk;
  401 + int64_t delay;
  402 +
  403 + uint16_t gcr;
  404 + int run_count;
  405 +
  406 + int chans;
  407 + struct omap_dma_channel_s ch[16];
  408 + struct omap_dma_lcd_channel_s lcd_ch;
  409 +};
  410 +
  411 +static void omap_dma_interrupts_update(struct omap_dma_s *s)
  412 +{
  413 + /* First three interrupts are shared between two channels each. */
  414 + qemu_set_irq(s->ih[OMAP_INT_DMA_CH0_6],
  415 + (s->ch[0].status | s->ch[6].status) & 0x3f);
  416 + qemu_set_irq(s->ih[OMAP_INT_DMA_CH1_7],
  417 + (s->ch[1].status | s->ch[7].status) & 0x3f);
  418 + qemu_set_irq(s->ih[OMAP_INT_DMA_CH2_8],
  419 + (s->ch[2].status | s->ch[8].status) & 0x3f);
  420 + qemu_set_irq(s->ih[OMAP_INT_DMA_CH3],
  421 + (s->ch[3].status) & 0x3f);
  422 + qemu_set_irq(s->ih[OMAP_INT_DMA_CH4],
  423 + (s->ch[4].status) & 0x3f);
  424 + qemu_set_irq(s->ih[OMAP_INT_DMA_CH5],
  425 + (s->ch[5].status) & 0x3f);
  426 +}
  427 +
  428 +static void omap_dma_channel_load(struct omap_dma_s *s, int ch)
  429 +{
  430 + struct omap_dma_reg_set_s *a = &s->ch[ch].active_set;
  431 + int i;
  432 +
  433 + /*
  434 + * TODO: verify address ranges and alignment
  435 + * TODO: port endianness
  436 + */
  437 +
  438 + a->src = s->ch[ch].addr[0];
  439 + a->dest = s->ch[ch].addr[1];
  440 + a->frames = s->ch[ch].frames;
  441 + a->elements = s->ch[ch].elements;
  442 + a->frame = 0;
  443 + a->element = 0;
  444 +
  445 + if (unlikely(!s->ch[ch].elements || !s->ch[ch].frames)) {
  446 + printf("%s: bad DMA request\n", __FUNCTION__);
  447 + return;
  448 + }
  449 +
  450 + for (i = 0; i < 2; i ++)
  451 + switch (s->ch[ch].mode[i]) {
  452 + case constant:
  453 + a->elem_delta[i] = 0;
  454 + a->frame_delta[i] = 0;
  455 + break;
  456 + case post_incremented:
  457 + a->elem_delta[i] = s->ch[ch].data_type;
  458 + a->frame_delta[i] = 0;
  459 + break;
  460 + case single_index:
  461 + a->elem_delta[i] = s->ch[ch].data_type +
  462 + s->ch[ch].element_index - 1;
  463 + if (s->ch[ch].element_index > 0x7fff)
  464 + a->elem_delta[i] -= 0x10000;
  465 + a->frame_delta[i] = 0;
  466 + break;
  467 + case double_index:
  468 + a->elem_delta[i] = s->ch[ch].data_type +
  469 + s->ch[ch].element_index - 1;
  470 + if (s->ch[ch].element_index > 0x7fff)
  471 + a->elem_delta[i] -= 0x10000;
  472 + a->frame_delta[i] = s->ch[ch].frame_index -
  473 + s->ch[ch].element_index;
  474 + if (s->ch[ch].frame_index > 0x7fff)
  475 + a->frame_delta[i] -= 0x10000;
  476 + break;
  477 + default:
  478 + break;
  479 + }
  480 +}
  481 +
  482 +static inline void omap_dma_request_run(struct omap_dma_s *s,
  483 + int channel, int request)
  484 +{
  485 +next_channel:
  486 + if (request > 0)
  487 + for (; channel < 9; channel ++)
  488 + if (s->ch[channel].sync == request && s->ch[channel].running)
  489 + break;
  490 + if (channel >= 9)
  491 + return;
  492 +
  493 + if (s->ch[channel].transfer) {
  494 + if (request > 0) {
  495 + s->ch[channel ++].post_sync = request;
  496 + goto next_channel;
  497 + }
  498 + s->ch[channel].status |= 0x02; /* Synchronisation drop */
  499 + omap_dma_interrupts_update(s);
  500 + return;
  501 + }
  502 +
  503 + if (!s->ch[channel].signalled)
  504 + s->run_count ++;
  505 + s->ch[channel].signalled = 1;
  506 +
  507 + if (request > 0)
  508 + s->ch[channel].status |= 0x40; /* External request */
  509 +
  510 + if (s->delay)
  511 + qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
  512 +
  513 + if (request > 0) {
  514 + channel ++;
  515 + goto next_channel;
  516 + }
  517 +}
  518 +
  519 +static inline void omap_dma_request_stop(struct omap_dma_s *s, int channel)
  520 +{
  521 + if (s->ch[channel].signalled)
  522 + s->run_count --;
  523 + s->ch[channel].signalled = 0;
  524 +
  525 + if (!s->run_count)
  526 + qemu_del_timer(s->tm);
  527 +}
  528 +
  529 +static void omap_dma_channel_run(struct omap_dma_s *s)
  530 +{
  531 + int ch;
  532 + uint16_t status;
  533 + uint8_t value[4];
  534 + struct omap_dma_port_if_s *src_p, *dest_p;
  535 + struct omap_dma_reg_set_s *a;
  536 +
  537 + for (ch = 0; ch < 9; ch ++) {
  538 + a = &s->ch[ch].active_set;
  539 +
  540 + src_p = &s->mpu->port[s->ch[ch].port[0]];
  541 + dest_p = &s->mpu->port[s->ch[ch].port[1]];
  542 + if (s->ch[ch].signalled && (!src_p->addr_valid(s->mpu, a->src) ||
  543 + !dest_p->addr_valid(s->mpu, a->dest))) {
  544 +#if 0
  545 + /* Bus time-out */
  546 + if (s->ch[ch].interrupts & 0x01)
  547 + s->ch[ch].status |= 0x01;
  548 + omap_dma_request_stop(s, ch);
  549 + continue;
  550 +#endif
  551 + printf("%s: Bus time-out in DMA%i operation\n", __FUNCTION__, ch);
  552 + }
  553 +
  554 + status = s->ch[ch].status;
  555 + while (status == s->ch[ch].status && s->ch[ch].signalled) {
  556 + /* Transfer a single element */
  557 + s->ch[ch].transfer = 1;
  558 + cpu_physical_memory_read(a->src, value, s->ch[ch].data_type);
  559 + cpu_physical_memory_write(a->dest, value, s->ch[ch].data_type);
  560 + s->ch[ch].transfer = 0;
  561 +
  562 + a->src += a->elem_delta[0];
  563 + a->dest += a->elem_delta[1];
  564 + a->element ++;
  565 +
  566 + /* Check interrupt conditions */
  567 + if (a->element == a->elements) {
  568 + a->element = 0;
  569 + a->src += a->frame_delta[0];
  570 + a->dest += a->frame_delta[1];
  571 + a->frame ++;
  572 +
  573 + if (a->frame == a->frames) {
  574 + if (!s->ch[ch].repeat || !s->ch[ch].auto_init)
  575 + s->ch[ch].running = 0;
  576 +
  577 + if (s->ch[ch].auto_init &&
  578 + (s->ch[ch].repeat ||
  579 + s->ch[ch].end_prog))
  580 + omap_dma_channel_load(s, ch);
  581 +
  582 + if (s->ch[ch].interrupts & 0x20)
  583 + s->ch[ch].status |= 0x20;
  584 +
  585 + if (!s->ch[ch].sync)
  586 + omap_dma_request_stop(s, ch);
  587 + }
  588 +
  589 + if (s->ch[ch].interrupts & 0x08)
  590 + s->ch[ch].status |= 0x08;
  591 +
  592 + if (s->ch[ch].sync && s->ch[ch].fs) {
  593 + s->ch[ch].status &= ~0x40;
  594 + omap_dma_request_stop(s, ch);
  595 + }
  596 + }
  597 +
  598 + if (a->element == 1 && a->frame == a->frames - 1)
  599 + if (s->ch[ch].interrupts & 0x10)
  600 + s->ch[ch].status |= 0x10;
  601 +
  602 + if (a->element == (a->elements >> 1))
  603 + if (s->ch[ch].interrupts & 0x04)
  604 + s->ch[ch].status |= 0x04;
  605 +
  606 + if (s->ch[ch].sync && !s->ch[ch].fs) {
  607 + s->ch[ch].status &= ~0x40;
  608 + omap_dma_request_stop(s, ch);
  609 + }
  610 +
  611 + /*
  612 + * Process requests made while the element was
  613 + * being transferred.
  614 + */
  615 + if (s->ch[ch].post_sync) {
  616 + omap_dma_request_run(s, 0, s->ch[ch].post_sync);
  617 + s->ch[ch].post_sync = 0;
  618 + }
  619 +
  620 +#if 0
  621 + break;
  622 +#endif
  623 + }
  624 +
  625 + s->ch[ch].cpc = a->dest & 0x0000ffff;
  626 + }
  627 +
  628 + omap_dma_interrupts_update(s);
  629 + if (s->run_count && s->delay)
  630 + qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
  631 +}
  632 +
  633 +static int omap_dma_ch_reg_read(struct omap_dma_s *s,
  634 + int ch, int reg, uint16_t *value) {
  635 + switch (reg) {
  636 + case 0x00: /* SYS_DMA_CSDP_CH0 */
  637 + *value = (s->ch[ch].burst[1] << 14) |
  638 + (s->ch[ch].pack[1] << 13) |
  639 + (s->ch[ch].port[1] << 9) |
  640 + (s->ch[ch].burst[0] << 7) |
  641 + (s->ch[ch].pack[0] << 6) |
  642 + (s->ch[ch].port[0] << 2) |
  643 + (s->ch[ch].data_type >> 1);
  644 + break;
  645 +
  646 + case 0x02: /* SYS_DMA_CCR_CH0 */
  647 + *value = (s->ch[ch].mode[1] << 14) |
  648 + (s->ch[ch].mode[0] << 12) |
  649 + (s->ch[ch].end_prog << 11) |
  650 + (s->ch[ch].repeat << 9) |
  651 + (s->ch[ch].auto_init << 8) |
  652 + (s->ch[ch].running << 7) |
  653 + (s->ch[ch].priority << 6) |
  654 + (s->ch[ch].fs << 5) | s->ch[ch].sync;
  655 + break;
  656 +
  657 + case 0x04: /* SYS_DMA_CICR_CH0 */
  658 + *value = s->ch[ch].interrupts;
  659 + break;
  660 +
  661 + case 0x06: /* SYS_DMA_CSR_CH0 */
  662 + /* FIXME: shared CSR for channels sharing the interrupts */
  663 + *value = s->ch[ch].status;
  664 + s->ch[ch].status &= 0x40;
  665 + omap_dma_interrupts_update(s);
  666 + break;
  667 +
  668 + case 0x08: /* SYS_DMA_CSSA_L_CH0 */
  669 + *value = s->ch[ch].addr[0] & 0x0000ffff;
  670 + break;
  671 +
  672 + case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
  673 + *value = s->ch[ch].addr[0] >> 16;
  674 + break;
  675 +
  676 + case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
  677 + *value = s->ch[ch].addr[1] & 0x0000ffff;
  678 + break;
  679 +
  680 + case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
  681 + *value = s->ch[ch].addr[1] >> 16;
  682 + break;
  683 +
  684 + case 0x10: /* SYS_DMA_CEN_CH0 */
  685 + *value = s->ch[ch].elements;
  686 + break;
  687 +
  688 + case 0x12: /* SYS_DMA_CFN_CH0 */
  689 + *value = s->ch[ch].frames;
  690 + break;
  691 +
  692 + case 0x14: /* SYS_DMA_CFI_CH0 */
  693 + *value = s->ch[ch].frame_index;
  694 + break;
  695 +
  696 + case 0x16: /* SYS_DMA_CEI_CH0 */
  697 + *value = s->ch[ch].element_index;
  698 + break;
  699 +
  700 + case 0x18: /* SYS_DMA_CPC_CH0 */
  701 + *value = s->ch[ch].cpc;
  702 + break;
  703 +
  704 + default:
  705 + return 1;
  706 + }
  707 + return 0;
  708 +}
  709 +
  710 +static int omap_dma_ch_reg_write(struct omap_dma_s *s,
  711 + int ch, int reg, uint16_t value) {
  712 + switch (reg) {
  713 + case 0x00: /* SYS_DMA_CSDP_CH0 */
  714 + s->ch[ch].burst[1] = (value & 0xc000) >> 14;
  715 + s->ch[ch].pack[1] = (value & 0x2000) >> 13;
  716 + s->ch[ch].port[1] = (enum omap_dma_port) ((value & 0x1e00) >> 9);
  717 + s->ch[ch].burst[0] = (value & 0x0180) >> 7;
  718 + s->ch[ch].pack[0] = (value & 0x0040) >> 6;
  719 + s->ch[ch].port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2);
  720 + s->ch[ch].data_type = (1 << (value & 3));
  721 + if (s->ch[ch].port[0] >= omap_dma_port_last)
  722 + printf("%s: invalid DMA port %i\n", __FUNCTION__,
  723 + s->ch[ch].port[0]);
  724 + if (s->ch[ch].port[1] >= omap_dma_port_last)
  725 + printf("%s: invalid DMA port %i\n", __FUNCTION__,
  726 + s->ch[ch].port[1]);
  727 + if ((value & 3) == 3)
  728 + printf("%s: bad data_type for DMA channel %i\n", __FUNCTION__, ch);
  729 + break;
  730 +
  731 + case 0x02: /* SYS_DMA_CCR_CH0 */
  732 + s->ch[ch].mode[1] = (omap_dma_addressing_t) ((value & 0xc000) >> 14);
  733 + s->ch[ch].mode[0] = (omap_dma_addressing_t) ((value & 0x3000) >> 12);
  734 + s->ch[ch].end_prog = (value & 0x0800) >> 11;
  735 + s->ch[ch].repeat = (value & 0x0200) >> 9;
  736 + s->ch[ch].auto_init = (value & 0x0100) >> 8;
  737 + s->ch[ch].priority = (value & 0x0040) >> 6;
  738 + s->ch[ch].fs = (value & 0x0020) >> 5;
  739 + s->ch[ch].sync = value & 0x001f;
  740 + if (value & 0x0080) {
  741 + if (s->ch[ch].running) {
  742 + if (!s->ch[ch].signalled &&
  743 + s->ch[ch].auto_init && s->ch[ch].end_prog)
  744 + omap_dma_channel_load(s, ch);
  745 + } else {
  746 + s->ch[ch].running = 1;
  747 + omap_dma_channel_load(s, ch);
  748 + }
  749 + if (!s->ch[ch].sync)
  750 + omap_dma_request_run(s, ch, 0);
  751 + } else {
  752 + s->ch[ch].running = 0;
  753 + omap_dma_request_stop(s, ch);
  754 + }
  755 + break;
  756 +
  757 + case 0x04: /* SYS_DMA_CICR_CH0 */
  758 + s->ch[ch].interrupts = value & 0x003f;
  759 + break;
  760 +
  761 + case 0x06: /* SYS_DMA_CSR_CH0 */
  762 + return 1;
  763 +
  764 + case 0x08: /* SYS_DMA_CSSA_L_CH0 */
  765 + s->ch[ch].addr[0] &= 0xffff0000;
  766 + s->ch[ch].addr[0] |= value;
  767 + break;
  768 +
  769 + case 0x0a: /* SYS_DMA_CSSA_U_CH0 */
  770 + s->ch[ch].addr[0] &= 0x0000ffff;
  771 + s->ch[ch].addr[0] |= value << 16;
  772 + break;
  773 +
  774 + case 0x0c: /* SYS_DMA_CDSA_L_CH0 */
  775 + s->ch[ch].addr[1] &= 0xffff0000;
  776 + s->ch[ch].addr[1] |= value;
  777 + break;
  778 +
  779 + case 0x0e: /* SYS_DMA_CDSA_U_CH0 */
  780 + s->ch[ch].addr[1] &= 0x0000ffff;
  781 + s->ch[ch].addr[1] |= value << 16;
  782 + break;
  783 +
  784 + case 0x10: /* SYS_DMA_CEN_CH0 */
  785 + s->ch[ch].elements = value & 0xffff;
  786 + break;
  787 +
  788 + case 0x12: /* SYS_DMA_CFN_CH0 */
  789 + s->ch[ch].frames = value & 0xffff;
  790 + break;
  791 +
  792 + case 0x14: /* SYS_DMA_CFI_CH0 */
  793 + s->ch[ch].frame_index = value & 0xffff;
  794 + break;
  795 +
  796 + case 0x16: /* SYS_DMA_CEI_CH0 */
  797 + s->ch[ch].element_index = value & 0xffff;
  798 + break;
  799 +
  800 + case 0x18: /* SYS_DMA_CPC_CH0 */
  801 + return 1;
  802 +
  803 + default:
  804 + OMAP_BAD_REG((unsigned long) reg);
  805 + }
  806 + return 0;
  807 +}
  808 +
  809 +static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
  810 +{
  811 + struct omap_dma_s *s = (struct omap_dma_s *) opaque;
  812 + int i, reg, ch, offset = addr - s->base;
  813 + uint16_t ret;
  814 +
  815 + switch (offset) {
  816 + case 0x000 ... 0x2fe:
  817 + reg = offset & 0x3f;
  818 + ch = (offset >> 6) & 0x0f;
  819 + if (omap_dma_ch_reg_read(s, ch, reg, &ret))
  820 + break;
  821 + return ret;
  822 +
  823 + case 0x300: /* SYS_DMA_LCD_CTRL */
  824 + i = s->lcd_ch.condition;
  825 + s->lcd_ch.condition = 0;
  826 + qemu_irq_lower(s->lcd_ch.irq);
  827 + return ((s->lcd_ch.src == imif) << 6) | (i << 3) |
  828 + (s->lcd_ch.interrupts << 1) | s->lcd_ch.dual;
  829 +
  830 + case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
  831 + return s->lcd_ch.src_f1_top & 0xffff;
  832 +
  833 + case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
  834 + return s->lcd_ch.src_f1_top >> 16;
  835 +
  836 + case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
  837 + return s->lcd_ch.src_f1_bottom & 0xffff;
  838 +
  839 + case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
  840 + return s->lcd_ch.src_f1_bottom >> 16;
  841 +
  842 + case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
  843 + return s->lcd_ch.src_f2_top & 0xffff;
  844 +
  845 + case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
  846 + return s->lcd_ch.src_f2_top >> 16;
  847 +
  848 + case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
  849 + return s->lcd_ch.src_f2_bottom & 0xffff;
  850 +
  851 + case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
  852 + return s->lcd_ch.src_f2_bottom >> 16;
  853 +
  854 + case 0x400: /* SYS_DMA_GCR */
  855 + return s->gcr;
  856 + }
  857 +
  858 + OMAP_BAD_REG(addr);
  859 + return 0;
  860 +}
  861 +
  862 +static void omap_dma_write(void *opaque, target_phys_addr_t addr,
  863 + uint32_t value)
  864 +{
  865 + struct omap_dma_s *s = (struct omap_dma_s *) opaque;
  866 + int reg, ch, offset = addr - s->base;
  867 +
  868 + switch (offset) {
  869 + case 0x000 ... 0x2fe:
  870 + reg = offset & 0x3f;
  871 + ch = (offset >> 6) & 0x0f;
  872 + if (omap_dma_ch_reg_write(s, ch, reg, value))
  873 + OMAP_RO_REG(addr);
  874 + break;
  875 +
  876 + case 0x300: /* SYS_DMA_LCD_CTRL */
  877 + s->lcd_ch.src = (value & 0x40) ? imif : emiff;
  878 + s->lcd_ch.condition = 0;
  879 + /* Assume no bus errors and thus no BUS_ERROR irq bits. */
  880 + s->lcd_ch.interrupts = (value >> 1) & 1;
  881 + s->lcd_ch.dual = value & 1;
  882 + break;
  883 +
  884 + case 0x302: /* SYS_DMA_LCD_TOP_F1_L */
  885 + s->lcd_ch.src_f1_top &= 0xffff0000;
  886 + s->lcd_ch.src_f1_top |= 0x0000ffff & value;
  887 + break;
  888 +
  889 + case 0x304: /* SYS_DMA_LCD_TOP_F1_U */
  890 + s->lcd_ch.src_f1_top &= 0x0000ffff;
  891 + s->lcd_ch.src_f1_top |= value << 16;
  892 + break;
  893 +
  894 + case 0x306: /* SYS_DMA_LCD_BOT_F1_L */
  895 + s->lcd_ch.src_f1_bottom &= 0xffff0000;
  896 + s->lcd_ch.src_f1_bottom |= 0x0000ffff & value;
  897 + break;
  898 +
  899 + case 0x308: /* SYS_DMA_LCD_BOT_F1_U */
  900 + s->lcd_ch.src_f1_bottom &= 0x0000ffff;
  901 + s->lcd_ch.src_f1_bottom |= value << 16;
  902 + break;
  903 +
  904 + case 0x30a: /* SYS_DMA_LCD_TOP_F2_L */
  905 + s->lcd_ch.src_f2_top &= 0xffff0000;
  906 + s->lcd_ch.src_f2_top |= 0x0000ffff & value;
  907 + break;
  908 +
  909 + case 0x30c: /* SYS_DMA_LCD_TOP_F2_U */
  910 + s->lcd_ch.src_f2_top &= 0x0000ffff;
  911 + s->lcd_ch.src_f2_top |= value << 16;
  912 + break;
  913 +
  914 + case 0x30e: /* SYS_DMA_LCD_BOT_F2_L */
  915 + s->lcd_ch.src_f2_bottom &= 0xffff0000;
  916 + s->lcd_ch.src_f2_bottom |= 0x0000ffff & value;
  917 + break;
  918 +
  919 + case 0x310: /* SYS_DMA_LCD_BOT_F2_U */
  920 + s->lcd_ch.src_f2_bottom &= 0x0000ffff;
  921 + s->lcd_ch.src_f2_bottom |= value << 16;
  922 + break;
  923 +
  924 + case 0x400: /* SYS_DMA_GCR */
  925 + s->gcr = value & 0x000c;
  926 + break;
  927 +
  928 + default:
  929 + OMAP_BAD_REG(addr);
  930 + }
  931 +}
  932 +
  933 +static CPUReadMemoryFunc *omap_dma_readfn[] = {
  934 + omap_badwidth_read16,
  935 + omap_dma_read,
  936 + omap_badwidth_read16,
  937 +};
  938 +
  939 +static CPUWriteMemoryFunc *omap_dma_writefn[] = {
  940 + omap_badwidth_write16,
  941 + omap_dma_write,
  942 + omap_badwidth_write16,
  943 +};
  944 +
  945 +static void omap_dma_request(void *opaque, int drq, int req)
  946 +{
  947 + struct omap_dma_s *s = (struct omap_dma_s *) opaque;
  948 + /* All the request pins are edge triggered. */
  949 + if (req)
  950 + omap_dma_request_run(s, 0, drq);
  951 +}
  952 +
  953 +static void omap_dma_clk_update(void *opaque, int line, int on)
  954 +{
  955 + struct omap_dma_s *s = (struct omap_dma_s *) opaque;
  956 +
  957 + if (on) {
  958 + s->delay = ticks_per_sec >> 5;
  959 + if (s->run_count)
  960 + qemu_mod_timer(s->tm, qemu_get_clock(vm_clock) + s->delay);
  961 + } else {
  962 + s->delay = 0;
  963 + qemu_del_timer(s->tm);
  964 + }
  965 +}
  966 +
  967 +static void omap_dma_reset(struct omap_dma_s *s)
  968 +{
  969 + int i;
  970 +
  971 + qemu_del_timer(s->tm);
  972 + s->gcr = 0x0004;
  973 + s->run_count = 0;
  974 + s->lcd_ch.src = emiff;
  975 + s->lcd_ch.condition = 0;
  976 + s->lcd_ch.interrupts = 0;
  977 + s->lcd_ch.dual = 0;
  978 + memset(s->ch, 0, sizeof(s->ch));
  979 + for (i = 0; i < s->chans; i ++)
  980 + s->ch[i].interrupts = 0x0003;
  981 +}
  982 +
  983 +struct omap_dma_s *omap_dma_init(target_phys_addr_t base,
  984 + qemu_irq pic[], struct omap_mpu_state_s *mpu, omap_clk clk)
  985 +{
  986 + int iomemtype;
  987 + struct omap_dma_s *s = (struct omap_dma_s *)
  988 + qemu_mallocz(sizeof(struct omap_dma_s));
  989 +
  990 + s->ih = pic;
  991 + s->base = base;
  992 + s->chans = 9;
  993 + s->mpu = mpu;
  994 + s->clk = clk;
  995 + s->lcd_ch.irq = pic[OMAP_INT_DMA_LCD];
  996 + s->lcd_ch.mpu = mpu;
  997 + s->tm = qemu_new_timer(vm_clock, (QEMUTimerCB *) omap_dma_channel_run, s);
  998 + omap_clk_adduser(s->clk, qemu_allocate_irqs(omap_dma_clk_update, s, 1)[0]);
  999 + mpu->drq = qemu_allocate_irqs(omap_dma_request, s, 32);
  1000 + omap_dma_reset(s);
  1001 +
  1002 + iomemtype = cpu_register_io_memory(0, omap_dma_readfn,
  1003 + omap_dma_writefn, s);
  1004 + cpu_register_physical_memory(s->base, 0x800, iomemtype);
  1005 +
  1006 + return s;
  1007 +}
  1008 +
  1009 +/* DMA ports */
  1010 +int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
  1011 + target_phys_addr_t addr)
  1012 +{
  1013 + return addr >= OMAP_EMIFF_BASE && addr < OMAP_EMIFF_BASE + s->sdram_size;
  1014 +}
  1015 +
  1016 +int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
  1017 + target_phys_addr_t addr)
  1018 +{
  1019 + return addr >= OMAP_EMIFS_BASE && addr < OMAP_EMIFF_BASE;
  1020 +}
  1021 +
  1022 +int omap_validate_imif_addr(struct omap_mpu_state_s *s,
  1023 + target_phys_addr_t addr)
  1024 +{
  1025 + return addr >= OMAP_IMIF_BASE && addr < OMAP_IMIF_BASE + s->sram_size;
  1026 +}
  1027 +
  1028 +int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
  1029 + target_phys_addr_t addr)
  1030 +{
  1031 + return addr >= 0xfffb0000 && addr < 0xffff0000;
  1032 +}
  1033 +
  1034 +int omap_validate_local_addr(struct omap_mpu_state_s *s,
  1035 + target_phys_addr_t addr)
  1036 +{
  1037 + return addr >= OMAP_LOCALBUS_BASE && addr < OMAP_LOCALBUS_BASE + 0x1000000;
  1038 +}
  1039 +
  1040 +int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
  1041 + target_phys_addr_t addr)
  1042 +{
  1043 + return addr >= 0xe1010000 && addr < 0xe1020004;
  1044 +}
  1045 +
  1046 +/* MPU OS timers */
  1047 +struct omap_mpu_timer_s {
  1048 + qemu_irq irq;
  1049 + omap_clk clk;
  1050 + target_phys_addr_t base;
  1051 + uint32_t val;
  1052 + int64_t time;
  1053 + QEMUTimer *timer;
  1054 + int64_t rate;
  1055 + int it_ena;
  1056 +
  1057 + int enable;
  1058 + int ptv;
  1059 + int ar;
  1060 + int st;
  1061 + uint32_t reset_val;
  1062 +};
  1063 +
  1064 +static inline uint32_t omap_timer_read(struct omap_mpu_timer_s *timer)
  1065 +{
  1066 + uint64_t distance = qemu_get_clock(vm_clock) - timer->time;
  1067 +
  1068 + if (timer->st && timer->enable && timer->rate)
  1069 + return timer->val - muldiv64(distance >> (timer->ptv + 1),
  1070 + timer->rate, ticks_per_sec);
  1071 + else
  1072 + return timer->val;
  1073 +}
  1074 +
  1075 +static inline void omap_timer_sync(struct omap_mpu_timer_s *timer)
  1076 +{
  1077 + timer->val = omap_timer_read(timer);
  1078 + timer->time = qemu_get_clock(vm_clock);
  1079 +}
  1080 +
  1081 +static inline void omap_timer_update(struct omap_mpu_timer_s *timer)
  1082 +{
  1083 + int64_t expires;
  1084 +
  1085 + if (timer->enable && timer->st && timer->rate) {
  1086 + timer->val = timer->reset_val; /* Should skip this on clk enable */
  1087 + expires = timer->time + muldiv64(timer->val << (timer->ptv + 1),
  1088 + ticks_per_sec, timer->rate);
  1089 + qemu_mod_timer(timer->timer, expires);
  1090 + } else
  1091 + qemu_del_timer(timer->timer);
  1092 +}
  1093 +
  1094 +static void omap_timer_tick(void *opaque)
  1095 +{
  1096 + struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
  1097 + omap_timer_sync(timer);
  1098 +
  1099 + if (!timer->ar) {
  1100 + timer->val = 0;
  1101 + timer->st = 0;
  1102 + }
  1103 +
  1104 + if (timer->it_ena)
  1105 + qemu_irq_raise(timer->irq);
  1106 + omap_timer_update(timer);
  1107 +}
  1108 +
  1109 +static void omap_timer_clk_update(void *opaque, int line, int on)
  1110 +{
  1111 + struct omap_mpu_timer_s *timer = (struct omap_mpu_timer_s *) opaque;
  1112 +
  1113 + omap_timer_sync(timer);
  1114 + timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
  1115 + omap_timer_update(timer);
  1116 +}
  1117 +
  1118 +static void omap_timer_clk_setup(struct omap_mpu_timer_s *timer)
  1119 +{
  1120 + omap_clk_adduser(timer->clk,
  1121 + qemu_allocate_irqs(omap_timer_clk_update, timer, 1)[0]);
  1122 + timer->rate = omap_clk_getrate(timer->clk);
  1123 +}
  1124 +
  1125 +static uint32_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr)
  1126 +{
  1127 + struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
  1128 + int offset = addr - s->base;
  1129 +
  1130 + switch (offset) {
  1131 + case 0x00: /* CNTL_TIMER */
  1132 + return (s->enable << 5) | (s->ptv << 2) | (s->ar << 1) | s->st;
  1133 +
  1134 + case 0x04: /* LOAD_TIM */
  1135 + break;
  1136 +
  1137 + case 0x08: /* READ_TIM */
  1138 + return omap_timer_read(s);
  1139 + }
  1140 +
  1141 + OMAP_BAD_REG(addr);
  1142 + return 0;
  1143 +}
  1144 +
  1145 +static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
  1146 + uint32_t value)
  1147 +{
  1148 + struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
  1149 + int offset = addr - s->base;
  1150 +
  1151 + switch (offset) {
  1152 + case 0x00: /* CNTL_TIMER */
  1153 + omap_timer_sync(s);
  1154 + s->enable = (value >> 5) & 1;
  1155 + s->ptv = (value >> 2) & 7;
  1156 + s->ar = (value >> 1) & 1;
  1157 + s->st = value & 1;
  1158 + omap_timer_update(s);
  1159 + return;
  1160 +
  1161 + case 0x04: /* LOAD_TIM */
  1162 + s->reset_val = value;
  1163 + return;
  1164 +
  1165 + case 0x08: /* READ_TIM */
  1166 + OMAP_RO_REG(addr);
  1167 + break;
  1168 +
  1169 + default:
  1170 + OMAP_BAD_REG(addr);
  1171 + }
  1172 +}
  1173 +
  1174 +static CPUReadMemoryFunc *omap_mpu_timer_readfn[] = {
  1175 + omap_badwidth_read32,
  1176 + omap_badwidth_read32,
  1177 + omap_mpu_timer_read,
  1178 +};
  1179 +
  1180 +static CPUWriteMemoryFunc *omap_mpu_timer_writefn[] = {
  1181 + omap_badwidth_write32,
  1182 + omap_badwidth_write32,
  1183 + omap_mpu_timer_write,
  1184 +};
  1185 +
  1186 +static void omap_mpu_timer_reset(struct omap_mpu_timer_s *s)
  1187 +{
  1188 + qemu_del_timer(s->timer);
  1189 + s->enable = 0;
  1190 + s->reset_val = 31337;
  1191 + s->val = 0;
  1192 + s->ptv = 0;
  1193 + s->ar = 0;
  1194 + s->st = 0;
  1195 + s->it_ena = 1;
  1196 +}
  1197 +
  1198 +struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
  1199 + qemu_irq irq, omap_clk clk)
  1200 +{
  1201 + int iomemtype;
  1202 + struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
  1203 + qemu_mallocz(sizeof(struct omap_mpu_timer_s));
  1204 +
  1205 + s->irq = irq;
  1206 + s->clk = clk;
  1207 + s->base = base;
  1208 + s->timer = qemu_new_timer(vm_clock, omap_timer_tick, s);
  1209 + omap_mpu_timer_reset(s);
  1210 + omap_timer_clk_setup(s);
  1211 +
  1212 + iomemtype = cpu_register_io_memory(0, omap_mpu_timer_readfn,
  1213 + omap_mpu_timer_writefn, s);
  1214 + cpu_register_physical_memory(s->base, 0x100, iomemtype);
  1215 +
  1216 + return s;
  1217 +}
  1218 +
  1219 +/* Watchdog timer */
  1220 +struct omap_watchdog_timer_s {
  1221 + struct omap_mpu_timer_s timer;
  1222 + uint8_t last_wr;
  1223 + int mode;
  1224 + int free;
  1225 + int reset;
  1226 +};
  1227 +
  1228 +static uint32_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr)
  1229 +{
  1230 + struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
  1231 + int offset = addr - s->timer.base;
  1232 +
  1233 + switch (offset) {
  1234 + case 0x00: /* CNTL_TIMER */
  1235 + return (s->timer.ptv << 9) | (s->timer.ar << 8) |
  1236 + (s->timer.st << 7) | (s->free << 1);
  1237 +
  1238 + case 0x04: /* READ_TIMER */
  1239 + return omap_timer_read(&s->timer);
  1240 +
  1241 + case 0x08: /* TIMER_MODE */
  1242 + return s->mode << 15;
  1243 + }
  1244 +
  1245 + OMAP_BAD_REG(addr);
  1246 + return 0;
  1247 +}
  1248 +
  1249 +static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
  1250 + uint32_t value)
  1251 +{
  1252 + struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
  1253 + int offset = addr - s->timer.base;
  1254 +
  1255 + switch (offset) {
  1256 + case 0x00: /* CNTL_TIMER */
  1257 + omap_timer_sync(&s->timer);
  1258 + s->timer.ptv = (value >> 9) & 7;
  1259 + s->timer.ar = (value >> 8) & 1;
  1260 + s->timer.st = (value >> 7) & 1;
  1261 + s->free = (value >> 1) & 1;
  1262 + omap_timer_update(&s->timer);
  1263 + break;
  1264 +
  1265 + case 0x04: /* LOAD_TIMER */
  1266 + s->timer.reset_val = value & 0xffff;
  1267 + break;
  1268 +
  1269 + case 0x08: /* TIMER_MODE */
  1270 + if (!s->mode && ((value >> 15) & 1))
  1271 + omap_clk_get(s->timer.clk);
  1272 + s->mode |= (value >> 15) & 1;
  1273 + if (s->last_wr == 0xf5) {
  1274 + if ((value & 0xff) == 0xa0) {
  1275 + s->mode = 0;
  1276 + omap_clk_put(s->timer.clk);
  1277 + } else {
  1278 + /* XXX: on T|E hardware somehow this has no effect,
  1279 + * on Zire 71 it works as specified. */
  1280 + s->reset = 1;
  1281 + qemu_system_reset_request();
  1282 + }
  1283 + }
  1284 + s->last_wr = value & 0xff;
  1285 + break;
  1286 +
  1287 + default:
  1288 + OMAP_BAD_REG(addr);
  1289 + }
  1290 +}
  1291 +
  1292 +static CPUReadMemoryFunc *omap_wd_timer_readfn[] = {
  1293 + omap_badwidth_read16,
  1294 + omap_wd_timer_read,
  1295 + omap_badwidth_read16,
  1296 +};
  1297 +
  1298 +static CPUWriteMemoryFunc *omap_wd_timer_writefn[] = {
  1299 + omap_badwidth_write16,
  1300 + omap_wd_timer_write,
  1301 + omap_badwidth_write16,
  1302 +};
  1303 +
  1304 +static void omap_wd_timer_reset(struct omap_watchdog_timer_s *s)
  1305 +{
  1306 + qemu_del_timer(s->timer.timer);
  1307 + if (!s->mode)
  1308 + omap_clk_get(s->timer.clk);
  1309 + s->mode = 1;
  1310 + s->free = 1;
  1311 + s->reset = 0;
  1312 + s->timer.enable = 1;
  1313 + s->timer.it_ena = 1;
  1314 + s->timer.reset_val = 0xffff;
  1315 + s->timer.val = 0;
  1316 + s->timer.st = 0;
  1317 + s->timer.ptv = 0;
  1318 + s->timer.ar = 0;
  1319 + omap_timer_update(&s->timer);
  1320 +}
  1321 +
  1322 +struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
  1323 + qemu_irq irq, omap_clk clk)
  1324 +{
  1325 + int iomemtype;
  1326 + struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
  1327 + qemu_mallocz(sizeof(struct omap_watchdog_timer_s));
  1328 +
  1329 + s->timer.irq = irq;
  1330 + s->timer.clk = clk;
  1331 + s->timer.base = base;
  1332 + s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
  1333 + omap_wd_timer_reset(s);
  1334 + omap_timer_clk_setup(&s->timer);
  1335 +
  1336 + iomemtype = cpu_register_io_memory(0, omap_wd_timer_readfn,
  1337 + omap_wd_timer_writefn, s);
  1338 + cpu_register_physical_memory(s->timer.base, 0x100, iomemtype);
  1339 +
  1340 + return s;
  1341 +}
  1342 +
  1343 +/* 32-kHz timer */
  1344 +struct omap_32khz_timer_s {
  1345 + struct omap_mpu_timer_s timer;
  1346 +};
  1347 +
  1348 +static uint32_t omap_os_timer_read(void *opaque, target_phys_addr_t addr)
  1349 +{
  1350 + struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
  1351 + int offset = addr - s->timer.base;
  1352 +
  1353 + switch (offset) {
  1354 + case 0x00: /* TVR */
  1355 + return s->timer.reset_val;
  1356 +
  1357 + case 0x04: /* TCR */
  1358 + return omap_timer_read(&s->timer);
  1359 +
  1360 + case 0x08: /* CR */
  1361 + return (s->timer.ar << 3) | (s->timer.it_ena << 2) | s->timer.st;
  1362 +
  1363 + default:
  1364 + break;
  1365 + }
  1366 + OMAP_BAD_REG(addr);
  1367 + return 0;
  1368 +}
  1369 +
  1370 +static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
  1371 + uint32_t value)
  1372 +{
  1373 + struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
  1374 + int offset = addr - s->timer.base;
  1375 +
  1376 + switch (offset) {
  1377 + case 0x00: /* TVR */
  1378 + s->timer.reset_val = value & 0x00ffffff;
  1379 + break;
  1380 +
  1381 + case 0x04: /* TCR */
  1382 + OMAP_RO_REG(addr);
  1383 + break;
  1384 +
  1385 + case 0x08: /* CR */
  1386 + s->timer.ar = (value >> 3) & 1;
  1387 + s->timer.it_ena = (value >> 2) & 1;
  1388 + if (s->timer.st != (value & 1) || (value & 2)) {
  1389 + omap_timer_sync(&s->timer);
  1390 + s->timer.enable = value & 1;
  1391 + s->timer.st = value & 1;
  1392 + omap_timer_update(&s->timer);
  1393 + }
  1394 + break;
  1395 +
  1396 + default:
  1397 + OMAP_BAD_REG(addr);
  1398 + }
  1399 +}
  1400 +
  1401 +static CPUReadMemoryFunc *omap_os_timer_readfn[] = {
  1402 + omap_badwidth_read32,
  1403 + omap_badwidth_read32,
  1404 + omap_os_timer_read,
  1405 +};
  1406 +
  1407 +static CPUWriteMemoryFunc *omap_os_timer_writefn[] = {
  1408 + omap_badwidth_write32,
  1409 + omap_badwidth_write32,
  1410 + omap_os_timer_write,
  1411 +};
  1412 +
  1413 +static void omap_os_timer_reset(struct omap_32khz_timer_s *s)
  1414 +{
  1415 + qemu_del_timer(s->timer.timer);
  1416 + s->timer.enable = 0;
  1417 + s->timer.it_ena = 0;
  1418 + s->timer.reset_val = 0x00ffffff;
  1419 + s->timer.val = 0;
  1420 + s->timer.st = 0;
  1421 + s->timer.ptv = 0;
  1422 + s->timer.ar = 1;
  1423 +}
  1424 +
  1425 +struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
  1426 + qemu_irq irq, omap_clk clk)
  1427 +{
  1428 + int iomemtype;
  1429 + struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
  1430 + qemu_mallocz(sizeof(struct omap_32khz_timer_s));
  1431 +
  1432 + s->timer.irq = irq;
  1433 + s->timer.clk = clk;
  1434 + s->timer.base = base;
  1435 + s->timer.timer = qemu_new_timer(vm_clock, omap_timer_tick, &s->timer);
  1436 + omap_os_timer_reset(s);
  1437 + omap_timer_clk_setup(&s->timer);
  1438 +
  1439 + iomemtype = cpu_register_io_memory(0, omap_os_timer_readfn,
  1440 + omap_os_timer_writefn, s);
  1441 + cpu_register_physical_memory(s->timer.base, 0x800, iomemtype);
  1442 +
  1443 + return s;
  1444 +}
  1445 +
  1446 +/* Ultra Low-Power Device Module */
  1447 +static uint32_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr)
  1448 +{
  1449 + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
  1450 + int offset = addr - s->ulpd_pm_base;
  1451 + uint16_t ret;
  1452 +
  1453 + switch (offset) {
  1454 + case 0x14: /* IT_STATUS */
  1455 + ret = s->ulpd_pm_regs[offset >> 2];
  1456 + s->ulpd_pm_regs[offset >> 2] = 0;
  1457 + qemu_irq_lower(s->irq[1][OMAP_INT_GAUGE_32K]);
  1458 + return ret;
  1459 +
  1460 + case 0x18: /* Reserved */
  1461 + case 0x1c: /* Reserved */
  1462 + case 0x20: /* Reserved */
  1463 + case 0x28: /* Reserved */
  1464 + case 0x2c: /* Reserved */
  1465 + OMAP_BAD_REG(addr);
  1466 + case 0x00: /* COUNTER_32_LSB */
  1467 + case 0x04: /* COUNTER_32_MSB */
  1468 + case 0x08: /* COUNTER_HIGH_FREQ_LSB */
  1469 + case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
  1470 + case 0x10: /* GAUGING_CTRL */
  1471 + case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
  1472 + case 0x30: /* CLOCK_CTRL */
  1473 + case 0x34: /* SOFT_REQ */
  1474 + case 0x38: /* COUNTER_32_FIQ */
  1475 + case 0x3c: /* DPLL_CTRL */
  1476 + case 0x40: /* STATUS_REQ */
  1477 + /* XXX: check clk::usecount state for every clock */
  1478 + case 0x48: /* LOCL_TIME */
  1479 + case 0x4c: /* APLL_CTRL */
  1480 + case 0x50: /* POWER_CTRL */
  1481 + return s->ulpd_pm_regs[offset >> 2];
  1482 + }
  1483 +
  1484 + OMAP_BAD_REG(addr);
  1485 + return 0;
  1486 +}
  1487 +
  1488 +static inline void omap_ulpd_clk_update(struct omap_mpu_state_s *s,
  1489 + uint16_t diff, uint16_t value)
  1490 +{
  1491 + if (diff & (1 << 4)) /* USB_MCLK_EN */
  1492 + omap_clk_onoff(omap_findclk(s, "usb_clk0"), (value >> 4) & 1);
  1493 + if (diff & (1 << 5)) /* DIS_USB_PVCI_CLK */
  1494 + omap_clk_onoff(omap_findclk(s, "usb_w2fc_ck"), (~value >> 5) & 1);
  1495 +}
  1496 +
  1497 +static inline void omap_ulpd_req_update(struct omap_mpu_state_s *s,
  1498 + uint16_t diff, uint16_t value)
  1499 +{
  1500 + if (diff & (1 << 0)) /* SOFT_DPLL_REQ */
  1501 + omap_clk_canidle(omap_findclk(s, "dpll4"), (~value >> 0) & 1);
  1502 + if (diff & (1 << 1)) /* SOFT_COM_REQ */
  1503 + omap_clk_canidle(omap_findclk(s, "com_mclk_out"), (~value >> 1) & 1);
  1504 + if (diff & (1 << 2)) /* SOFT_SDW_REQ */
  1505 + omap_clk_canidle(omap_findclk(s, "bt_mclk_out"), (~value >> 2) & 1);
  1506 + if (diff & (1 << 3)) /* SOFT_USB_REQ */
  1507 + omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
  1508 +}
  1509 +
  1510 +static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
  1511 + uint32_t value)
  1512 +{
  1513 + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
  1514 + int offset = addr - s->ulpd_pm_base;
  1515 + int64_t now, ticks;
  1516 + int div, mult;
  1517 + static const int bypass_div[4] = { 1, 2, 4, 4 };
  1518 + uint16_t diff;
  1519 +
  1520 + switch (offset) {
  1521 + case 0x00: /* COUNTER_32_LSB */
  1522 + case 0x04: /* COUNTER_32_MSB */
  1523 + case 0x08: /* COUNTER_HIGH_FREQ_LSB */
  1524 + case 0x0c: /* COUNTER_HIGH_FREQ_MSB */
  1525 + case 0x14: /* IT_STATUS */
  1526 + case 0x40: /* STATUS_REQ */
  1527 + OMAP_RO_REG(addr);
  1528 + break;
  1529 +
  1530 + case 0x10: /* GAUGING_CTRL */
  1531 + /* Bits 0 and 1 seem to be confused in the OMAP 310 TRM */
  1532 + if ((s->ulpd_pm_regs[offset >> 2] ^ value) & 1) {
  1533 + now = qemu_get_clock(vm_clock);
  1534 +
  1535 + if (value & 1)
  1536 + s->ulpd_gauge_start = now;
  1537 + else {
  1538 + now -= s->ulpd_gauge_start;
  1539 +
  1540 + /* 32-kHz ticks */
  1541 + ticks = muldiv64(now, 32768, ticks_per_sec);
  1542 + s->ulpd_pm_regs[0x00 >> 2] = (ticks >> 0) & 0xffff;
  1543 + s->ulpd_pm_regs[0x04 >> 2] = (ticks >> 16) & 0xffff;
  1544 + if (ticks >> 32) /* OVERFLOW_32K */
  1545 + s->ulpd_pm_regs[0x14 >> 2] |= 1 << 2;
  1546 +
  1547 + /* High frequency ticks */
  1548 + ticks = muldiv64(now, 12000000, ticks_per_sec);
  1549 + s->ulpd_pm_regs[0x08 >> 2] = (ticks >> 0) & 0xffff;
  1550 + s->ulpd_pm_regs[0x0c >> 2] = (ticks >> 16) & 0xffff;
  1551 + if (ticks >> 32) /* OVERFLOW_HI_FREQ */
  1552 + s->ulpd_pm_regs[0x14 >> 2] |= 1 << 1;
  1553 +
  1554 + s->ulpd_pm_regs[0x14 >> 2] |= 1 << 0; /* IT_GAUGING */
  1555 + qemu_irq_raise(s->irq[1][OMAP_INT_GAUGE_32K]);
  1556 + }
  1557 + }
  1558 + s->ulpd_pm_regs[offset >> 2] = value;
  1559 + break;
  1560 +
  1561 + case 0x18: /* Reserved */
  1562 + case 0x1c: /* Reserved */
  1563 + case 0x20: /* Reserved */
  1564 + case 0x28: /* Reserved */
  1565 + case 0x2c: /* Reserved */
  1566 + OMAP_BAD_REG(addr);
  1567 + case 0x24: /* SETUP_ANALOG_CELL3_ULPD1 */
  1568 + case 0x38: /* COUNTER_32_FIQ */
  1569 + case 0x48: /* LOCL_TIME */
  1570 + case 0x50: /* POWER_CTRL */
  1571 + s->ulpd_pm_regs[offset >> 2] = value;
  1572 + break;
  1573 +
  1574 + case 0x30: /* CLOCK_CTRL */
  1575 + diff = s->ulpd_pm_regs[offset >> 2] ^ value;
  1576 + s->ulpd_pm_regs[offset >> 2] = value & 0x3f;
  1577 + omap_ulpd_clk_update(s, diff, value);
  1578 + break;
  1579 +
  1580 + case 0x34: /* SOFT_REQ */
  1581 + diff = s->ulpd_pm_regs[offset >> 2] ^ value;
  1582 + s->ulpd_pm_regs[offset >> 2] = value & 0x1f;
  1583 + omap_ulpd_req_update(s, diff, value);
  1584 + break;
  1585 +
  1586 + case 0x3c: /* DPLL_CTRL */
  1587 + /* XXX: OMAP310 TRM claims bit 3 is PLL_ENABLE, and bit 4 is
  1588 + * omitted altogether, probably a typo. */
  1589 + /* This register has identical semantics with DPLL(1:3) control
  1590 + * registers, see omap_dpll_write() */
  1591 + diff = s->ulpd_pm_regs[offset >> 2] & value;
  1592 + s->ulpd_pm_regs[offset >> 2] = value & 0x2fff;
  1593 + if (diff & (0x3ff << 2)) {
  1594 + if (value & (1 << 4)) { /* PLL_ENABLE */
  1595 + div = ((value >> 5) & 3) + 1; /* PLL_DIV */
  1596 + mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
  1597 + } else {
  1598 + div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
  1599 + mult = 1;
  1600 + }
  1601 + omap_clk_setrate(omap_findclk(s, "dpll4"), div, mult);
  1602 + }
  1603 +
  1604 + /* Enter the desired mode. */
  1605 + s->ulpd_pm_regs[offset >> 2] =
  1606 + (s->ulpd_pm_regs[offset >> 2] & 0xfffe) |
  1607 + ((s->ulpd_pm_regs[offset >> 2] >> 4) & 1);
  1608 +
  1609 + /* Act as if the lock is restored. */
  1610 + s->ulpd_pm_regs[offset >> 2] |= 2;
  1611 + break;
  1612 +
  1613 + case 0x4c: /* APLL_CTRL */
  1614 + diff = s->ulpd_pm_regs[offset >> 2] & value;
  1615 + s->ulpd_pm_regs[offset >> 2] = value & 0xf;
  1616 + if (diff & (1 << 0)) /* APLL_NDPLL_SWITCH */
  1617 + omap_clk_reparent(omap_findclk(s, "ck_48m"), omap_findclk(s,
  1618 + (value & (1 << 0)) ? "apll" : "dpll4"));
  1619 + break;
  1620 +
  1621 + default:
  1622 + OMAP_BAD_REG(addr);
  1623 + }
  1624 +}
  1625 +
  1626 +static CPUReadMemoryFunc *omap_ulpd_pm_readfn[] = {
  1627 + omap_badwidth_read16,
  1628 + omap_ulpd_pm_read,
  1629 + omap_badwidth_read16,
  1630 +};
  1631 +
  1632 +static CPUWriteMemoryFunc *omap_ulpd_pm_writefn[] = {
  1633 + omap_badwidth_write16,
  1634 + omap_ulpd_pm_write,
  1635 + omap_badwidth_write16,
  1636 +};
  1637 +
  1638 +static void omap_ulpd_pm_reset(struct omap_mpu_state_s *mpu)
  1639 +{
  1640 + mpu->ulpd_pm_regs[0x00 >> 2] = 0x0001;
  1641 + mpu->ulpd_pm_regs[0x04 >> 2] = 0x0000;
  1642 + mpu->ulpd_pm_regs[0x08 >> 2] = 0x0001;
  1643 + mpu->ulpd_pm_regs[0x0c >> 2] = 0x0000;
  1644 + mpu->ulpd_pm_regs[0x10 >> 2] = 0x0000;
  1645 + mpu->ulpd_pm_regs[0x18 >> 2] = 0x01;
  1646 + mpu->ulpd_pm_regs[0x1c >> 2] = 0x01;
  1647 + mpu->ulpd_pm_regs[0x20 >> 2] = 0x01;
  1648 + mpu->ulpd_pm_regs[0x24 >> 2] = 0x03ff;
  1649 + mpu->ulpd_pm_regs[0x28 >> 2] = 0x01;
  1650 + mpu->ulpd_pm_regs[0x2c >> 2] = 0x01;
  1651 + omap_ulpd_clk_update(mpu, mpu->ulpd_pm_regs[0x30 >> 2], 0x0000);
  1652 + mpu->ulpd_pm_regs[0x30 >> 2] = 0x0000;
  1653 + omap_ulpd_req_update(mpu, mpu->ulpd_pm_regs[0x34 >> 2], 0x0000);
  1654 + mpu->ulpd_pm_regs[0x34 >> 2] = 0x0000;
  1655 + mpu->ulpd_pm_regs[0x38 >> 2] = 0x0001;
  1656 + mpu->ulpd_pm_regs[0x3c >> 2] = 0x2211;
  1657 + mpu->ulpd_pm_regs[0x40 >> 2] = 0x0000; /* FIXME: dump a real STATUS_REQ */
  1658 + mpu->ulpd_pm_regs[0x48 >> 2] = 0x960;
  1659 + mpu->ulpd_pm_regs[0x4c >> 2] = 0x08;
  1660 + mpu->ulpd_pm_regs[0x50 >> 2] = 0x08;
  1661 + omap_clk_setrate(omap_findclk(mpu, "dpll4"), 1, 4);
  1662 + omap_clk_reparent(omap_findclk(mpu, "ck_48m"), omap_findclk(mpu, "dpll4"));
  1663 +}
  1664 +
  1665 +static void omap_ulpd_pm_init(target_phys_addr_t base,
  1666 + struct omap_mpu_state_s *mpu)
  1667 +{
  1668 + int iomemtype = cpu_register_io_memory(0, omap_ulpd_pm_readfn,
  1669 + omap_ulpd_pm_writefn, mpu);
  1670 +
  1671 + mpu->ulpd_pm_base = base;
  1672 + cpu_register_physical_memory(mpu->ulpd_pm_base, 0x800, iomemtype);
  1673 + omap_ulpd_pm_reset(mpu);
  1674 +}
  1675 +
  1676 +/* OMAP Pin Configuration */
  1677 +static uint32_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr)
  1678 +{
  1679 + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
  1680 + int offset = addr - s->pin_cfg_base;
  1681 +
  1682 + switch (offset) {
  1683 + case 0x00: /* FUNC_MUX_CTRL_0 */
  1684 + case 0x04: /* FUNC_MUX_CTRL_1 */
  1685 + case 0x08: /* FUNC_MUX_CTRL_2 */
  1686 + return s->func_mux_ctrl[offset >> 2];
  1687 +
  1688 + case 0x0c: /* COMP_MODE_CTRL_0 */
  1689 + return s->comp_mode_ctrl[0];
  1690 +
  1691 + case 0x10: /* FUNC_MUX_CTRL_3 */
  1692 + case 0x14: /* FUNC_MUX_CTRL_4 */
  1693 + case 0x18: /* FUNC_MUX_CTRL_5 */
  1694 + case 0x1c: /* FUNC_MUX_CTRL_6 */
  1695 + case 0x20: /* FUNC_MUX_CTRL_7 */
  1696 + case 0x24: /* FUNC_MUX_CTRL_8 */
  1697 + case 0x28: /* FUNC_MUX_CTRL_9 */
  1698 + case 0x2c: /* FUNC_MUX_CTRL_A */
  1699 + case 0x30: /* FUNC_MUX_CTRL_B */
  1700 + case 0x34: /* FUNC_MUX_CTRL_C */
  1701 + case 0x38: /* FUNC_MUX_CTRL_D */
  1702 + return s->func_mux_ctrl[(offset >> 2) - 1];
  1703 +
  1704 + case 0x40: /* PULL_DWN_CTRL_0 */
  1705 + case 0x44: /* PULL_DWN_CTRL_1 */
  1706 + case 0x48: /* PULL_DWN_CTRL_2 */
  1707 + case 0x4c: /* PULL_DWN_CTRL_3 */
  1708 + return s->pull_dwn_ctrl[(offset & 0xf) >> 2];
  1709 +
  1710 + case 0x50: /* GATE_INH_CTRL_0 */
  1711 + return s->gate_inh_ctrl[0];
  1712 +
  1713 + case 0x60: /* VOLTAGE_CTRL_0 */
  1714 + return s->voltage_ctrl[0];
  1715 +
  1716 + case 0x70: /* TEST_DBG_CTRL_0 */
  1717 + return s->test_dbg_ctrl[0];
  1718 +
  1719 + case 0x80: /* MOD_CONF_CTRL_0 */
  1720 + return s->mod_conf_ctrl[0];
  1721 + }
  1722 +
  1723 + OMAP_BAD_REG(addr);
  1724 + return 0;
  1725 +}
  1726 +
  1727 +static inline void omap_pin_funcmux0_update(struct omap_mpu_state_s *s,
  1728 + uint32_t diff, uint32_t value)
  1729 +{
  1730 + if (s->compat1509) {
  1731 + if (diff & (1 << 9)) /* BLUETOOTH */
  1732 + omap_clk_onoff(omap_findclk(s, "bt_mclk_out"),
  1733 + (~value >> 9) & 1);
  1734 + if (diff & (1 << 7)) /* USB.CLKO */
  1735 + omap_clk_onoff(omap_findclk(s, "usb.clko"),
  1736 + (value >> 7) & 1);
  1737 + }
  1738 +}
  1739 +
  1740 +static inline void omap_pin_funcmux1_update(struct omap_mpu_state_s *s,
  1741 + uint32_t diff, uint32_t value)
  1742 +{
  1743 + if (s->compat1509) {
  1744 + if (diff & (1 << 31)) /* MCBSP3_CLK_HIZ_DI */
  1745 + omap_clk_onoff(omap_findclk(s, "mcbsp3.clkx"),
  1746 + (value >> 31) & 1);
  1747 + if (diff & (1 << 1)) /* CLK32K */
  1748 + omap_clk_onoff(omap_findclk(s, "clk32k_out"),
  1749 + (~value >> 1) & 1);
  1750 + }
  1751 +}
  1752 +
  1753 +static inline void omap_pin_modconf1_update(struct omap_mpu_state_s *s,
  1754 + uint32_t diff, uint32_t value)
  1755 +{
  1756 + if (diff & (1 << 31)) /* CONF_MOD_UART3_CLK_MODE_R */
  1757 + omap_clk_reparent(omap_findclk(s, "uart3_ck"),
  1758 + omap_findclk(s, ((value >> 31) & 1) ?
  1759 + "ck_48m" : "armper_ck"));
  1760 + if (diff & (1 << 30)) /* CONF_MOD_UART2_CLK_MODE_R */
  1761 + omap_clk_reparent(omap_findclk(s, "uart2_ck"),
  1762 + omap_findclk(s, ((value >> 30) & 1) ?
  1763 + "ck_48m" : "armper_ck"));
  1764 + if (diff & (1 << 29)) /* CONF_MOD_UART1_CLK_MODE_R */
  1765 + omap_clk_reparent(omap_findclk(s, "uart1_ck"),
  1766 + omap_findclk(s, ((value >> 29) & 1) ?
  1767 + "ck_48m" : "armper_ck"));
  1768 + if (diff & (1 << 23)) /* CONF_MOD_MMC_SD_CLK_REQ_R */
  1769 + omap_clk_reparent(omap_findclk(s, "mmc_ck"),
  1770 + omap_findclk(s, ((value >> 23) & 1) ?
  1771 + "ck_48m" : "armper_ck"));
  1772 + if (diff & (1 << 12)) /* CONF_MOD_COM_MCLK_12_48_S */
  1773 + omap_clk_reparent(omap_findclk(s, "com_mclk_out"),
  1774 + omap_findclk(s, ((value >> 12) & 1) ?
  1775 + "ck_48m" : "armper_ck"));
  1776 + if (diff & (1 << 9)) /* CONF_MOD_USB_HOST_HHC_UHO */
  1777 + omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
  1778 +}
  1779 +
  1780 +static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
  1781 + uint32_t value)
  1782 +{
  1783 + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
  1784 + int offset = addr - s->pin_cfg_base;
  1785 + uint32_t diff;
  1786 +
  1787 + switch (offset) {
  1788 + case 0x00: /* FUNC_MUX_CTRL_0 */
  1789 + diff = s->func_mux_ctrl[offset >> 2] ^ value;
  1790 + s->func_mux_ctrl[offset >> 2] = value;
  1791 + omap_pin_funcmux0_update(s, diff, value);
  1792 + return;
  1793 +
  1794 + case 0x04: /* FUNC_MUX_CTRL_1 */
  1795 + diff = s->func_mux_ctrl[offset >> 2] ^ value;
  1796 + s->func_mux_ctrl[offset >> 2] = value;
  1797 + omap_pin_funcmux1_update(s, diff, value);
  1798 + return;
  1799 +
  1800 + case 0x08: /* FUNC_MUX_CTRL_2 */
  1801 + s->func_mux_ctrl[offset >> 2] = value;
  1802 + return;
  1803 +
  1804 + case 0x0c: /* COMP_MODE_CTRL_0 */
  1805 + s->comp_mode_ctrl[0] = value;
  1806 + s->compat1509 = (value != 0x0000eaef);
  1807 + omap_pin_funcmux0_update(s, ~0, s->func_mux_ctrl[0]);
  1808 + omap_pin_funcmux1_update(s, ~0, s->func_mux_ctrl[1]);
  1809 + return;
  1810 +
  1811 + case 0x10: /* FUNC_MUX_CTRL_3 */
  1812 + case 0x14: /* FUNC_MUX_CTRL_4 */
  1813 + case 0x18: /* FUNC_MUX_CTRL_5 */
  1814 + case 0x1c: /* FUNC_MUX_CTRL_6 */
  1815 + case 0x20: /* FUNC_MUX_CTRL_7 */
  1816 + case 0x24: /* FUNC_MUX_CTRL_8 */
  1817 + case 0x28: /* FUNC_MUX_CTRL_9 */
  1818 + case 0x2c: /* FUNC_MUX_CTRL_A */
  1819 + case 0x30: /* FUNC_MUX_CTRL_B */
  1820 + case 0x34: /* FUNC_MUX_CTRL_C */
  1821 + case 0x38: /* FUNC_MUX_CTRL_D */
  1822 + s->func_mux_ctrl[(offset >> 2) - 1] = value;
  1823 + return;
  1824 +
  1825 + case 0x40: /* PULL_DWN_CTRL_0 */
  1826 + case 0x44: /* PULL_DWN_CTRL_1 */
  1827 + case 0x48: /* PULL_DWN_CTRL_2 */
  1828 + case 0x4c: /* PULL_DWN_CTRL_3 */
  1829 + s->pull_dwn_ctrl[(offset & 0xf) >> 2] = value;
  1830 + return;
  1831 +
  1832 + case 0x50: /* GATE_INH_CTRL_0 */
  1833 + s->gate_inh_ctrl[0] = value;
  1834 + return;
  1835 +
  1836 + case 0x60: /* VOLTAGE_CTRL_0 */
  1837 + s->voltage_ctrl[0] = value;
  1838 + return;
  1839 +
  1840 + case 0x70: /* TEST_DBG_CTRL_0 */
  1841 + s->test_dbg_ctrl[0] = value;
  1842 + return;
  1843 +
  1844 + case 0x80: /* MOD_CONF_CTRL_0 */
  1845 + diff = s->mod_conf_ctrl[0] ^ value;
  1846 + s->mod_conf_ctrl[0] = value;
  1847 + omap_pin_modconf1_update(s, diff, value);
  1848 + return;
  1849 +
  1850 + default:
  1851 + OMAP_BAD_REG(addr);
  1852 + }
  1853 +}
  1854 +
  1855 +static CPUReadMemoryFunc *omap_pin_cfg_readfn[] = {
  1856 + omap_badwidth_read32,
  1857 + omap_badwidth_read32,
  1858 + omap_pin_cfg_read,
  1859 +};
  1860 +
  1861 +static CPUWriteMemoryFunc *omap_pin_cfg_writefn[] = {
  1862 + omap_badwidth_write32,
  1863 + omap_badwidth_write32,
  1864 + omap_pin_cfg_write,
  1865 +};
  1866 +
  1867 +static void omap_pin_cfg_reset(struct omap_mpu_state_s *mpu)
  1868 +{
  1869 + /* Start in Compatibility Mode. */
  1870 + mpu->compat1509 = 1;
  1871 + omap_pin_funcmux0_update(mpu, mpu->func_mux_ctrl[0], 0);
  1872 + omap_pin_funcmux1_update(mpu, mpu->func_mux_ctrl[1], 0);
  1873 + omap_pin_modconf1_update(mpu, mpu->mod_conf_ctrl[0], 0);
  1874 + memset(mpu->func_mux_ctrl, 0, sizeof(mpu->func_mux_ctrl));
  1875 + memset(mpu->comp_mode_ctrl, 0, sizeof(mpu->comp_mode_ctrl));
  1876 + memset(mpu->pull_dwn_ctrl, 0, sizeof(mpu->pull_dwn_ctrl));
  1877 + memset(mpu->gate_inh_ctrl, 0, sizeof(mpu->gate_inh_ctrl));
  1878 + memset(mpu->voltage_ctrl, 0, sizeof(mpu->voltage_ctrl));
  1879 + memset(mpu->test_dbg_ctrl, 0, sizeof(mpu->test_dbg_ctrl));
  1880 + memset(mpu->mod_conf_ctrl, 0, sizeof(mpu->mod_conf_ctrl));
  1881 +}
  1882 +
  1883 +static void omap_pin_cfg_init(target_phys_addr_t base,
  1884 + struct omap_mpu_state_s *mpu)
  1885 +{
  1886 + int iomemtype = cpu_register_io_memory(0, omap_pin_cfg_readfn,
  1887 + omap_pin_cfg_writefn, mpu);
  1888 +
  1889 + mpu->pin_cfg_base = base;
  1890 + cpu_register_physical_memory(mpu->pin_cfg_base, 0x800, iomemtype);
  1891 + omap_pin_cfg_reset(mpu);
  1892 +}
  1893 +
  1894 +/* Device Identification, Die Identification */
  1895 +static uint32_t omap_id_read(void *opaque, target_phys_addr_t addr)
  1896 +{
  1897 + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
  1898 +
  1899 + switch (addr) {
  1900 + case 0xfffe1800: /* DIE_ID_LSB */
  1901 + return 0xc9581f0e;
  1902 + case 0xfffe1804: /* DIE_ID_MSB */
  1903 + return 0xa8858bfa;
  1904 +
  1905 + case 0xfffe2000: /* PRODUCT_ID_LSB */
  1906 + return 0x00aaaafc;
  1907 + case 0xfffe2004: /* PRODUCT_ID_MSB */
  1908 + return 0xcafeb574;
  1909 +
  1910 + case 0xfffed400: /* JTAG_ID_LSB */
  1911 + switch (s->mpu_model) {
  1912 + case omap310:
  1913 + return 0x03310315;
  1914 + case omap1510:
  1915 + return 0x03310115;
  1916 + }
  1917 + break;
  1918 +
  1919 + case 0xfffed404: /* JTAG_ID_MSB */
  1920 + switch (s->mpu_model) {
  1921 + case omap310:
  1922 + return 0xfb57402f;
  1923 + case omap1510:
  1924 + return 0xfb47002f;
  1925 + }
  1926 + break;
  1927 + }
  1928 +
  1929 + OMAP_BAD_REG(addr);
  1930 + return 0;
  1931 +}
  1932 +
  1933 +static void omap_id_write(void *opaque, target_phys_addr_t addr,
  1934 + uint32_t value)
  1935 +{
  1936 + OMAP_BAD_REG(addr);
  1937 +}
  1938 +
  1939 +static CPUReadMemoryFunc *omap_id_readfn[] = {
  1940 + omap_badwidth_read32,
  1941 + omap_badwidth_read32,
  1942 + omap_id_read,
  1943 +};
  1944 +
  1945 +static CPUWriteMemoryFunc *omap_id_writefn[] = {
  1946 + omap_badwidth_write32,
  1947 + omap_badwidth_write32,
  1948 + omap_id_write,
  1949 +};
  1950 +
  1951 +static void omap_id_init(struct omap_mpu_state_s *mpu)
  1952 +{
  1953 + int iomemtype = cpu_register_io_memory(0, omap_id_readfn,
  1954 + omap_id_writefn, mpu);
  1955 + cpu_register_physical_memory(0xfffe1800, 0x800, iomemtype);
  1956 + cpu_register_physical_memory(0xfffed400, 0x100, iomemtype);
  1957 + if (!cpu_is_omap15xx(mpu))
  1958 + cpu_register_physical_memory(0xfffe2000, 0x800, iomemtype);
  1959 +}
  1960 +
  1961 +/* MPUI Control (Dummy) */
  1962 +static uint32_t omap_mpui_read(void *opaque, target_phys_addr_t addr)
  1963 +{
  1964 + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
  1965 + int offset = addr - s->mpui_base;
  1966 +
  1967 + switch (offset) {
  1968 + case 0x00: /* CTRL */
  1969 + return s->mpui_ctrl;
  1970 + case 0x04: /* DEBUG_ADDR */
  1971 + return 0x01ffffff;
  1972 + case 0x08: /* DEBUG_DATA */
  1973 + return 0xffffffff;
  1974 + case 0x0c: /* DEBUG_FLAG */
  1975 + return 0x00000800;
  1976 + case 0x10: /* STATUS */
  1977 + return 0x00000000;
  1978 +
  1979 + /* Not in OMAP310 */
  1980 + case 0x14: /* DSP_STATUS */
  1981 + case 0x18: /* DSP_BOOT_CONFIG */
  1982 + return 0x00000000;
  1983 + case 0x1c: /* DSP_MPUI_CONFIG */
  1984 + return 0x0000ffff;
  1985 + }
  1986 +
  1987 + OMAP_BAD_REG(addr);
  1988 + return 0;
  1989 +}
  1990 +
  1991 +static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
  1992 + uint32_t value)
  1993 +{
  1994 + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
  1995 + int offset = addr - s->mpui_base;
  1996 +
  1997 + switch (offset) {
  1998 + case 0x00: /* CTRL */
  1999 + s->mpui_ctrl = value & 0x007fffff;
  2000 + break;
  2001 +
  2002 + case 0x04: /* DEBUG_ADDR */
  2003 + case 0x08: /* DEBUG_DATA */
  2004 + case 0x0c: /* DEBUG_FLAG */
  2005 + case 0x10: /* STATUS */
  2006 + /* Not in OMAP310 */
  2007 + case 0x14: /* DSP_STATUS */
  2008 + OMAP_RO_REG(addr);
  2009 + case 0x18: /* DSP_BOOT_CONFIG */
  2010 + case 0x1c: /* DSP_MPUI_CONFIG */
  2011 + break;
  2012 +
  2013 + default:
  2014 + OMAP_BAD_REG(addr);
  2015 + }
  2016 +}
  2017 +
  2018 +static CPUReadMemoryFunc *omap_mpui_readfn[] = {
  2019 + omap_badwidth_read32,
  2020 + omap_badwidth_read32,
  2021 + omap_mpui_read,
  2022 +};
  2023 +
  2024 +static CPUWriteMemoryFunc *omap_mpui_writefn[] = {
  2025 + omap_badwidth_write32,
  2026 + omap_badwidth_write32,
  2027 + omap_mpui_write,
  2028 +};
  2029 +
  2030 +static void omap_mpui_reset(struct omap_mpu_state_s *s)
  2031 +{
  2032 + s->mpui_ctrl = 0x0003ff1b;
  2033 +}
  2034 +
  2035 +static void omap_mpui_init(target_phys_addr_t base,
  2036 + struct omap_mpu_state_s *mpu)
  2037 +{
  2038 + int iomemtype = cpu_register_io_memory(0, omap_mpui_readfn,
  2039 + omap_mpui_writefn, mpu);
  2040 +
  2041 + mpu->mpui_base = base;
  2042 + cpu_register_physical_memory(mpu->mpui_base, 0x100, iomemtype);
  2043 +
  2044 + omap_mpui_reset(mpu);
  2045 +}
  2046 +
  2047 +/* TIPB Bridges */
  2048 +struct omap_tipb_bridge_s {
  2049 + target_phys_addr_t base;
  2050 + qemu_irq abort;
  2051 +
  2052 + int width_intr;
  2053 + uint16_t control;
  2054 + uint16_t alloc;
  2055 + uint16_t buffer;
  2056 + uint16_t enh_control;
  2057 +};
  2058 +
  2059 +static uint32_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr)
  2060 +{
  2061 + struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
  2062 + int offset = addr - s->base;
  2063 +
  2064 + switch (offset) {
  2065 + case 0x00: /* TIPB_CNTL */
  2066 + return s->control;
  2067 + case 0x04: /* TIPB_BUS_ALLOC */
  2068 + return s->alloc;
  2069 + case 0x08: /* MPU_TIPB_CNTL */
  2070 + return s->buffer;
  2071 + case 0x0c: /* ENHANCED_TIPB_CNTL */
  2072 + return s->enh_control;
  2073 + case 0x10: /* ADDRESS_DBG */
  2074 + case 0x14: /* DATA_DEBUG_LOW */
  2075 + case 0x18: /* DATA_DEBUG_HIGH */
  2076 + return 0xffff;
  2077 + case 0x1c: /* DEBUG_CNTR_SIG */
  2078 + return 0x00f8;
  2079 + }
  2080 +
  2081 + OMAP_BAD_REG(addr);
  2082 + return 0;
  2083 +}
  2084 +
  2085 +static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
  2086 + uint32_t value)
  2087 +{
  2088 + struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
  2089 + int offset = addr - s->base;
  2090 +
  2091 + switch (offset) {
  2092 + case 0x00: /* TIPB_CNTL */
  2093 + s->control = value & 0xffff;
  2094 + break;
  2095 +
  2096 + case 0x04: /* TIPB_BUS_ALLOC */
  2097 + s->alloc = value & 0x003f;
  2098 + break;
  2099 +
  2100 + case 0x08: /* MPU_TIPB_CNTL */
  2101 + s->buffer = value & 0x0003;
  2102 + break;
  2103 +
  2104 + case 0x0c: /* ENHANCED_TIPB_CNTL */
  2105 + s->width_intr = !(value & 2);
  2106 + s->enh_control = value & 0x000f;
  2107 + break;
  2108 +
  2109 + case 0x10: /* ADDRESS_DBG */
  2110 + case 0x14: /* DATA_DEBUG_LOW */
  2111 + case 0x18: /* DATA_DEBUG_HIGH */
  2112 + case 0x1c: /* DEBUG_CNTR_SIG */
  2113 + OMAP_RO_REG(addr);
  2114 + break;
  2115 +
  2116 + default:
  2117 + OMAP_BAD_REG(addr);
  2118 + }
  2119 +}
  2120 +
  2121 +static CPUReadMemoryFunc *omap_tipb_bridge_readfn[] = {
  2122 + omap_badwidth_read16,
  2123 + omap_tipb_bridge_read,
  2124 + omap_tipb_bridge_read,
  2125 +};
  2126 +
  2127 +static CPUWriteMemoryFunc *omap_tipb_bridge_writefn[] = {
  2128 + omap_badwidth_write16,
  2129 + omap_tipb_bridge_write,
  2130 + omap_tipb_bridge_write,
  2131 +};
  2132 +
  2133 +static void omap_tipb_bridge_reset(struct omap_tipb_bridge_s *s)
  2134 +{
  2135 + s->control = 0xffff;
  2136 + s->alloc = 0x0009;
  2137 + s->buffer = 0x0000;
  2138 + s->enh_control = 0x000f;
  2139 +}
  2140 +
  2141 +struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
  2142 + qemu_irq abort_irq, omap_clk clk)
  2143 +{
  2144 + int iomemtype;
  2145 + struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
  2146 + qemu_mallocz(sizeof(struct omap_tipb_bridge_s));
  2147 +
  2148 + s->abort = abort_irq;
  2149 + s->base = base;
  2150 + omap_tipb_bridge_reset(s);
  2151 +
  2152 + iomemtype = cpu_register_io_memory(0, omap_tipb_bridge_readfn,
  2153 + omap_tipb_bridge_writefn, s);
  2154 + cpu_register_physical_memory(s->base, 0x100, iomemtype);
  2155 +
  2156 + return s;
  2157 +}
  2158 +
  2159 +/* Dummy Traffic Controller's Memory Interface */
  2160 +static uint32_t omap_tcmi_read(void *opaque, target_phys_addr_t addr)
  2161 +{
  2162 + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
  2163 + int offset = addr - s->tcmi_base;
  2164 + uint32_t ret;
  2165 +
  2166 + switch (offset) {
  2167 + case 0xfffecc00: /* IMIF_PRIO */
  2168 + case 0xfffecc04: /* EMIFS_PRIO */
  2169 + case 0xfffecc08: /* EMIFF_PRIO */
  2170 + case 0xfffecc0c: /* EMIFS_CONFIG */
  2171 + case 0xfffecc10: /* EMIFS_CS0_CONFIG */
  2172 + case 0xfffecc14: /* EMIFS_CS1_CONFIG */
  2173 + case 0xfffecc18: /* EMIFS_CS2_CONFIG */
  2174 + case 0xfffecc1c: /* EMIFS_CS3_CONFIG */
  2175 + case 0xfffecc24: /* EMIFF_MRS */
  2176 + case 0xfffecc28: /* TIMEOUT1 */
  2177 + case 0xfffecc2c: /* TIMEOUT2 */
  2178 + case 0xfffecc30: /* TIMEOUT3 */
  2179 + case 0xfffecc3c: /* EMIFF_SDRAM_CONFIG_2 */
  2180 + case 0xfffecc40: /* EMIFS_CFG_DYN_WAIT */
  2181 + return s->tcmi_regs[offset >> 2];
  2182 +
  2183 + case 0xfffecc20: /* EMIFF_SDRAM_CONFIG */
  2184 + ret = s->tcmi_regs[offset >> 2];
  2185 + s->tcmi_regs[offset >> 2] &= ~1; /* XXX: Clear SLRF on SDRAM access */
  2186 + /* XXX: We can try using the VGA_DIRTY flag for this */
  2187 + return ret;
  2188 + }
  2189 +
  2190 + OMAP_BAD_REG(addr);
  2191 + return 0;
  2192 +}
  2193 +
  2194 +static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
  2195 + uint32_t value)
  2196 +{
  2197 + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
  2198 + int offset = addr - s->tcmi_base;
  2199 +
  2200 + switch (offset) {
  2201 + case 0xfffecc00: /* IMIF_PRIO */
  2202 + case 0xfffecc04: /* EMIFS_PRIO */
  2203 + case 0xfffecc08: /* EMIFF_PRIO */
  2204 + case 0xfffecc10: /* EMIFS_CS0_CONFIG */
  2205 + case 0xfffecc14: /* EMIFS_CS1_CONFIG */
  2206 + case 0xfffecc18: /* EMIFS_CS2_CONFIG */
  2207 + case 0xfffecc1c: /* EMIFS_CS3_CONFIG */
  2208 + case 0xfffecc20: /* EMIFF_SDRAM_CONFIG */
  2209 + case 0xfffecc24: /* EMIFF_MRS */
  2210 + case 0xfffecc28: /* TIMEOUT1 */
  2211 + case 0xfffecc2c: /* TIMEOUT2 */
  2212 + case 0xfffecc30: /* TIMEOUT3 */
  2213 + case 0xfffecc3c: /* EMIFF_SDRAM_CONFIG_2 */
  2214 + case 0xfffecc40: /* EMIFS_CFG_DYN_WAIT */
  2215 + s->tcmi_regs[offset >> 2] = value;
  2216 + break;
  2217 + case 0xfffecc0c: /* EMIFS_CONFIG */
  2218 + s->tcmi_regs[offset >> 2] = (value & 0xf) | (1 << 4);
  2219 + break;
  2220 +
  2221 + default:
  2222 + OMAP_BAD_REG(addr);
  2223 + }
  2224 +}
  2225 +
  2226 +static CPUReadMemoryFunc *omap_tcmi_readfn[] = {
  2227 + omap_badwidth_read32,
  2228 + omap_badwidth_read32,
  2229 + omap_tcmi_read,
  2230 +};
  2231 +
  2232 +static CPUWriteMemoryFunc *omap_tcmi_writefn[] = {
  2233 + omap_badwidth_write32,
  2234 + omap_badwidth_write32,
  2235 + omap_tcmi_write,
  2236 +};
  2237 +
  2238 +static void omap_tcmi_reset(struct omap_mpu_state_s *mpu)
  2239 +{
  2240 + mpu->tcmi_regs[0x00 >> 2] = 0x00000000;
  2241 + mpu->tcmi_regs[0x04 >> 2] = 0x00000000;
  2242 + mpu->tcmi_regs[0x08 >> 2] = 0x00000000;
  2243 + mpu->tcmi_regs[0x0c >> 2] = 0x00000010;
  2244 + mpu->tcmi_regs[0x10 >> 2] = 0x0010fffb;
  2245 + mpu->tcmi_regs[0x14 >> 2] = 0x0010fffb;
  2246 + mpu->tcmi_regs[0x18 >> 2] = 0x0010fffb;
  2247 + mpu->tcmi_regs[0x1c >> 2] = 0x0010fffb;
  2248 + mpu->tcmi_regs[0x20 >> 2] = 0x00618800;
  2249 + mpu->tcmi_regs[0x24 >> 2] = 0x00000037;
  2250 + mpu->tcmi_regs[0x28 >> 2] = 0x00000000;
  2251 + mpu->tcmi_regs[0x2c >> 2] = 0x00000000;
  2252 + mpu->tcmi_regs[0x30 >> 2] = 0x00000000;
  2253 + mpu->tcmi_regs[0x3c >> 2] = 0x00000003;
  2254 + mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
  2255 +}
  2256 +
  2257 +static void omap_tcmi_init(target_phys_addr_t base,
  2258 + struct omap_mpu_state_s *mpu)
  2259 +{
  2260 + int iomemtype = cpu_register_io_memory(0, omap_tcmi_readfn,
  2261 + omap_tcmi_writefn, mpu);
  2262 +
  2263 + mpu->tcmi_base = base;
  2264 + cpu_register_physical_memory(mpu->tcmi_base, 0x100, iomemtype);
  2265 + omap_tcmi_reset(mpu);
  2266 +}
  2267 +
  2268 +/* Digital phase-locked loops control */
  2269 +static uint32_t omap_dpll_read(void *opaque, target_phys_addr_t addr)
  2270 +{
  2271 + struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
  2272 + int offset = addr - s->base;
  2273 +
  2274 + if (offset == 0x00) /* CTL_REG */
  2275 + return s->mode;
  2276 +
  2277 + OMAP_BAD_REG(addr);
  2278 + return 0;
  2279 +}
  2280 +
  2281 +static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
  2282 + uint32_t value)
  2283 +{
  2284 + struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
  2285 + uint16_t diff;
  2286 + int offset = addr - s->base;
  2287 + static const int bypass_div[4] = { 1, 2, 4, 4 };
  2288 + int div, mult;
  2289 +
  2290 + if (offset == 0x00) { /* CTL_REG */
  2291 + /* See omap_ulpd_pm_write() too */
  2292 + diff = s->mode & value;
  2293 + s->mode = value & 0x2fff;
  2294 + if (diff & (0x3ff << 2)) {
  2295 + if (value & (1 << 4)) { /* PLL_ENABLE */
  2296 + div = ((value >> 5) & 3) + 1; /* PLL_DIV */
  2297 + mult = MIN((value >> 7) & 0x1f, 1); /* PLL_MULT */
  2298 + } else {
  2299 + div = bypass_div[((value >> 2) & 3)]; /* BYPASS_DIV */
  2300 + mult = 1;
  2301 + }
  2302 + omap_clk_setrate(s->dpll, div, mult);
  2303 + }
  2304 +
  2305 + /* Enter the desired mode. */
  2306 + s->mode = (s->mode & 0xfffe) | ((s->mode >> 4) & 1);
  2307 +
  2308 + /* Act as if the lock is restored. */
  2309 + s->mode |= 2;
  2310 + } else {
  2311 + OMAP_BAD_REG(addr);
  2312 + }
  2313 +}
  2314 +
  2315 +static CPUReadMemoryFunc *omap_dpll_readfn[] = {
  2316 + omap_badwidth_read16,
  2317 + omap_dpll_read,
  2318 + omap_badwidth_read16,
  2319 +};
  2320 +
  2321 +static CPUWriteMemoryFunc *omap_dpll_writefn[] = {
  2322 + omap_badwidth_write16,
  2323 + omap_dpll_write,
  2324 + omap_badwidth_write16,
  2325 +};
  2326 +
  2327 +static void omap_dpll_reset(struct dpll_ctl_s *s)
  2328 +{
  2329 + s->mode = 0x2002;
  2330 + omap_clk_setrate(s->dpll, 1, 1);
  2331 +}
  2332 +
  2333 +static void omap_dpll_init(struct dpll_ctl_s *s, target_phys_addr_t base,
  2334 + omap_clk clk)
  2335 +{
  2336 + int iomemtype = cpu_register_io_memory(0, omap_dpll_readfn,
  2337 + omap_dpll_writefn, s);
  2338 +
  2339 + s->base = base;
  2340 + s->dpll = clk;
  2341 + omap_dpll_reset(s);
  2342 +
  2343 + cpu_register_physical_memory(s->base, 0x100, iomemtype);
  2344 +}
  2345 +
  2346 +/* UARTs */
  2347 +struct omap_uart_s {
  2348 + SerialState *serial; /* TODO */
  2349 +};
  2350 +
  2351 +static void omap_uart_reset(struct omap_uart_s *s)
  2352 +{
  2353 +}
  2354 +
  2355 +struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
  2356 + qemu_irq irq, omap_clk clk, CharDriverState *chr)
  2357 +{
  2358 + struct omap_uart_s *s = (struct omap_uart_s *)
  2359 + qemu_mallocz(sizeof(struct omap_uart_s));
  2360 + if (chr)
  2361 + s->serial = serial_mm_init(base, 2, irq, chr, 1);
  2362 + return s;
  2363 +}
  2364 +
  2365 +/* MPU Clock/Reset/Power Mode Control */
  2366 +static uint32_t omap_clkm_read(void *opaque, target_phys_addr_t addr)
  2367 +{
  2368 + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
  2369 + int offset = addr - s->clkm.mpu_base;
  2370 +
  2371 + switch (offset) {
  2372 + case 0x00: /* ARM_CKCTL */
  2373 + return s->clkm.arm_ckctl;
  2374 +
  2375 + case 0x04: /* ARM_IDLECT1 */
  2376 + return s->clkm.arm_idlect1;
  2377 +
  2378 + case 0x08: /* ARM_IDLECT2 */
  2379 + return s->clkm.arm_idlect2;
  2380 +
  2381 + case 0x0c: /* ARM_EWUPCT */
  2382 + return s->clkm.arm_ewupct;
  2383 +
  2384 + case 0x10: /* ARM_RSTCT1 */
  2385 + return s->clkm.arm_rstct1;
  2386 +
  2387 + case 0x14: /* ARM_RSTCT2 */
  2388 + return s->clkm.arm_rstct2;
  2389 +
  2390 + case 0x18: /* ARM_SYSST */
  2391 + return (s->clkm.clocking_scheme < 11) | s->clkm.cold_start;
  2392 +
  2393 + case 0x1c: /* ARM_CKOUT1 */
  2394 + return s->clkm.arm_ckout1;
  2395 +
  2396 + case 0x20: /* ARM_CKOUT2 */
  2397 + break;
  2398 + }
  2399 +
  2400 + OMAP_BAD_REG(addr);
  2401 + return 0;
  2402 +}
  2403 +
  2404 +static inline void omap_clkm_ckctl_update(struct omap_mpu_state_s *s,
  2405 + uint16_t diff, uint16_t value)
  2406 +{
  2407 + omap_clk clk;
  2408 +
  2409 + if (diff & (1 << 14)) { /* ARM_INTHCK_SEL */
  2410 + if (value & (1 << 14))
  2411 + /* Reserved */;
  2412 + else {
  2413 + clk = omap_findclk(s, "arminth_ck");
  2414 + omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
  2415 + }
  2416 + }
  2417 + if (diff & (1 << 12)) { /* ARM_TIMXO */
  2418 + clk = omap_findclk(s, "armtim_ck");
  2419 + if (value & (1 << 12))
  2420 + omap_clk_reparent(clk, omap_findclk(s, "clkin"));
  2421 + else
  2422 + omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
  2423 + }
  2424 + /* XXX: en_dspck */
  2425 + if (diff & (3 << 10)) { /* DSPMMUDIV */
  2426 + clk = omap_findclk(s, "dspmmu_ck");
  2427 + omap_clk_setrate(clk, 1 << ((value >> 10) & 3), 1);
  2428 + }
  2429 + if (diff & (3 << 8)) { /* TCDIV */
  2430 + clk = omap_findclk(s, "tc_ck");
  2431 + omap_clk_setrate(clk, 1 << ((value >> 8) & 3), 1);
  2432 + }
  2433 + if (diff & (3 << 6)) { /* DSPDIV */
  2434 + clk = omap_findclk(s, "dsp_ck");
  2435 + omap_clk_setrate(clk, 1 << ((value >> 6) & 3), 1);
  2436 + }
  2437 + if (diff & (3 << 4)) { /* ARMDIV */
  2438 + clk = omap_findclk(s, "arm_ck");
  2439 + omap_clk_setrate(clk, 1 << ((value >> 4) & 3), 1);
  2440 + }
  2441 + if (diff & (3 << 2)) { /* LCDDIV */
  2442 + clk = omap_findclk(s, "lcd_ck");
  2443 + omap_clk_setrate(clk, 1 << ((value >> 2) & 3), 1);
  2444 + }
  2445 + if (diff & (3 << 0)) { /* PERDIV */
  2446 + clk = omap_findclk(s, "armper_ck");
  2447 + omap_clk_setrate(clk, 1 << ((value >> 0) & 3), 1);
  2448 + }
  2449 +}
  2450 +
  2451 +static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s,
  2452 + uint16_t diff, uint16_t value)
  2453 +{
  2454 + omap_clk clk;
  2455 +
  2456 + if (value & (1 << 11)) /* SETARM_IDLE */
  2457 + cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
  2458 + if (!(value & (1 << 10))) /* WKUP_MODE */
  2459 + qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
  2460 +
  2461 +#define SET_CANIDLE(clock, bit) \
  2462 + if (diff & (1 << bit)) { \
  2463 + clk = omap_findclk(s, clock); \
  2464 + omap_clk_canidle(clk, (value >> bit) & 1); \
  2465 + }
  2466 + SET_CANIDLE("mpuwd_ck", 0) /* IDLWDT_ARM */
  2467 + SET_CANIDLE("armxor_ck", 1) /* IDLXORP_ARM */
  2468 + SET_CANIDLE("mpuper_ck", 2) /* IDLPER_ARM */
  2469 + SET_CANIDLE("lcd_ck", 3) /* IDLLCD_ARM */
  2470 + SET_CANIDLE("lb_ck", 4) /* IDLLB_ARM */
  2471 + SET_CANIDLE("hsab_ck", 5) /* IDLHSAB_ARM */
  2472 + SET_CANIDLE("tipb_ck", 6) /* IDLIF_ARM */
  2473 + SET_CANIDLE("dma_ck", 6) /* IDLIF_ARM */
  2474 + SET_CANIDLE("tc_ck", 6) /* IDLIF_ARM */
  2475 + SET_CANIDLE("dpll1", 7) /* IDLDPLL_ARM */
  2476 + SET_CANIDLE("dpll2", 7) /* IDLDPLL_ARM */
  2477 + SET_CANIDLE("dpll3", 7) /* IDLDPLL_ARM */
  2478 + SET_CANIDLE("mpui_ck", 8) /* IDLAPI_ARM */
  2479 + SET_CANIDLE("armtim_ck", 9) /* IDLTIM_ARM */
  2480 +}
  2481 +
  2482 +static inline void omap_clkm_idlect2_update(struct omap_mpu_state_s *s,
  2483 + uint16_t diff, uint16_t value)
  2484 +{
  2485 + omap_clk clk;
  2486 +
  2487 +#define SET_ONOFF(clock, bit) \
  2488 + if (diff & (1 << bit)) { \
  2489 + clk = omap_findclk(s, clock); \
  2490 + omap_clk_onoff(clk, (value >> bit) & 1); \
  2491 + }
  2492 + SET_ONOFF("mpuwd_ck", 0) /* EN_WDTCK */
  2493 + SET_ONOFF("armxor_ck", 1) /* EN_XORPCK */
  2494 + SET_ONOFF("mpuper_ck", 2) /* EN_PERCK */
  2495 + SET_ONOFF("lcd_ck", 3) /* EN_LCDCK */
  2496 + SET_ONOFF("lb_ck", 4) /* EN_LBCK */
  2497 + SET_ONOFF("hsab_ck", 5) /* EN_HSABCK */
  2498 + SET_ONOFF("mpui_ck", 6) /* EN_APICK */
  2499 + SET_ONOFF("armtim_ck", 7) /* EN_TIMCK */
  2500 + SET_CANIDLE("dma_ck", 8) /* DMACK_REQ */
  2501 + SET_ONOFF("arm_gpio_ck", 9) /* EN_GPIOCK */
  2502 + SET_ONOFF("lbfree_ck", 10) /* EN_LBFREECK */
  2503 +}
  2504 +
  2505 +static inline void omap_clkm_ckout1_update(struct omap_mpu_state_s *s,
  2506 + uint16_t diff, uint16_t value)
  2507 +{
  2508 + omap_clk clk;
  2509 +
  2510 + if (diff & (3 << 4)) { /* TCLKOUT */
  2511 + clk = omap_findclk(s, "tclk_out");
  2512 + switch ((value >> 4) & 3) {
  2513 + case 1:
  2514 + omap_clk_reparent(clk, omap_findclk(s, "ck_gen3"));
  2515 + omap_clk_onoff(clk, 1);
  2516 + break;
  2517 + case 2:
  2518 + omap_clk_reparent(clk, omap_findclk(s, "tc_ck"));
  2519 + omap_clk_onoff(clk, 1);
  2520 + break;
  2521 + default:
  2522 + omap_clk_onoff(clk, 0);
  2523 + }
  2524 + }
  2525 + if (diff & (3 << 2)) { /* DCLKOUT */
  2526 + clk = omap_findclk(s, "dclk_out");
  2527 + switch ((value >> 2) & 3) {
  2528 + case 0:
  2529 + omap_clk_reparent(clk, omap_findclk(s, "dspmmu_ck"));
  2530 + break;
  2531 + case 1:
  2532 + omap_clk_reparent(clk, omap_findclk(s, "ck_gen2"));
  2533 + break;
  2534 + case 2:
  2535 + omap_clk_reparent(clk, omap_findclk(s, "dsp_ck"));
  2536 + break;
  2537 + case 3:
  2538 + omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
  2539 + break;
  2540 + }
  2541 + }
  2542 + if (diff & (3 << 0)) { /* ACLKOUT */
  2543 + clk = omap_findclk(s, "aclk_out");
  2544 + switch ((value >> 0) & 3) {
  2545 + case 1:
  2546 + omap_clk_reparent(clk, omap_findclk(s, "ck_gen1"));
  2547 + omap_clk_onoff(clk, 1);
  2548 + break;
  2549 + case 2:
  2550 + omap_clk_reparent(clk, omap_findclk(s, "arm_ck"));
  2551 + omap_clk_onoff(clk, 1);
  2552 + break;
  2553 + case 3:
  2554 + omap_clk_reparent(clk, omap_findclk(s, "ck_ref14"));
  2555 + omap_clk_onoff(clk, 1);
  2556 + break;
  2557 + default:
  2558 + omap_clk_onoff(clk, 0);
  2559 + }
  2560 + }
  2561 +}
  2562 +
  2563 +static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
  2564 + uint32_t value)
  2565 +{
  2566 + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
  2567 + int offset = addr - s->clkm.mpu_base;
  2568 + uint16_t diff;
  2569 + omap_clk clk;
  2570 + static const char *clkschemename[8] = {
  2571 + "fully synchronous", "fully asynchronous", "synchronous scalable",
  2572 + "mix mode 1", "mix mode 2", "bypass mode", "mix mode 3", "mix mode 4",
  2573 + };
  2574 +
  2575 + switch (offset) {
  2576 + case 0x00: /* ARM_CKCTL */
  2577 + diff = s->clkm.arm_ckctl ^ value;
  2578 + s->clkm.arm_ckctl = value & 0x7fff;
  2579 + omap_clkm_ckctl_update(s, diff, value);
  2580 + return;
  2581 +
  2582 + case 0x04: /* ARM_IDLECT1 */
  2583 + diff = s->clkm.arm_idlect1 ^ value;
  2584 + s->clkm.arm_idlect1 = value & 0x0fff;
  2585 + omap_clkm_idlect1_update(s, diff, value);
  2586 + return;
  2587 +
  2588 + case 0x08: /* ARM_IDLECT2 */
  2589 + diff = s->clkm.arm_idlect2 ^ value;
  2590 + s->clkm.arm_idlect2 = value & 0x07ff;
  2591 + omap_clkm_idlect2_update(s, diff, value);
  2592 + return;
  2593 +
  2594 + case 0x0c: /* ARM_EWUPCT */
  2595 + diff = s->clkm.arm_ewupct ^ value;
  2596 + s->clkm.arm_ewupct = value & 0x003f;
  2597 + return;
  2598 +
  2599 + case 0x10: /* ARM_RSTCT1 */
  2600 + diff = s->clkm.arm_rstct1 ^ value;
  2601 + s->clkm.arm_rstct1 = value & 0x0007;
  2602 + if (value & 9) {
  2603 + qemu_system_reset_request();
  2604 + s->clkm.cold_start = 0xa;
  2605 + }
  2606 + if (diff & ~value & 4) { /* DSP_RST */
  2607 + omap_mpui_reset(s);
  2608 + omap_tipb_bridge_reset(s->private_tipb);
  2609 + omap_tipb_bridge_reset(s->public_tipb);
  2610 + }
  2611 + if (diff & 2) { /* DSP_EN */
  2612 + clk = omap_findclk(s, "dsp_ck");
  2613 + omap_clk_canidle(clk, (~value >> 1) & 1);
  2614 + }
  2615 + return;
  2616 +
  2617 + case 0x14: /* ARM_RSTCT2 */
  2618 + s->clkm.arm_rstct2 = value & 0x0001;
  2619 + return;
  2620 +
  2621 + case 0x18: /* ARM_SYSST */
  2622 + if ((s->clkm.clocking_scheme ^ (value >> 11)) & 7) {
  2623 + s->clkm.clocking_scheme = (value >> 11) & 7;
  2624 + printf("%s: clocking scheme set to %s\n", __FUNCTION__,
  2625 + clkschemename[s->clkm.clocking_scheme]);
  2626 + }
  2627 + s->clkm.cold_start &= value & 0x3f;
  2628 + return;
  2629 +
  2630 + case 0x1c: /* ARM_CKOUT1 */
  2631 + diff = s->clkm.arm_ckout1 ^ value;
  2632 + s->clkm.arm_ckout1 = value & 0x003f;
  2633 + omap_clkm_ckout1_update(s, diff, value);
  2634 + return;
  2635 +
  2636 + case 0x20: /* ARM_CKOUT2 */
  2637 + default:
  2638 + OMAP_BAD_REG(addr);
  2639 + }
  2640 +}
  2641 +
  2642 +static CPUReadMemoryFunc *omap_clkm_readfn[] = {
  2643 + omap_badwidth_read16,
  2644 + omap_clkm_read,
  2645 + omap_badwidth_read16,
  2646 +};
  2647 +
  2648 +static CPUWriteMemoryFunc *omap_clkm_writefn[] = {
  2649 + omap_badwidth_write16,
  2650 + omap_clkm_write,
  2651 + omap_badwidth_write16,
  2652 +};
  2653 +
  2654 +static uint32_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr)
  2655 +{
  2656 + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
  2657 + int offset = addr - s->clkm.dsp_base;
  2658 +
  2659 + switch (offset) {
  2660 + case 0x04: /* DSP_IDLECT1 */
  2661 + return s->clkm.dsp_idlect1;
  2662 +
  2663 + case 0x08: /* DSP_IDLECT2 */
  2664 + return s->clkm.dsp_idlect2;
  2665 +
  2666 + case 0x14: /* DSP_RSTCT2 */
  2667 + return s->clkm.dsp_rstct2;
  2668 +
  2669 + case 0x18: /* DSP_SYSST */
  2670 + return (s->clkm.clocking_scheme < 11) | s->clkm.cold_start |
  2671 + (s->env->halted << 6); /* Quite useless... */
  2672 + }
  2673 +
  2674 + OMAP_BAD_REG(addr);
  2675 + return 0;
  2676 +}
  2677 +
  2678 +static inline void omap_clkdsp_idlect1_update(struct omap_mpu_state_s *s,
  2679 + uint16_t diff, uint16_t value)
  2680 +{
  2681 + omap_clk clk;
  2682 +
  2683 + SET_CANIDLE("dspxor_ck", 1); /* IDLXORP_DSP */
  2684 +}
  2685 +
  2686 +static inline void omap_clkdsp_idlect2_update(struct omap_mpu_state_s *s,
  2687 + uint16_t diff, uint16_t value)
  2688 +{
  2689 + omap_clk clk;
  2690 +
  2691 + SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
  2692 +}
  2693 +
  2694 +static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
  2695 + uint32_t value)
  2696 +{
  2697 + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
  2698 + int offset = addr - s->clkm.dsp_base;
  2699 + uint16_t diff;
  2700 +
  2701 + switch (offset) {
  2702 + case 0x04: /* DSP_IDLECT1 */
  2703 + diff = s->clkm.dsp_idlect1 ^ value;
  2704 + s->clkm.dsp_idlect1 = value & 0x01f7;
  2705 + omap_clkdsp_idlect1_update(s, diff, value);
  2706 + break;
  2707 +
  2708 + case 0x08: /* DSP_IDLECT2 */
  2709 + s->clkm.dsp_idlect2 = value & 0x0037;
  2710 + diff = s->clkm.dsp_idlect1 ^ value;
  2711 + omap_clkdsp_idlect2_update(s, diff, value);
  2712 + break;
  2713 +
  2714 + case 0x14: /* DSP_RSTCT2 */
  2715 + s->clkm.dsp_rstct2 = value & 0x0001;
  2716 + break;
  2717 +
  2718 + case 0x18: /* DSP_SYSST */
  2719 + s->clkm.cold_start &= value & 0x3f;
  2720 + break;
  2721 +
  2722 + default:
  2723 + OMAP_BAD_REG(addr);
  2724 + }
  2725 +}
  2726 +
  2727 +static CPUReadMemoryFunc *omap_clkdsp_readfn[] = {
  2728 + omap_badwidth_read16,
  2729 + omap_clkdsp_read,
  2730 + omap_badwidth_read16,
  2731 +};
  2732 +
  2733 +static CPUWriteMemoryFunc *omap_clkdsp_writefn[] = {
  2734 + omap_badwidth_write16,
  2735 + omap_clkdsp_write,
  2736 + omap_badwidth_write16,
  2737 +};
  2738 +
  2739 +static void omap_clkm_reset(struct omap_mpu_state_s *s)
  2740 +{
  2741 + if (s->wdt && s->wdt->reset)
  2742 + s->clkm.cold_start = 0x6;
  2743 + s->clkm.clocking_scheme = 0;
  2744 + omap_clkm_ckctl_update(s, ~0, 0x3000);
  2745 + s->clkm.arm_ckctl = 0x3000;
  2746 + omap_clkm_idlect1_update(s, s->clkm.arm_idlect1 & 0x0400, 0x0400);
  2747 + s->clkm.arm_idlect1 = 0x0400;
  2748 + omap_clkm_idlect2_update(s, s->clkm.arm_idlect2 & 0x0100, 0x0100);
  2749 + s->clkm.arm_idlect2 = 0x0100;
  2750 + s->clkm.arm_ewupct = 0x003f;
  2751 + s->clkm.arm_rstct1 = 0x0000;
  2752 + s->clkm.arm_rstct2 = 0x0000;
  2753 + s->clkm.arm_ckout1 = 0x0015;
  2754 + s->clkm.dpll1_mode = 0x2002;
  2755 + omap_clkdsp_idlect1_update(s, s->clkm.dsp_idlect1 ^ 0x0040, 0x0040);
  2756 + s->clkm.dsp_idlect1 = 0x0040;
  2757 + omap_clkdsp_idlect2_update(s, ~0, 0x0000);
  2758 + s->clkm.dsp_idlect2 = 0x0000;
  2759 + s->clkm.dsp_rstct2 = 0x0000;
  2760 +}
  2761 +
  2762 +static void omap_clkm_init(target_phys_addr_t mpu_base,
  2763 + target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
  2764 +{
  2765 + int iomemtype[2] = {
  2766 + cpu_register_io_memory(0, omap_clkm_readfn, omap_clkm_writefn, s),
  2767 + cpu_register_io_memory(0, omap_clkdsp_readfn, omap_clkdsp_writefn, s),
  2768 + };
  2769 +
  2770 + s->clkm.mpu_base = mpu_base;
  2771 + s->clkm.dsp_base = dsp_base;
  2772 + s->clkm.cold_start = 0x3a;
  2773 + omap_clkm_reset(s);
  2774 +
  2775 + cpu_register_physical_memory(s->clkm.mpu_base, 0x100, iomemtype[0]);
  2776 + cpu_register_physical_memory(s->clkm.dsp_base, 0x1000, iomemtype[1]);
  2777 +}
  2778 +
  2779 +/* General chip reset */
  2780 +static void omap_mpu_reset(void *opaque)
  2781 +{
  2782 + struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
  2783 +
  2784 + omap_clkm_reset(mpu);
  2785 + omap_inth_reset(mpu->ih[0]);
  2786 + omap_inth_reset(mpu->ih[1]);
  2787 + omap_dma_reset(mpu->dma);
  2788 + omap_mpu_timer_reset(mpu->timer[0]);
  2789 + omap_mpu_timer_reset(mpu->timer[1]);
  2790 + omap_mpu_timer_reset(mpu->timer[2]);
  2791 + omap_wd_timer_reset(mpu->wdt);
  2792 + omap_os_timer_reset(mpu->os_timer);
  2793 + omap_lcdc_reset(mpu->lcd);
  2794 + omap_ulpd_pm_reset(mpu);
  2795 + omap_pin_cfg_reset(mpu);
  2796 + omap_mpui_reset(mpu);
  2797 + omap_tipb_bridge_reset(mpu->private_tipb);
  2798 + omap_tipb_bridge_reset(mpu->public_tipb);
  2799 + omap_dpll_reset(&mpu->dpll[0]);
  2800 + omap_dpll_reset(&mpu->dpll[1]);
  2801 + omap_dpll_reset(&mpu->dpll[2]);
  2802 + omap_uart_reset(mpu->uart1);
  2803 + omap_uart_reset(mpu->uart2);
  2804 + omap_uart_reset(mpu->uart3);
  2805 + cpu_reset(mpu->env);
  2806 +}
  2807 +
  2808 +static void omap_mpu_wakeup(void *opaque, int irq, int req)
  2809 +{
  2810 + struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
  2811 +
  2812 + cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB);
  2813 +}
  2814 +
  2815 +struct omap_mpu_state_s *omap310_mpu_init(unsigned long sdram_size,
  2816 + DisplayState *ds, const char *core)
  2817 +{
  2818 + struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
  2819 + qemu_mallocz(sizeof(struct omap_mpu_state_s));
  2820 + ram_addr_t imif_base, emiff_base;
  2821 +
  2822 + /* Core */
  2823 + s->mpu_model = omap310;
  2824 + s->env = cpu_init();
  2825 + s->sdram_size = sdram_size;
  2826 + s->sram_size = OMAP15XX_SRAM_SIZE;
  2827 +
  2828 + cpu_arm_set_model(s->env, core ?: "ti925t");
  2829 +
  2830 + /* Clocks */
  2831 + omap_clk_init(s);
  2832 +
  2833 + /* Memory-mapped stuff */
  2834 + cpu_register_physical_memory(OMAP_EMIFF_BASE, s->sdram_size,
  2835 + (emiff_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
  2836 + cpu_register_physical_memory(OMAP_IMIF_BASE, s->sram_size,
  2837 + (imif_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
  2838 +
  2839 + omap_clkm_init(0xfffece00, 0xe1008000, s);
  2840 +
  2841 + s->ih[0] = omap_inth_init(0xfffecb00, 0x100,
  2842 + arm_pic_init_cpu(s->env),
  2843 + omap_findclk(s, "arminth_ck"));
  2844 + s->ih[1] = omap_inth_init(0xfffe0000, 0x800,
  2845 + &s->ih[0]->pins[OMAP_INT_15XX_IH2_IRQ],
  2846 + omap_findclk(s, "arminth_ck"));
  2847 + s->irq[0] = s->ih[0]->pins;
  2848 + s->irq[1] = s->ih[1]->pins;
  2849 +
  2850 + s->dma = omap_dma_init(0xfffed800, s->irq[0], s,
  2851 + omap_findclk(s, "dma_ck"));
  2852 + s->port[emiff ].addr_valid = omap_validate_emiff_addr;
  2853 + s->port[emifs ].addr_valid = omap_validate_emifs_addr;
  2854 + s->port[imif ].addr_valid = omap_validate_imif_addr;
  2855 + s->port[tipb ].addr_valid = omap_validate_tipb_addr;
  2856 + s->port[local ].addr_valid = omap_validate_local_addr;
  2857 + s->port[tipb_mpui].addr_valid = omap_validate_tipb_mpui_addr;
  2858 +
  2859 + s->timer[0] = omap_mpu_timer_init(0xfffec500,
  2860 + s->irq[0][OMAP_INT_TIMER1],
  2861 + omap_findclk(s, "mputim_ck"));
  2862 + s->timer[1] = omap_mpu_timer_init(0xfffec600,
  2863 + s->irq[0][OMAP_INT_TIMER2],
  2864 + omap_findclk(s, "mputim_ck"));
  2865 + s->timer[2] = omap_mpu_timer_init(0xfffec700,
  2866 + s->irq[0][OMAP_INT_TIMER3],
  2867 + omap_findclk(s, "mputim_ck"));
  2868 +
  2869 + s->wdt = omap_wd_timer_init(0xfffec800,
  2870 + s->irq[0][OMAP_INT_WD_TIMER],
  2871 + omap_findclk(s, "armwdt_ck"));
  2872 +
  2873 + s->os_timer = omap_os_timer_init(0xfffb9000,
  2874 + s->irq[1][OMAP_INT_OS_TIMER],
  2875 + omap_findclk(s, "clk32-kHz"));
  2876 +
  2877 + s->lcd = omap_lcdc_init(0xfffec000, s->irq[0][OMAP_INT_LCD_CTRL],
  2878 + &s->dma->lcd_ch, ds, imif_base, emiff_base,
  2879 + omap_findclk(s, "lcd_ck"));
  2880 +
  2881 + omap_ulpd_pm_init(0xfffe0800, s);
  2882 + omap_pin_cfg_init(0xfffe1000, s);
  2883 + omap_id_init(s);
  2884 +
  2885 + omap_mpui_init(0xfffec900, s);
  2886 +
  2887 + s->private_tipb = omap_tipb_bridge_init(0xfffeca00,
  2888 + s->irq[0][OMAP_INT_BRIDGE_PRIV],
  2889 + omap_findclk(s, "tipb_ck"));
  2890 + s->public_tipb = omap_tipb_bridge_init(0xfffed300,
  2891 + s->irq[0][OMAP_INT_BRIDGE_PUB],
  2892 + omap_findclk(s, "tipb_ck"));
  2893 +
  2894 + omap_tcmi_init(0xfffecc00, s);
  2895 +
  2896 + s->uart1 = omap_uart_init(0xfffb0000, s->irq[1][OMAP_INT_UART1],
  2897 + omap_findclk(s, "uart1_ck"),
  2898 + serial_hds[0]);
  2899 + s->uart2 = omap_uart_init(0xfffb0800, s->irq[1][OMAP_INT_UART2],
  2900 + omap_findclk(s, "uart2_ck"),
  2901 + serial_hds[0] ? serial_hds[1] : 0);
  2902 + s->uart3 = omap_uart_init(0xe1019800, s->irq[0][OMAP_INT_UART3],
  2903 + omap_findclk(s, "uart3_ck"),
  2904 + serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0);
  2905 +
  2906 + omap_dpll_init(&s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
  2907 + omap_dpll_init(&s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
  2908 + omap_dpll_init(&s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
  2909 +
  2910 + qemu_register_reset(omap_mpu_reset, s);
  2911 + s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
  2912 +
  2913 + return s;
  2914 +}
... ...
hw/omap.h 0 → 100644
  View file @c3d2689
  1 +/*
  2 + * Texas Instruments OMAP processors.
  3 + *
  4 + * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
  5 + *
  6 + * This program is free software; you can redistribute it and/or
  7 + * modify it under the terms of the GNU General Public License as
  8 + * published by the Free Software Foundation; either version 2 of
  9 + * the License, or (at your option) any later version.
  10 + *
  11 + * This program is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 + * GNU General Public License for more details.
  15 + *
  16 + * You should have received a copy of the GNU General Public License
  17 + * along with this program; if not, write to the Free Software
  18 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19 + * MA 02111-1307 USA
  20 + */
  21 +#ifndef hw_omap_h
  22 +# define hw_omap_h "omap.h"
  23 +
  24 +# define OMAP_EMIFS_BASE 0x00000000
  25 +# define OMAP_CS0_BASE 0x00000000
  26 +# define OMAP_CS1_BASE 0x04000000
  27 +# define OMAP_CS2_BASE 0x08000000
  28 +# define OMAP_CS3_BASE 0x0c000000
  29 +# define OMAP_EMIFF_BASE 0x10000000
  30 +# define OMAP_IMIF_BASE 0x20000000
  31 +# define OMAP_LOCALBUS_BASE 0x30000000
  32 +# define OMAP_MPUI_BASE 0xe1000000
  33 +
  34 +# define OMAP730_SRAM_SIZE 0x00032000
  35 +# define OMAP15XX_SRAM_SIZE 0x00030000
  36 +# define OMAP16XX_SRAM_SIZE 0x00004000
  37 +# define OMAP1611_SRAM_SIZE 0x0003e800
  38 +# define OMAP_CS0_SIZE 0x04000000
  39 +# define OMAP_CS1_SIZE 0x04000000
  40 +# define OMAP_CS2_SIZE 0x04000000
  41 +# define OMAP_CS3_SIZE 0x04000000
  42 +
  43 +/* omap1_clk.c */
  44 +struct omap_mpu_state_s;
  45 +typedef struct clk *omap_clk;
  46 +omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name);
  47 +void omap_clk_init(struct omap_mpu_state_s *mpu);
  48 +void omap_clk_adduser(struct clk *clk, qemu_irq user);
  49 +void omap_clk_get(omap_clk clk);
  50 +void omap_clk_put(omap_clk clk);
  51 +void omap_clk_onoff(omap_clk clk, int on);
  52 +void omap_clk_canidle(omap_clk clk, int can);
  53 +void omap_clk_setrate(omap_clk clk, int divide, int multiply);
  54 +int64_t omap_clk_getrate(omap_clk clk);
  55 +void omap_clk_reparent(omap_clk clk, omap_clk parent);
  56 +
  57 +/* omap.c */
  58 +struct omap_intr_handler_s;
  59 +struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
  60 + unsigned long size, qemu_irq parent[2], omap_clk clk);
  61 +
  62 +/*
  63 + * Common IRQ numbers for level 1 interrupt handler
  64 + * See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
  65 + */
  66 +# define OMAP_INT_CAMERA 1
  67 +# define OMAP_INT_FIQ 3
  68 +# define OMAP_INT_RTDX 6
  69 +# define OMAP_INT_DSP_MMU_ABORT 7
  70 +# define OMAP_INT_HOST 8
  71 +# define OMAP_INT_ABORT 9
  72 +# define OMAP_INT_BRIDGE_PRIV 13
  73 +# define OMAP_INT_GPIO_BANK1 14
  74 +# define OMAP_INT_UART3 15
  75 +# define OMAP_INT_TIMER3 16
  76 +# define OMAP_INT_DMA_CH0_6 19
  77 +# define OMAP_INT_DMA_CH1_7 20
  78 +# define OMAP_INT_DMA_CH2_8 21
  79 +# define OMAP_INT_DMA_CH3 22
  80 +# define OMAP_INT_DMA_CH4 23
  81 +# define OMAP_INT_DMA_CH5 24
  82 +# define OMAP_INT_DMA_LCD 25
  83 +# define OMAP_INT_TIMER1 26
  84 +# define OMAP_INT_WD_TIMER 27
  85 +# define OMAP_INT_BRIDGE_PUB 28
  86 +# define OMAP_INT_TIMER2 30
  87 +# define OMAP_INT_LCD_CTRL 31
  88 +
  89 +/*
  90 + * Common OMAP-15xx IRQ numbers for level 1 interrupt handler
  91 + */
  92 +# define OMAP_INT_15XX_IH2_IRQ 0
  93 +# define OMAP_INT_15XX_LB_MMU 17
  94 +# define OMAP_INT_15XX_LOCAL_BUS 29
  95 +
  96 +/*
  97 + * OMAP-1510 specific IRQ numbers for level 1 interrupt handler
  98 + */
  99 +# define OMAP_INT_1510_SPI_TX 4
  100 +# define OMAP_INT_1510_SPI_RX 5
  101 +# define OMAP_INT_1510_DSP_MAILBOX1 10
  102 +# define OMAP_INT_1510_DSP_MAILBOX2 11
  103 +
  104 +/*
  105 + * OMAP-310 specific IRQ numbers for level 1 interrupt handler
  106 + */
  107 +# define OMAP_INT_310_McBSP2_TX 4
  108 +# define OMAP_INT_310_McBSP2_RX 5
  109 +# define OMAP_INT_310_HSB_MAILBOX1 12
  110 +# define OMAP_INT_310_HSAB_MMU 18
  111 +
  112 +/*
  113 + * OMAP-1610 specific IRQ numbers for level 1 interrupt handler
  114 + */
  115 +# define OMAP_INT_1610_IH2_IRQ 0
  116 +# define OMAP_INT_1610_IH2_FIQ 2
  117 +# define OMAP_INT_1610_McBSP2_TX 4
  118 +# define OMAP_INT_1610_McBSP2_RX 5
  119 +# define OMAP_INT_1610_DSP_MAILBOX1 10
  120 +# define OMAP_INT_1610_DSP_MAILBOX2 11
  121 +# define OMAP_INT_1610_LCD_LINE 12
  122 +# define OMAP_INT_1610_GPTIMER1 17
  123 +# define OMAP_INT_1610_GPTIMER2 18
  124 +# define OMAP_INT_1610_SSR_FIFO_0 29
  125 +
  126 +/*
  127 + * OMAP-730 specific IRQ numbers for level 1 interrupt handler
  128 + */
  129 +# define OMAP_INT_730_IH2_FIQ 0
  130 +# define OMAP_INT_730_IH2_IRQ 1
  131 +# define OMAP_INT_730_USB_NON_ISO 2
  132 +# define OMAP_INT_730_USB_ISO 3
  133 +# define OMAP_INT_730_ICR 4
  134 +# define OMAP_INT_730_EAC 5
  135 +# define OMAP_INT_730_GPIO_BANK1 6
  136 +# define OMAP_INT_730_GPIO_BANK2 7
  137 +# define OMAP_INT_730_GPIO_BANK3 8
  138 +# define OMAP_INT_730_McBSP2TX 10
  139 +# define OMAP_INT_730_McBSP2RX 11
  140 +# define OMAP_INT_730_McBSP2RX_OVF 12
  141 +# define OMAP_INT_730_LCD_LINE 14
  142 +# define OMAP_INT_730_GSM_PROTECT 15
  143 +# define OMAP_INT_730_TIMER3 16
  144 +# define OMAP_INT_730_GPIO_BANK5 17
  145 +# define OMAP_INT_730_GPIO_BANK6 18
  146 +# define OMAP_INT_730_SPGIO_WR 29
  147 +
  148 +/*
  149 + * Common IRQ numbers for level 2 interrupt handler
  150 + */
  151 +# define OMAP_INT_KEYBOARD 1
  152 +# define OMAP_INT_uWireTX 2
  153 +# define OMAP_INT_uWireRX 3
  154 +# define OMAP_INT_I2C 4
  155 +# define OMAP_INT_MPUIO 5
  156 +# define OMAP_INT_USB_HHC_1 6
  157 +# define OMAP_INT_McBSP3TX 10
  158 +# define OMAP_INT_McBSP3RX 11
  159 +# define OMAP_INT_McBSP1TX 12
  160 +# define OMAP_INT_McBSP1RX 13
  161 +# define OMAP_INT_UART1 14
  162 +# define OMAP_INT_UART2 15
  163 +# define OMAP_INT_USB_W2FC 20
  164 +# define OMAP_INT_1WIRE 21
  165 +# define OMAP_INT_OS_TIMER 22
  166 +# define OMAP_INT_MMC 23
  167 +# define OMAP_INT_GAUGE_32K 24
  168 +# define OMAP_INT_RTC_TIMER 25
  169 +# define OMAP_INT_RTC_ALARM 26
  170 +# define OMAP_INT_DSP_MMU 28
  171 +
  172 +/*
  173 + * OMAP-1510 specific IRQ numbers for level 2 interrupt handler
  174 + */
  175 +# define OMAP_INT_1510_BT_MCSI1TX 16
  176 +# define OMAP_INT_1510_BT_MCSI1RX 17
  177 +# define OMAP_INT_1510_SoSSI_MATCH 19
  178 +# define OMAP_INT_1510_MEM_STICK 27
  179 +# define OMAP_INT_1510_COM_SPI_RO 31
  180 +
  181 +/*
  182 + * OMAP-310 specific IRQ numbers for level 2 interrupt handler
  183 + */
  184 +# define OMAP_INT_310_FAC 0
  185 +# define OMAP_INT_310_USB_HHC_2 7
  186 +# define OMAP_INT_310_MCSI1_FE 16
  187 +# define OMAP_INT_310_MCSI2_FE 17
  188 +# define OMAP_INT_310_USB_W2FC_ISO 29
  189 +# define OMAP_INT_310_USB_W2FC_NON_ISO 30
  190 +# define OMAP_INT_310_McBSP2RX_OF 31
  191 +
  192 +/*
  193 + * OMAP-1610 specific IRQ numbers for level 2 interrupt handler
  194 + */
  195 +# define OMAP_INT_1610_FAC 0
  196 +# define OMAP_INT_1610_USB_HHC_2 7
  197 +# define OMAP_INT_1610_USB_OTG 8
  198 +# define OMAP_INT_1610_SoSSI 9
  199 +# define OMAP_INT_1610_BT_MCSI1TX 16
  200 +# define OMAP_INT_1610_BT_MCSI1RX 17
  201 +# define OMAP_INT_1610_SoSSI_MATCH 19
  202 +# define OMAP_INT_1610_MEM_STICK 27
  203 +# define OMAP_INT_1610_McBSP2RX_OF 31
  204 +# define OMAP_INT_1610_STI 32
  205 +# define OMAP_INT_1610_STI_WAKEUP 33
  206 +# define OMAP_INT_1610_GPTIMER3 34
  207 +# define OMAP_INT_1610_GPTIMER4 35
  208 +# define OMAP_INT_1610_GPTIMER5 36
  209 +# define OMAP_INT_1610_GPTIMER6 37
  210 +# define OMAP_INT_1610_GPTIMER7 38
  211 +# define OMAP_INT_1610_GPTIMER8 39
  212 +# define OMAP_INT_1610_GPIO_BANK2 40
  213 +# define OMAP_INT_1610_GPIO_BANK3 41
  214 +# define OMAP_INT_1610_MMC2 42
  215 +# define OMAP_INT_1610_CF 43
  216 +# define OMAP_INT_1610_WAKE_UP_REQ 46
  217 +# define OMAP_INT_1610_GPIO_BANK4 48
  218 +# define OMAP_INT_1610_SPI 49
  219 +# define OMAP_INT_1610_DMA_CH6 53
  220 +# define OMAP_INT_1610_DMA_CH7 54
  221 +# define OMAP_INT_1610_DMA_CH8 55
  222 +# define OMAP_INT_1610_DMA_CH9 56
  223 +# define OMAP_INT_1610_DMA_CH10 57
  224 +# define OMAP_INT_1610_DMA_CH11 58
  225 +# define OMAP_INT_1610_DMA_CH12 59
  226 +# define OMAP_INT_1610_DMA_CH13 60
  227 +# define OMAP_INT_1610_DMA_CH14 61
  228 +# define OMAP_INT_1610_DMA_CH15 62
  229 +# define OMAP_INT_1610_NAND 63
  230 +
  231 +/*
  232 + * OMAP-730 specific IRQ numbers for level 2 interrupt handler
  233 + */
  234 +# define OMAP_INT_730_HW_ERRORS 0
  235 +# define OMAP_INT_730_NFIQ_PWR_FAIL 1
  236 +# define OMAP_INT_730_CFCD 2
  237 +# define OMAP_INT_730_CFIREQ 3
  238 +# define OMAP_INT_730_I2C 4
  239 +# define OMAP_INT_730_PCC 5
  240 +# define OMAP_INT_730_MPU_EXT_NIRQ 6
  241 +# define OMAP_INT_730_SPI_100K_1 7
  242 +# define OMAP_INT_730_SYREN_SPI 8
  243 +# define OMAP_INT_730_VLYNQ 9
  244 +# define OMAP_INT_730_GPIO_BANK4 10
  245 +# define OMAP_INT_730_McBSP1TX 11
  246 +# define OMAP_INT_730_McBSP1RX 12
  247 +# define OMAP_INT_730_McBSP1RX_OF 13
  248 +# define OMAP_INT_730_UART_MODEM_IRDA_2 14
  249 +# define OMAP_INT_730_UART_MODEM_1 15
  250 +# define OMAP_INT_730_MCSI 16
  251 +# define OMAP_INT_730_uWireTX 17
  252 +# define OMAP_INT_730_uWireRX 18
  253 +# define OMAP_INT_730_SMC_CD 19
  254 +# define OMAP_INT_730_SMC_IREQ 20
  255 +# define OMAP_INT_730_HDQ_1WIRE 21
  256 +# define OMAP_INT_730_TIMER32K 22
  257 +# define OMAP_INT_730_MMC_SDIO 23
  258 +# define OMAP_INT_730_UPLD 24
  259 +# define OMAP_INT_730_USB_HHC_1 27
  260 +# define OMAP_INT_730_USB_HHC_2 28
  261 +# define OMAP_INT_730_USB_GENI 29
  262 +# define OMAP_INT_730_USB_OTG 30
  263 +# define OMAP_INT_730_CAMERA_IF 31
  264 +# define OMAP_INT_730_RNG 32
  265 +# define OMAP_INT_730_DUAL_MODE_TIMER 33
  266 +# define OMAP_INT_730_DBB_RF_EN 34
  267 +# define OMAP_INT_730_MPUIO_KEYPAD 35
  268 +# define OMAP_INT_730_SHA1_MD5 36
  269 +# define OMAP_INT_730_SPI_100K_2 37
  270 +# define OMAP_INT_730_RNG_IDLE 38
  271 +# define OMAP_INT_730_MPUIO 39
  272 +# define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40
  273 +# define OMAP_INT_730_LLPC_OE_FALLING 41
  274 +# define OMAP_INT_730_LLPC_OE_RISING 42
  275 +# define OMAP_INT_730_LLPC_VSYNC 43
  276 +# define OMAP_INT_730_WAKE_UP_REQ 46
  277 +# define OMAP_INT_730_DMA_CH6 53
  278 +# define OMAP_INT_730_DMA_CH7 54
  279 +# define OMAP_INT_730_DMA_CH8 55
  280 +# define OMAP_INT_730_DMA_CH9 56
  281 +# define OMAP_INT_730_DMA_CH10 57
  282 +# define OMAP_INT_730_DMA_CH11 58
  283 +# define OMAP_INT_730_DMA_CH12 59
  284 +# define OMAP_INT_730_DMA_CH13 60
  285 +# define OMAP_INT_730_DMA_CH14 61
  286 +# define OMAP_INT_730_DMA_CH15 62
  287 +# define OMAP_INT_730_NAND 63
  288 +
  289 +/*
  290 + * OMAP-24xx common IRQ numbers
  291 + */
  292 +# define OMAP_INT_24XX_SYS_NIRQ 7
  293 +# define OMAP_INT_24XX_SDMA_IRQ0 12
  294 +# define OMAP_INT_24XX_SDMA_IRQ1 13
  295 +# define OMAP_INT_24XX_SDMA_IRQ2 14
  296 +# define OMAP_INT_24XX_SDMA_IRQ3 15
  297 +# define OMAP_INT_24XX_CAM_IRQ 24
  298 +# define OMAP_INT_24XX_DSS_IRQ 25
  299 +# define OMAP_INT_24XX_MAIL_U0_MPU 26
  300 +# define OMAP_INT_24XX_DSP_UMA 27
  301 +# define OMAP_INT_24XX_DSP_MMU 28
  302 +# define OMAP_INT_24XX_GPIO_BANK1 29
  303 +# define OMAP_INT_24XX_GPIO_BANK2 30
  304 +# define OMAP_INT_24XX_GPIO_BANK3 31
  305 +# define OMAP_INT_24XX_GPIO_BANK4 32
  306 +# define OMAP_INT_24XX_GPIO_BANK5 33
  307 +# define OMAP_INT_24XX_MAIL_U3_MPU 34
  308 +# define OMAP_INT_24XX_GPTIMER1 37
  309 +# define OMAP_INT_24XX_GPTIMER2 38
  310 +# define OMAP_INT_24XX_GPTIMER3 39
  311 +# define OMAP_INT_24XX_GPTIMER4 40
  312 +# define OMAP_INT_24XX_GPTIMER5 41
  313 +# define OMAP_INT_24XX_GPTIMER6 42
  314 +# define OMAP_INT_24XX_GPTIMER7 43
  315 +# define OMAP_INT_24XX_GPTIMER8 44
  316 +# define OMAP_INT_24XX_GPTIMER9 45
  317 +# define OMAP_INT_24XX_GPTIMER10 46
  318 +# define OMAP_INT_24XX_GPTIMER11 47
  319 +# define OMAP_INT_24XX_GPTIMER12 48
  320 +# define OMAP_INT_24XX_MCBSP1_IRQ_TX 59
  321 +# define OMAP_INT_24XX_MCBSP1_IRQ_RX 60
  322 +# define OMAP_INT_24XX_MCBSP2_IRQ_TX 62
  323 +# define OMAP_INT_24XX_MCBSP2_IRQ_RX 63
  324 +# define OMAP_INT_24XX_UART1_IRQ 72
  325 +# define OMAP_INT_24XX_UART2_IRQ 73
  326 +# define OMAP_INT_24XX_UART3_IRQ 74
  327 +# define OMAP_INT_24XX_USB_IRQ_GEN 75
  328 +# define OMAP_INT_24XX_USB_IRQ_NISO 76
  329 +# define OMAP_INT_24XX_USB_IRQ_ISO 77
  330 +# define OMAP_INT_24XX_USB_IRQ_HGEN 78
  331 +# define OMAP_INT_24XX_USB_IRQ_HSOF 79
  332 +# define OMAP_INT_24XX_USB_IRQ_OTG 80
  333 +# define OMAP_INT_24XX_MMC_IRQ 83
  334 +# define OMAP_INT_243X_HS_USB_MC 92
  335 +# define OMAP_INT_243X_HS_USB_DMA 93
  336 +# define OMAP_INT_243X_CARKIT 94
  337 +
  338 +struct omap_dma_s;
  339 +struct omap_dma_s *omap_dma_init(target_phys_addr_t base,
  340 + qemu_irq pic[], struct omap_mpu_state_s *mpu, omap_clk clk);
  341 +
  342 +enum omap_dma_port {
  343 + emiff = 0,
  344 + emifs,
  345 + imif,
  346 + tipb,
  347 + local,
  348 + tipb_mpui,
  349 + omap_dma_port_last,
  350 +};
  351 +
  352 +struct omap_dma_lcd_channel_s {
  353 + enum omap_dma_port src;
  354 + target_phys_addr_t src_f1_top;
  355 + target_phys_addr_t src_f1_bottom;
  356 + target_phys_addr_t src_f2_top;
  357 + target_phys_addr_t src_f2_bottom;
  358 + /* Destination port is fixed. */
  359 + int interrupts;
  360 + int condition;
  361 + int dual;
  362 +
  363 + int current_frame;
  364 + ram_addr_t phys_framebuffer[2];
  365 + qemu_irq irq;
  366 + struct omap_mpu_state_s *mpu;
  367 +};
  368 +
  369 +/*
  370 + * DMA request numbers for OMAP1
  371 + * See /usr/include/asm-arm/arch-omap/dma.h in Linux.
  372 + */
  373 +# define OMAP_DMA_NO_DEVICE 0
  374 +# define OMAP_DMA_MCSI1_TX 1
  375 +# define OMAP_DMA_MCSI1_RX 2
  376 +# define OMAP_DMA_I2C_RX 3
  377 +# define OMAP_DMA_I2C_TX 4
  378 +# define OMAP_DMA_EXT_NDMA_REQ0 5
  379 +# define OMAP_DMA_EXT_NDMA_REQ1 6
  380 +# define OMAP_DMA_UWIRE_TX 7
  381 +# define OMAP_DMA_MCBSP1_TX 8
  382 +# define OMAP_DMA_MCBSP1_RX 9
  383 +# define OMAP_DMA_MCBSP3_TX 10
  384 +# define OMAP_DMA_MCBSP3_RX 11
  385 +# define OMAP_DMA_UART1_TX 12
  386 +# define OMAP_DMA_UART1_RX 13
  387 +# define OMAP_DMA_UART2_TX 14
  388 +# define OMAP_DMA_UART2_RX 15
  389 +# define OMAP_DMA_MCBSP2_TX 16
  390 +# define OMAP_DMA_MCBSP2_RX 17
  391 +# define OMAP_DMA_UART3_TX 18
  392 +# define OMAP_DMA_UART3_RX 19
  393 +# define OMAP_DMA_CAMERA_IF_RX 20
  394 +# define OMAP_DMA_MMC_TX 21
  395 +# define OMAP_DMA_MMC_RX 22
  396 +# define OMAP_DMA_NAND 23 /* Not in OMAP310 */
  397 +# define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */
  398 +# define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */
  399 +# define OMAP_DMA_USB_W2FC_RX0 26
  400 +# define OMAP_DMA_USB_W2FC_RX1 27
  401 +# define OMAP_DMA_USB_W2FC_RX2 28
  402 +# define OMAP_DMA_USB_W2FC_TX0 29
  403 +# define OMAP_DMA_USB_W2FC_TX1 30
  404 +# define OMAP_DMA_USB_W2FC_TX2 31
  405 +
  406 +/* These are only for 1610 */
  407 +# define OMAP_DMA_CRYPTO_DES_IN 32
  408 +# define OMAP_DMA_SPI_TX 33
  409 +# define OMAP_DMA_SPI_RX 34
  410 +# define OMAP_DMA_CRYPTO_HASH 35
  411 +# define OMAP_DMA_CCP_ATTN 36
  412 +# define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
  413 +# define OMAP_DMA_CMT_APE_TX_CHAN_0 38
  414 +# define OMAP_DMA_CMT_APE_RV_CHAN_0 39
  415 +# define OMAP_DMA_CMT_APE_TX_CHAN_1 40
  416 +# define OMAP_DMA_CMT_APE_RV_CHAN_1 41
  417 +# define OMAP_DMA_CMT_APE_TX_CHAN_2 42
  418 +# define OMAP_DMA_CMT_APE_RV_CHAN_2 43
  419 +# define OMAP_DMA_CMT_APE_TX_CHAN_3 44
  420 +# define OMAP_DMA_CMT_APE_RV_CHAN_3 45
  421 +# define OMAP_DMA_CMT_APE_TX_CHAN_4 46
  422 +# define OMAP_DMA_CMT_APE_RV_CHAN_4 47
  423 +# define OMAP_DMA_CMT_APE_TX_CHAN_5 48
  424 +# define OMAP_DMA_CMT_APE_RV_CHAN_5 49
  425 +# define OMAP_DMA_CMT_APE_TX_CHAN_6 50
  426 +# define OMAP_DMA_CMT_APE_RV_CHAN_6 51
  427 +# define OMAP_DMA_CMT_APE_TX_CHAN_7 52
  428 +# define OMAP_DMA_CMT_APE_RV_CHAN_7 53
  429 +# define OMAP_DMA_MMC2_TX 54
  430 +# define OMAP_DMA_MMC2_RX 55
  431 +# define OMAP_DMA_CRYPTO_DES_OUT 56
  432 +
  433 +struct omap_mpu_timer_s;
  434 +struct omap_mpu_timer_s *omap_mpu_timer_init(target_phys_addr_t base,
  435 + qemu_irq irq, omap_clk clk);
  436 +
  437 +struct omap_watchdog_timer_s;
  438 +struct omap_watchdog_timer_s *omap_wd_timer_init(target_phys_addr_t base,
  439 + qemu_irq irq, omap_clk clk);
  440 +
  441 +struct omap_32khz_timer_s;
  442 +struct omap_32khz_timer_s *omap_os_timer_init(target_phys_addr_t base,
  443 + qemu_irq irq, omap_clk clk);
  444 +
  445 +struct omap_tipb_bridge_s;
  446 +struct omap_tipb_bridge_s *omap_tipb_bridge_init(target_phys_addr_t base,
  447 + qemu_irq abort_irq, omap_clk clk);
  448 +
  449 +struct omap_uart_s;
  450 +struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
  451 + qemu_irq irq, omap_clk clk, CharDriverState *chr);
  452 +
  453 +/* omap_lcdc.c */
  454 +struct omap_lcd_panel_s;
  455 +void omap_lcdc_reset(struct omap_lcd_panel_s *s);
  456 +struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
  457 + struct omap_dma_lcd_channel_s *dma, DisplayState *ds,
  458 + ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk);
  459 +
  460 +# define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
  461 +# define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
  462 +# define cpu_is_omap15xx(cpu) \
  463 + (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu))
  464 +# define cpu_class_omap1(cpu) 1
  465 +
  466 +struct omap_mpu_state_s {
  467 + enum omap1_mpu_model {
  468 + omap310,
  469 + omap1510,
  470 + } mpu_model;
  471 +
  472 + CPUState *env;
  473 +
  474 + qemu_irq *irq[2];
  475 + qemu_irq *drq;
  476 +
  477 + qemu_irq wakeup;
  478 +
  479 + struct omap_dma_port_if_s {
  480 + uint32_t (*read[3])(struct omap_mpu_state_s *s,
  481 + target_phys_addr_t offset);
  482 + void (*write[3])(struct omap_mpu_state_s *s,
  483 + target_phys_addr_t offset, uint32_t value);
  484 + int (*addr_valid)(struct omap_mpu_state_s *s,
  485 + target_phys_addr_t addr);
  486 + } port[omap_dma_port_last];
  487 +
  488 + unsigned long sdram_size;
  489 + unsigned long sram_size;
  490 +
  491 + /* MPUI-TIPB peripherals */
  492 + struct omap_uart_s *uart3;
  493 +
  494 + /* MPU public TIPB peripherals */
  495 + struct omap_32khz_timer_s *os_timer;
  496 +
  497 + struct omap_uart_s *uart1;
  498 + struct omap_uart_s *uart2;
  499 +
  500 + /* MPU private TIPB peripherals */
  501 + struct omap_intr_handler_s *ih[2];
  502 +
  503 + struct omap_dma_s *dma;
  504 +
  505 + struct omap_mpu_timer_s *timer[3];
  506 + struct omap_watchdog_timer_s *wdt;
  507 +
  508 + struct omap_lcd_panel_s *lcd;
  509 +
  510 + target_phys_addr_t ulpd_pm_base;
  511 + uint32_t ulpd_pm_regs[21];
  512 + int64_t ulpd_gauge_start;
  513 +
  514 + target_phys_addr_t pin_cfg_base;
  515 + uint32_t func_mux_ctrl[14];
  516 + uint32_t comp_mode_ctrl[1];
  517 + uint32_t pull_dwn_ctrl[4];
  518 + uint32_t gate_inh_ctrl[1];
  519 + uint32_t voltage_ctrl[1];
  520 + uint32_t test_dbg_ctrl[1];
  521 + uint32_t mod_conf_ctrl[1];
  522 + int compat1509;
  523 +
  524 + uint32_t mpui_ctrl;
  525 + target_phys_addr_t mpui_base;
  526 +
  527 + struct omap_tipb_bridge_s *private_tipb;
  528 + struct omap_tipb_bridge_s *public_tipb;
  529 +
  530 + target_phys_addr_t tcmi_base;
  531 + uint32_t tcmi_regs[17];
  532 +
  533 + struct dpll_ctl_s {
  534 + target_phys_addr_t base;
  535 + uint16_t mode;
  536 + omap_clk dpll;
  537 + } dpll[3];
  538 +
  539 + omap_clk clks;
  540 + struct {
  541 + target_phys_addr_t mpu_base;
  542 + target_phys_addr_t dsp_base;
  543 +
  544 + int cold_start;
  545 + int clocking_scheme;
  546 + uint16_t arm_ckctl;
  547 + uint16_t arm_idlect1;
  548 + uint16_t arm_idlect2;
  549 + uint16_t arm_ewupct;
  550 + uint16_t arm_rstct1;
  551 + uint16_t arm_rstct2;
  552 + uint16_t arm_ckout1;
  553 + int dpll1_mode;
  554 + uint16_t dsp_idlect1;
  555 + uint16_t dsp_idlect2;
  556 + uint16_t dsp_rstct2;
  557 + } clkm;
  558 +} *omap310_mpu_init(unsigned long sdram_size,
  559 + DisplayState *ds, const char *core);
  560 +
  561 +# if TARGET_PHYS_ADDR_BITS == 32
  562 +# define OMAP_FMT_plx "%#08x"
  563 +# elif TARGET_PHYS_ADDR_BITS == 64
  564 +# define OMAP_FMT_plx "%#08" PRIx64
  565 +# else
  566 +# error TARGET_PHYS_ADDR_BITS undefined
  567 +# endif
  568 +
  569 +# define OMAP_BAD_REG(paddr) \
  570 + printf("%s: Bad register " OMAP_FMT_plx "\n", __FUNCTION__, paddr)
  571 +# define OMAP_RO_REG(paddr) \
  572 + printf("%s: Read-only register " OMAP_FMT_plx "\n", \
  573 + __FUNCTION__, paddr)
  574 +# define OMAP_16B_REG(paddr) \
  575 + printf("%s: 16-bit register " OMAP_FMT_plx "\n", \
  576 + __FUNCTION__, paddr)
  577 +# define OMAP_32B_REG(paddr) \
  578 + printf("%s: 32-bit register " OMAP_FMT_plx "\n", \
  579 + __FUNCTION__, paddr)
  580 +
  581 +#endif /* hw_omap_h */
... ...
hw/omap1_clk.c 0 → 100644
  View file @c3d2689
  1 +/*
  2 + * OMAP clocks.
  3 + *
  4 + * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
  5 + *
  6 + * Clocks data comes in part from arch/arm/mach-omap1/clock.h in Linux.
  7 + *
  8 + * This program is free software; you can redistribute it and/or
  9 + * modify it under the terms of the GNU General Public License as
  10 + * published by the Free Software Foundation; either version 2 of
  11 + * the License, or (at your option) any later version.
  12 + *
  13 + * This program is distributed in the hope that it will be useful,
  14 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 + * GNU General Public License for more details.
  17 + *
  18 + * You should have received a copy of the GNU General Public License
  19 + * along with this program; if not, write to the Free Software
  20 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 + * MA 02111-1307 USA
  22 + */
  23 +#include "vl.h"
  24 +
  25 +struct clk {
  26 + const char *name;
  27 + const char *alias;
  28 + struct clk *parent;
  29 + struct clk *child1;
  30 + struct clk *sibling;
  31 +#define ALWAYS_ENABLED (1 << 0)
  32 +#define CLOCK_IN_OMAP310 (1 << 10)
  33 +#define CLOCK_IN_OMAP730 (1 << 11)
  34 +#define CLOCK_IN_OMAP1510 (1 << 12)
  35 +#define CLOCK_IN_OMAP16XX (1 << 13)
  36 + uint32_t flags;
  37 + int id;
  38 +
  39 + int running; /* Is currently ticking */
  40 + int enabled; /* Is enabled, regardless of its input clk */
  41 + unsigned long rate; /* Current rate (if .running) */
  42 + unsigned int divisor; /* Rate relative to input (if .enabled) */
  43 + unsigned int multiplier; /* Rate relative to input (if .enabled) */
  44 + qemu_irq users[16]; /* Who to notify on change */
  45 + int usecount; /* Automatically idle when unused */
  46 +};
  47 +
  48 +static struct clk xtal_osc12m = {
  49 + .name = "xtal_osc_12m",
  50 + .rate = 12000000,
  51 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
  52 +};
  53 +
  54 +static struct clk xtal_osc32k = {
  55 + .name = "xtal_osc_32k",
  56 + .rate = 32768,
  57 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
  58 +};
  59 +
  60 +static struct clk ck_ref = {
  61 + .name = "ck_ref",
  62 + .alias = "clkin",
  63 + .parent = &xtal_osc12m,
  64 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
  65 + ALWAYS_ENABLED,
  66 +};
  67 +
  68 +/* If a dpll is disabled it becomes a bypass, child clocks don't stop */
  69 +static struct clk dpll1 = {
  70 + .name = "dpll1",
  71 + .parent = &ck_ref,
  72 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
  73 + ALWAYS_ENABLED,
  74 +};
  75 +
  76 +static struct clk dpll2 = {
  77 + .name = "dpll2",
  78 + .parent = &ck_ref,
  79 + .flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
  80 +};
  81 +
  82 +static struct clk dpll3 = {
  83 + .name = "dpll3",
  84 + .parent = &ck_ref,
  85 + .flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
  86 +};
  87 +
  88 +static struct clk dpll4 = {
  89 + .name = "dpll4",
  90 + .parent = &ck_ref,
  91 + .multiplier = 4,
  92 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
  93 +};
  94 +
  95 +static struct clk apll = {
  96 + .name = "apll",
  97 + .parent = &ck_ref,
  98 + .multiplier = 48,
  99 + .divisor = 12,
  100 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
  101 +};
  102 +
  103 +static struct clk ck_48m = {
  104 + .name = "ck_48m",
  105 + .parent = &dpll4, /* either dpll4 or apll */
  106 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
  107 +};
  108 +
  109 +static struct clk ck_dpll1out = {
  110 + .name = "ck_dpll1out",
  111 + .parent = &dpll1,
  112 + .flags = CLOCK_IN_OMAP16XX,
  113 +};
  114 +
  115 +static struct clk sossi_ck = {
  116 + .name = "ck_sossi",
  117 + .parent = &ck_dpll1out,
  118 + .flags = CLOCK_IN_OMAP16XX,
  119 +};
  120 +
  121 +static struct clk clkm1 = {
  122 + .name = "clkm1",
  123 + .alias = "ck_gen1",
  124 + .parent = &dpll1,
  125 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
  126 + ALWAYS_ENABLED,
  127 +};
  128 +
  129 +static struct clk clkm2 = {
  130 + .name = "clkm2",
  131 + .alias = "ck_gen2",
  132 + .parent = &dpll1,
  133 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
  134 + ALWAYS_ENABLED,
  135 +};
  136 +
  137 +static struct clk clkm3 = {
  138 + .name = "clkm3",
  139 + .alias = "ck_gen3",
  140 + .parent = &dpll1, /* either dpll1 or ck_ref */
  141 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
  142 + ALWAYS_ENABLED,
  143 +};
  144 +
  145 +static struct clk arm_ck = {
  146 + .name = "arm_ck",
  147 + .alias = "mpu_ck",
  148 + .parent = &clkm1,
  149 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
  150 + ALWAYS_ENABLED,
  151 +};
  152 +
  153 +static struct clk armper_ck = {
  154 + .name = "armper_ck",
  155 + .alias = "mpuper_ck",
  156 + .parent = &clkm1,
  157 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
  158 +};
  159 +
  160 +static struct clk arm_gpio_ck = {
  161 + .name = "arm_gpio_ck",
  162 + .alias = "mpu_gpio_ck",
  163 + .parent = &clkm1,
  164 + .divisor = 1,
  165 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
  166 +};
  167 +
  168 +static struct clk armxor_ck = {
  169 + .name = "armxor_ck",
  170 + .alias = "mpuxor_ck",
  171 + .parent = &ck_ref,
  172 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
  173 +};
  174 +
  175 +static struct clk armtim_ck = {
  176 + .name = "armtim_ck",
  177 + .alias = "mputim_ck",
  178 + .parent = &ck_ref, /* either CLKIN or DPLL1 */
  179 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
  180 +};
  181 +
  182 +static struct clk armwdt_ck = {
  183 + .name = "armwdt_ck",
  184 + .alias = "mpuwd_ck",
  185 + .parent = &clkm1,
  186 + .divisor = 14,
  187 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
  188 + ALWAYS_ENABLED,
  189 +};
  190 +
  191 +static struct clk arminth_ck16xx = {
  192 + .name = "arminth_ck",
  193 + .parent = &arm_ck,
  194 + .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
  195 + /* Note: On 16xx the frequency can be divided by 2 by programming
  196 + * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
  197 + *
  198 + * 1510 version is in TC clocks.
  199 + */
  200 +};
  201 +
  202 +static struct clk dsp_ck = {
  203 + .name = "dsp_ck",
  204 + .parent = &clkm2,
  205 + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
  206 +};
  207 +
  208 +static struct clk dspmmu_ck = {
  209 + .name = "dspmmu_ck",
  210 + .parent = &clkm2,
  211 + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
  212 + ALWAYS_ENABLED,
  213 +};
  214 +
  215 +static struct clk dspper_ck = {
  216 + .name = "dspper_ck",
  217 + .parent = &clkm2,
  218 + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
  219 +};
  220 +
  221 +static struct clk dspxor_ck = {
  222 + .name = "dspxor_ck",
  223 + .parent = &ck_ref,
  224 + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
  225 +};
  226 +
  227 +static struct clk dsptim_ck = {
  228 + .name = "dsptim_ck",
  229 + .parent = &ck_ref,
  230 + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
  231 +};
  232 +
  233 +static struct clk tc_ck = {
  234 + .name = "tc_ck",
  235 + .parent = &clkm3,
  236 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
  237 + CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
  238 + ALWAYS_ENABLED,
  239 +};
  240 +
  241 +static struct clk arminth_ck15xx = {
  242 + .name = "arminth_ck",
  243 + .parent = &tc_ck,
  244 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
  245 + /* Note: On 1510 the frequency follows TC_CK
  246 + *
  247 + * 16xx version is in MPU clocks.
  248 + */
  249 +};
  250 +
  251 +static struct clk tipb_ck = {
  252 + /* No-idle controlled by "tc_ck" */
  253 + .name = "tipb_ck",
  254 + .parent = &tc_ck,
  255 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
  256 +};
  257 +
  258 +static struct clk l3_ocpi_ck = {
  259 + /* No-idle controlled by "tc_ck" */
  260 + .name = "l3_ocpi_ck",
  261 + .parent = &tc_ck,
  262 + .flags = CLOCK_IN_OMAP16XX,
  263 +};
  264 +
  265 +static struct clk tc1_ck = {
  266 + .name = "tc1_ck",
  267 + .parent = &tc_ck,
  268 + .flags = CLOCK_IN_OMAP16XX,
  269 +};
  270 +
  271 +static struct clk tc2_ck = {
  272 + .name = "tc2_ck",
  273 + .parent = &tc_ck,
  274 + .flags = CLOCK_IN_OMAP16XX,
  275 +};
  276 +
  277 +static struct clk dma_ck = {
  278 + /* No-idle controlled by "tc_ck" */
  279 + .name = "dma_ck",
  280 + .parent = &tc_ck,
  281 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
  282 + ALWAYS_ENABLED,
  283 +};
  284 +
  285 +static struct clk dma_lcdfree_ck = {
  286 + .name = "dma_lcdfree_ck",
  287 + .parent = &tc_ck,
  288 + .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
  289 +};
  290 +
  291 +static struct clk api_ck = {
  292 + .name = "api_ck",
  293 + .alias = "mpui_ck",
  294 + .parent = &tc_ck,
  295 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
  296 +};
  297 +
  298 +static struct clk lb_ck = {
  299 + .name = "lb_ck",
  300 + .parent = &tc_ck,
  301 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
  302 +};
  303 +
  304 +static struct clk lbfree_ck = {
  305 + .name = "lbfree_ck",
  306 + .parent = &tc_ck,
  307 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
  308 +};
  309 +
  310 +static struct clk rhea1_ck = {
  311 + .name = "rhea1_ck",
  312 + .parent = &tc_ck,
  313 + .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
  314 +};
  315 +
  316 +static struct clk rhea2_ck = {
  317 + .name = "rhea2_ck",
  318 + .parent = &tc_ck,
  319 + .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
  320 +};
  321 +
  322 +static struct clk lcd_ck_16xx = {
  323 + .name = "lcd_ck",
  324 + .parent = &clkm3,
  325 + .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730,
  326 +};
  327 +
  328 +static struct clk lcd_ck_1510 = {
  329 + .name = "lcd_ck",
  330 + .parent = &clkm3,
  331 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
  332 +};
  333 +
  334 +static struct clk uart1_1510 = {
  335 + .name = "uart1_ck",
  336 + /* Direct from ULPD, no real parent */
  337 + .parent = &armper_ck, /* either armper_ck or dpll4 */
  338 + .rate = 12000000,
  339 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
  340 +};
  341 +
  342 +static struct clk uart1_16xx = {
  343 + .name = "uart1_ck",
  344 + /* Direct from ULPD, no real parent */
  345 + .parent = &armper_ck,
  346 + .rate = 48000000,
  347 + .flags = CLOCK_IN_OMAP16XX,
  348 +};
  349 +
  350 +static struct clk uart2_ck = {
  351 + .name = "uart2_ck",
  352 + /* Direct from ULPD, no real parent */
  353 + .parent = &armper_ck, /* either armper_ck or dpll4 */
  354 + .rate = 12000000,
  355 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
  356 + ALWAYS_ENABLED,
  357 +};
  358 +
  359 +static struct clk uart3_1510 = {
  360 + .name = "uart3_ck",
  361 + /* Direct from ULPD, no real parent */
  362 + .parent = &armper_ck,/* either armper_ck or dpll4 */
  363 + .rate = 12000000,
  364 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
  365 +};
  366 +
  367 +static struct clk uart3_16xx = {
  368 + .name = "uart3_ck",
  369 + /* Direct from ULPD, no real parent */
  370 + .parent = &armper_ck,
  371 + .rate = 48000000,
  372 + .flags = CLOCK_IN_OMAP16XX,
  373 +};
  374 +
  375 +static struct clk usb_clk0 = { /* 6 MHz output on W4_USB_CLK0 */
  376 + .name = "usb_clk0",
  377 + .alias = "usb.clko",
  378 + /* Direct from ULPD, no parent */
  379 + .rate = 6000000,
  380 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
  381 +};
  382 +
  383 +static struct clk usb_hhc_ck1510 = {
  384 + .name = "usb_hhc_ck",
  385 + /* Direct from ULPD, no parent */
  386 + .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
  387 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
  388 +};
  389 +
  390 +static struct clk usb_hhc_ck16xx = {
  391 + .name = "usb_hhc_ck",
  392 + /* Direct from ULPD, no parent */
  393 + .rate = 48000000,
  394 + /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
  395 + .flags = CLOCK_IN_OMAP16XX,
  396 +};
  397 +
  398 +static struct clk usb_dc_ck = {
  399 + .name = "usb_dc_ck",
  400 + /* Direct from ULPD, no parent */
  401 + .rate = 48000000,
  402 + .flags = CLOCK_IN_OMAP16XX,
  403 +};
  404 +
  405 +static struct clk mclk_1510 = {
  406 + .name = "mclk",
  407 + /* Direct from ULPD, no parent. May be enabled by ext hardware. */
  408 + .rate = 12000000,
  409 + .flags = CLOCK_IN_OMAP1510,
  410 +};
  411 +
  412 +static struct clk bclk_310 = {
  413 + .name = "bt_mclk_out", /* Alias midi_mclk_out? */
  414 + .parent = &armper_ck,
  415 + .flags = CLOCK_IN_OMAP310,
  416 +};
  417 +
  418 +static struct clk mclk_310 = {
  419 + .name = "com_mclk_out",
  420 + .parent = &armper_ck,
  421 + .flags = CLOCK_IN_OMAP310,
  422 +};
  423 +
  424 +static struct clk mclk_16xx = {
  425 + .name = "mclk",
  426 + /* Direct from ULPD, no parent. May be enabled by ext hardware. */
  427 + .flags = CLOCK_IN_OMAP16XX,
  428 +};
  429 +
  430 +static struct clk bclk_1510 = {
  431 + .name = "bclk",
  432 + /* Direct from ULPD, no parent. May be enabled by ext hardware. */
  433 + .rate = 12000000,
  434 + .flags = CLOCK_IN_OMAP1510,
  435 +};
  436 +
  437 +static struct clk bclk_16xx = {
  438 + .name = "bclk",
  439 + /* Direct from ULPD, no parent. May be enabled by ext hardware. */
  440 + .flags = CLOCK_IN_OMAP16XX,
  441 +};
  442 +
  443 +static struct clk mmc1_ck = {
  444 + .name = "mmc_ck",
  445 + .id = 1,
  446 + /* Functional clock is direct from ULPD, interface clock is ARMPER */
  447 + .parent = &armper_ck, /* either armper_ck or dpll4 */
  448 + .rate = 48000000,
  449 + .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
  450 +};
  451 +
  452 +static struct clk mmc2_ck = {
  453 + .name = "mmc_ck",
  454 + .id = 2,
  455 + /* Functional clock is direct from ULPD, interface clock is ARMPER */
  456 + .parent = &armper_ck,
  457 + .rate = 48000000,
  458 + .flags = CLOCK_IN_OMAP16XX,
  459 +};
  460 +
  461 +static struct clk cam_mclk = {
  462 + .name = "cam.mclk",
  463 + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
  464 + .rate = 12000000,
  465 +};
  466 +
  467 +static struct clk cam_exclk = {
  468 + .name = "cam.exclk",
  469 + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
  470 + /* Either 12M from cam.mclk or 48M from dpll4 */
  471 + .parent = &cam_mclk,
  472 +};
  473 +
  474 +static struct clk cam_lclk = {
  475 + .name = "cam.lclk",
  476 + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
  477 +};
  478 +
  479 +static struct clk i2c_fck = {
  480 + .name = "i2c_fck",
  481 + .id = 1,
  482 + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
  483 + ALWAYS_ENABLED,
  484 + .parent = &armxor_ck,
  485 +};
  486 +
  487 +static struct clk i2c_ick = {
  488 + .name = "i2c_ick",
  489 + .id = 1,
  490 + .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
  491 + .parent = &armper_ck,
  492 +};
  493 +
  494 +static struct clk clk32k = {
  495 + .name = "clk32-kHz",
  496 + .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
  497 + ALWAYS_ENABLED,
  498 + .parent = &xtal_osc32k,
  499 +};
  500 +
  501 +static struct clk *onchip_clks[] = {
  502 + /* non-ULPD clocks */
  503 + &xtal_osc12m,
  504 + &xtal_osc32k,
  505 + &ck_ref,
  506 + &dpll1,
  507 + &dpll2,
  508 + &dpll3,
  509 + &dpll4,
  510 + &apll,
  511 + &ck_48m,
  512 + /* CK_GEN1 clocks */
  513 + &clkm1,
  514 + &ck_dpll1out,
  515 + &sossi_ck,
  516 + &arm_ck,
  517 + &armper_ck,
  518 + &arm_gpio_ck,
  519 + &armxor_ck,
  520 + &armtim_ck,
  521 + &armwdt_ck,
  522 + &arminth_ck15xx, &arminth_ck16xx,
  523 + /* CK_GEN2 clocks */
  524 + &clkm2,
  525 + &dsp_ck,
  526 + &dspmmu_ck,
  527 + &dspper_ck,
  528 + &dspxor_ck,
  529 + &dsptim_ck,
  530 + /* CK_GEN3 clocks */
  531 + &clkm3,
  532 + &tc_ck,
  533 + &tipb_ck,
  534 + &l3_ocpi_ck,
  535 + &tc1_ck,
  536 + &tc2_ck,
  537 + &dma_ck,
  538 + &dma_lcdfree_ck,
  539 + &api_ck,
  540 + &lb_ck,
  541 + &lbfree_ck,
  542 + &rhea1_ck,
  543 + &rhea2_ck,
  544 + &lcd_ck_16xx,
  545 + &lcd_ck_1510,
  546 + /* ULPD clocks */
  547 + &uart1_1510,
  548 + &uart1_16xx,
  549 + &uart2_ck,
  550 + &uart3_1510,
  551 + &uart3_16xx,
  552 + &usb_clk0,
  553 + &usb_hhc_ck1510, &usb_hhc_ck16xx,
  554 + &usb_dc_ck,
  555 + &mclk_1510, &mclk_16xx, &mclk_310,
  556 + &bclk_1510, &bclk_16xx, &bclk_310,
  557 + &mmc1_ck,
  558 + &mmc2_ck,
  559 + &cam_mclk,
  560 + &cam_exclk,
  561 + &cam_lclk,
  562 + &clk32k,
  563 + /* Virtual clocks */
  564 + &i2c_fck,
  565 + &i2c_ick,
  566 + 0
  567 +};
  568 +
  569 +void omap_clk_adduser(struct clk *clk, qemu_irq user)
  570 +{
  571 + qemu_irq *i;
  572 +
  573 + for (i = clk->users; *i; i ++);
  574 + *i = user;
  575 +}
  576 +
  577 +/* If a clock is allowed to idle, it is disabled automatically when
  578 + * all of clock domains using it are disabled. */
  579 +int omap_clk_is_idle(struct clk *clk)
  580 +{
  581 + struct clk *chld;
  582 +
  583 + if (!clk->enabled && (!clk->usecount || !(clk->flags && ALWAYS_ENABLED)))
  584 + return 1;
  585 + if (clk->usecount)
  586 + return 0;
  587 +
  588 + for (chld = clk->child1; chld; chld = chld->sibling)
  589 + if (!omap_clk_is_idle(chld))
  590 + return 0;
  591 + return 1;
  592 +}
  593 +
  594 +struct clk *omap_findclk(struct omap_mpu_state_s *mpu, const char *name)
  595 +{
  596 + struct clk *i;
  597 +
  598 + for (i = mpu->clks; i->name; i ++)
  599 + if (!strcmp(i->name, name) || (i->alias && !strcmp(i->alias, name)))
  600 + return i;
  601 + cpu_abort(mpu->env, "%s: %s not found\n", __FUNCTION__, name);
  602 +}
  603 +
  604 +void omap_clk_get(struct clk *clk)
  605 +{
  606 + clk->usecount ++;
  607 +}
  608 +
  609 +void omap_clk_put(struct clk *clk)
  610 +{
  611 + if (!(clk->usecount --))
  612 + cpu_abort(cpu_single_env, "%s: %s is not in use\n",
  613 + __FUNCTION__, clk->name);
  614 +}
  615 +
  616 +static void omap_clk_update(struct clk *clk)
  617 +{
  618 + int parent, running;
  619 + qemu_irq *user;
  620 + struct clk *i;
  621 +
  622 + if (clk->parent)
  623 + parent = clk->parent->running;
  624 + else
  625 + parent = 1;
  626 +
  627 + running = parent && (clk->enabled ||
  628 + ((clk->flags & ALWAYS_ENABLED) && clk->usecount));
  629 + if (clk->running != running) {
  630 + clk->running = running;
  631 + for (user = clk->users; *user; user ++)
  632 + qemu_set_irq(*user, running);
  633 + for (i = clk->child1; i; i = i->sibling)
  634 + omap_clk_update(i);
  635 + }
  636 +}
  637 +
  638 +static void omap_clk_rate_update_full(struct clk *clk, unsigned long int rate,
  639 + unsigned long int div, unsigned long int mult)
  640 +{
  641 + struct clk *i;
  642 + qemu_irq *user;
  643 +
  644 + clk->rate = muldiv64(rate, mult, div);
  645 + if (clk->running)
  646 + for (user = clk->users; *user; user ++)
  647 + qemu_irq_raise(*user);
  648 + for (i = clk->child1; i; i = i->sibling)
  649 + omap_clk_rate_update_full(i, rate,
  650 + div * i->divisor, mult * i->multiplier);
  651 +}
  652 +
  653 +static void omap_clk_rate_update(struct clk *clk)
  654 +{
  655 + struct clk *i;
  656 + unsigned long int div, mult = div = 1;
  657 +
  658 + for (i = clk; i->parent; i = i->parent) {
  659 + div *= i->divisor;
  660 + mult *= i->multiplier;
  661 + }
  662 +
  663 + omap_clk_rate_update_full(clk, i->rate, div, mult);
  664 +}
  665 +
  666 +void omap_clk_reparent(struct clk *clk, struct clk *parent)
  667 +{
  668 + struct clk **p;
  669 +
  670 + if (clk->parent) {
  671 + for (p = &clk->parent->child1; *p != clk; p = &(*p)->sibling);
  672 + *p = clk->sibling;
  673 + }
  674 +
  675 + clk->parent = parent;
  676 + if (parent) {
  677 + clk->sibling = parent->child1;
  678 + parent->child1 = clk;
  679 + omap_clk_update(clk);
  680 + omap_clk_rate_update(clk);
  681 + } else
  682 + clk->sibling = 0;
  683 +}
  684 +
  685 +void omap_clk_onoff(struct clk *clk, int on)
  686 +{
  687 + clk->enabled = on;
  688 + omap_clk_update(clk);
  689 +}
  690 +
  691 +void omap_clk_canidle(struct clk *clk, int can)
  692 +{
  693 + if (can)
  694 + omap_clk_put(clk);
  695 + else
  696 + omap_clk_get(clk);
  697 +}
  698 +
  699 +void omap_clk_setrate(struct clk *clk, int divide, int multiply)
  700 +{
  701 + clk->divisor = divide;
  702 + clk->multiplier = multiply;
  703 + omap_clk_rate_update(clk);
  704 +}
  705 +
  706 +int64_t omap_clk_getrate(omap_clk clk)
  707 +{
  708 + return clk->rate;
  709 +}
  710 +
  711 +void omap_clk_init(struct omap_mpu_state_s *mpu)
  712 +{
  713 + struct clk **i, *j, *k;
  714 + int count;
  715 + int flag;
  716 +
  717 + if (cpu_is_omap310(mpu))
  718 + flag = CLOCK_IN_OMAP310;
  719 + else if (cpu_is_omap1510(mpu))
  720 + flag = CLOCK_IN_OMAP1510;
  721 + else
  722 + return;
  723 +
  724 + for (i = onchip_clks, count = 0; *i; i ++)
  725 + if ((*i)->flags & flag)
  726 + count ++;
  727 + mpu->clks = (struct clk *) qemu_mallocz(sizeof(struct clk) * (count + 1));
  728 + for (i = onchip_clks, j = mpu->clks; *i; i ++)
  729 + if ((*i)->flags & flag) {
  730 + memcpy(j, *i, sizeof(struct clk));
  731 + for (k = mpu->clks; k < j; k ++)
  732 + if (j->parent && !strcmp(j->parent->name, k->name)) {
  733 + j->parent = k;
  734 + j->sibling = k->child1;
  735 + k->child1 = j;
  736 + } else if (k->parent && !strcmp(k->parent->name, j->name)) {
  737 + k->parent = j;
  738 + k->sibling = j->child1;
  739 + j->child1 = k;
  740 + }
  741 + j->divisor = j->divisor ?: 1;
  742 + j->multiplier = j->multiplier ?: 1;
  743 + j ++;
  744 + }
  745 +}
... ...
hw/omap_lcd_template.h 0 → 100644
  View file @c3d2689
  1 +/*
  2 + * QEMU OMAP LCD Emulator templates
  3 + *
  4 + * Copyright (c) 2006 Andrzej Zaborowski <balrog@zabor.org>
  5 + *
  6 + * Redistribution and use in source and binary forms, with or without
  7 + * modification, are permitted provided that the following conditions
  8 + * are met:
  9 + *
  10 + * 1. Redistributions of source code must retain the above copyright
  11 + * notice, this list of conditions and the following disclaimer.
  12 + * 2. Redistributions in binary form must reproduce the above copyright
  13 + * notice, this list of conditions and the following disclaimer in
  14 + * the documentation and/or other materials provided with the
  15 + * distribution.
  16 + *
  17 + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
  18 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  19 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  20 + * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
  21 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  22 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  23 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  24 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  25 + * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 + */
  29 +
  30 +#if DEPTH == 8
  31 +# define BPP 1
  32 +# define PIXEL_TYPE uint8_t
  33 +#elif DEPTH == 15 || DEPTH == 16
  34 +# define BPP 2
  35 +# define PIXEL_TYPE uint16_t
  36 +#elif DEPTH == 32
  37 +# define BPP 4
  38 +# define PIXEL_TYPE uint32_t
  39 +#else
  40 +# error unsupport depth
  41 +#endif
  42 +
  43 +/*
  44 + * 2-bit colour
  45 + */
  46 +static void glue(draw_line2_, DEPTH)(
  47 + uint8_t *d, const uint8_t *s, int width, const uint16_t *pal)
  48 +{
  49 + uint8_t v, r, g, b;
  50 +
  51 + do {
  52 + v = ldub_raw((void *) s);
  53 + r = (pal[v & 3] >> 4) & 0xf0;
  54 + g = pal[v & 3] & 0xf0;
  55 + b = (pal[v & 3] << 4) & 0xf0;
  56 + ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
  57 + d += BPP;
  58 + v >>= 2;
  59 + r = (pal[v & 3] >> 4) & 0xf0;
  60 + g = pal[v & 3] & 0xf0;
  61 + b = (pal[v & 3] << 4) & 0xf0;
  62 + ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
  63 + d += BPP;
  64 + v >>= 2;
  65 + r = (pal[v & 3] >> 4) & 0xf0;
  66 + g = pal[v & 3] & 0xf0;
  67 + b = (pal[v & 3] << 4) & 0xf0;
  68 + ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
  69 + d += BPP;
  70 + v >>= 2;
  71 + r = (pal[v & 3] >> 4) & 0xf0;
  72 + g = pal[v & 3] & 0xf0;
  73 + b = (pal[v & 3] << 4) & 0xf0;
  74 + ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
  75 + d += BPP;
  76 + s ++;
  77 + width -= 4;
  78 + } while (width > 0);
  79 +}
  80 +
  81 +/*
  82 + * 4-bit colour
  83 + */
  84 +static void glue(draw_line4_, DEPTH)(
  85 + uint8_t *d, const uint8_t *s, int width, const uint16_t *pal)
  86 +{
  87 + uint8_t v, r, g, b;
  88 +
  89 + do {
  90 + v = ldub_raw((void *) s);
  91 + r = (pal[v & 0xf] >> 4) & 0xf0;
  92 + g = pal[v & 0xf] & 0xf0;
  93 + b = (pal[v & 0xf] << 4) & 0xf0;
  94 + ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
  95 + d += BPP;
  96 + v >>= 4;
  97 + r = (pal[v & 0xf] >> 4) & 0xf0;
  98 + g = pal[v & 0xf] & 0xf0;
  99 + b = (pal[v & 0xf] << 4) & 0xf0;
  100 + ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
  101 + d += BPP;
  102 + s ++;
  103 + width -= 2;
  104 + } while (width > 0);
  105 +}
  106 +
  107 +/*
  108 + * 8-bit colour
  109 + */
  110 +static void glue(draw_line8_, DEPTH)(
  111 + uint8_t *d, const uint8_t *s, int width, const uint16_t *pal)
  112 +{
  113 + uint8_t v, r, g, b;
  114 +
  115 + do {
  116 + v = ldub_raw((void *) s);
  117 + r = (pal[v] >> 4) & 0xf0;
  118 + g = pal[v] & 0xf0;
  119 + b = (pal[v] << 4) & 0xf0;
  120 + ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
  121 + s ++;
  122 + d += BPP;
  123 + } while (-- width != 0);
  124 +}
  125 +
  126 +/*
  127 + * 12-bit colour
  128 + */
  129 +static void glue(draw_line12_, DEPTH)(
  130 + uint8_t *d, const uint8_t *s, int width, const uint16_t *pal)
  131 +{
  132 + uint16_t v;
  133 + uint8_t r, g, b;
  134 +
  135 + do {
  136 + v = lduw_raw((void *) s);
  137 + r = (v >> 4) & 0xf0;
  138 + g = v & 0xf0;
  139 + b = (v << 4) & 0xf0;
  140 + ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
  141 + s += 2;
  142 + d += BPP;
  143 + } while (-- width != 0);
  144 +}
  145 +
  146 +/*
  147 + * 16-bit colour
  148 + */
  149 +static void glue(draw_line16_, DEPTH)(
  150 + uint8_t *d, const uint8_t *s, int width, const uint16_t *pal)
  151 +{
  152 +#if DEPTH == 16 && defined(WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
  153 + memcpy(d, s, width * 2);
  154 +#else
  155 + uint16_t v;
  156 + uint8_t r, g, b;
  157 +
  158 + do {
  159 + v = lduw_raw((void *) s);
  160 + r = (v >> 8) & 0xf8;
  161 + g = (v >> 3) & 0xfc;
  162 + b = (v << 3) & 0xf8;
  163 + ((PIXEL_TYPE *) d)[0] = glue(rgb_to_pixel, DEPTH)(r, g, b);
  164 + s += 2;
  165 + d += BPP;
  166 + } while (-- width != 0);
  167 +#endif
  168 +}
  169 +
  170 +#undef DEPTH
  171 +#undef BPP
  172 +#undef PIXEL_TYPE
... ...
hw/omap_lcdc.c 0 → 100644
  View file @c3d2689
  1 +/*
  2 + * OMAP LCD controller.
  3 + *
  4 + * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
  5 + *
  6 + * This program is free software; you can redistribute it and/or
  7 + * modify it under the terms of the GNU General Public License as
  8 + * published by the Free Software Foundation; either version 2 of
  9 + * the License, or (at your option) any later version.
  10 + *
  11 + * This program is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 + * GNU General Public License for more details.
  15 + *
  16 + * You should have received a copy of the GNU General Public License
  17 + * along with this program; if not, write to the Free Software
  18 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19 + * MA 02111-1307 USA
  20 + */
  21 +#include "vl.h"
  22 +
  23 +struct omap_lcd_panel_s {
  24 + target_phys_addr_t base;
  25 + qemu_irq irq;
  26 + DisplayState *state;
  27 + ram_addr_t imif_base;
  28 + ram_addr_t emiff_base;
  29 +
  30 + int plm;
  31 + int tft;
  32 + int mono;
  33 + int enable;
  34 + int width;
  35 + int height;
  36 + int interrupts;
  37 + uint32_t timing[3];
  38 + uint32_t subpanel;
  39 + uint32_t ctrl;
  40 +
  41 + struct omap_dma_lcd_channel_s *dma;
  42 + uint16_t palette[256];
  43 + int palette_done;
  44 + int frame_done;
  45 + int invalidate;
  46 + int sync_error;
  47 +};
  48 +
  49 +static void omap_lcd_interrupts(struct omap_lcd_panel_s *s)
  50 +{
  51 + if (s->frame_done && (s->interrupts & 1)) {
  52 + qemu_irq_raise(s->irq);
  53 + return;
  54 + }
  55 +
  56 + if (s->palette_done && (s->interrupts & 2)) {
  57 + qemu_irq_raise(s->irq);
  58 + return;
  59 + }
  60 +
  61 + if (s->sync_error) {
  62 + qemu_irq_raise(s->irq);
  63 + return;
  64 + }
  65 +
  66 + qemu_irq_lower(s->irq);
  67 +}
  68 +
  69 +#include "pixel_ops.h"
  70 +
  71 +typedef void draw_line_func(
  72 + uint8_t *d, const uint8_t *s, int width, const uint16_t *pal);
  73 +
  74 +#define DEPTH 8
  75 +#include "omap_lcd_template.h"
  76 +#define DEPTH 15
  77 +#include "omap_lcd_template.h"
  78 +#define DEPTH 16
  79 +#include "omap_lcd_template.h"
  80 +#define DEPTH 32
  81 +#include "omap_lcd_template.h"
  82 +
  83 +static draw_line_func *draw_line_table2[33] = {
  84 + [0 ... 32] = 0,
  85 + [8] = draw_line2_8,
  86 + [15] = draw_line2_15,
  87 + [16] = draw_line2_16,
  88 + [32] = draw_line2_32,
  89 +}, *draw_line_table4[33] = {
  90 + [0 ... 32] = 0,
  91 + [8] = draw_line4_8,
  92 + [15] = draw_line4_15,
  93 + [16] = draw_line4_16,
  94 + [32] = draw_line4_32,
  95 +}, *draw_line_table8[33] = {
  96 + [0 ... 32] = 0,
  97 + [8] = draw_line8_8,
  98 + [15] = draw_line8_15,
  99 + [16] = draw_line8_16,
  100 + [32] = draw_line8_32,
  101 +}, *draw_line_table12[33] = {
  102 + [0 ... 32] = 0,
  103 + [8] = draw_line12_8,
  104 + [15] = draw_line12_15,
  105 + [16] = draw_line12_16,
  106 + [32] = draw_line12_32,
  107 +}, *draw_line_table16[33] = {
  108 + [0 ... 32] = 0,
  109 + [8] = draw_line16_8,
  110 + [15] = draw_line16_15,
  111 + [16] = draw_line16_16,
  112 + [32] = draw_line16_32,
  113 +};
  114 +
  115 +void omap_update_display(void *opaque)
  116 +{
  117 + struct omap_lcd_panel_s *omap_lcd = (struct omap_lcd_panel_s *) opaque;
  118 + draw_line_func *draw_line;
  119 + int size, dirty[2], minline, maxline, height;
  120 + int line, width, linesize, step, bpp, frame_offset;
  121 + ram_addr_t frame_base, scanline, newline, x;
  122 + uint8_t *s, *d;
  123 +
  124 + if (!omap_lcd || omap_lcd->plm == 1 ||
  125 + !omap_lcd->enable || !omap_lcd->state->depth)
  126 + return;
  127 +
  128 + frame_offset = 0;
  129 + if (omap_lcd->plm != 2) {
  130 + memcpy(omap_lcd->palette, phys_ram_base +
  131 + omap_lcd->dma->phys_framebuffer[
  132 + omap_lcd->dma->current_frame], 0x200);
  133 + switch (omap_lcd->palette[0] >> 12 & 7) {
  134 + case 3 ... 7:
  135 + frame_offset += 0x200;
  136 + break;
  137 + default:
  138 + frame_offset += 0x20;
  139 + }
  140 + }
  141 +
  142 + /* Colour depth */
  143 + switch ((omap_lcd->palette[0] >> 12) & 7) {
  144 + case 1:
  145 + draw_line = draw_line_table2[omap_lcd->state->depth];
  146 + bpp = 2;
  147 + break;
  148 +
  149 + case 2:
  150 + draw_line = draw_line_table4[omap_lcd->state->depth];
  151 + bpp = 4;
  152 + break;
  153 +
  154 + case 3:
  155 + draw_line = draw_line_table8[omap_lcd->state->depth];
  156 + bpp = 8;
  157 + break;
  158 +
  159 + case 4 ... 7:
  160 + if (!omap_lcd->tft)
  161 + draw_line = draw_line_table12[omap_lcd->state->depth];
  162 + else
  163 + draw_line = draw_line_table16[omap_lcd->state->depth];
  164 + bpp = 16;
  165 + break;
  166 +
  167 + default:
  168 + /* Unsupported at the moment. */
  169 + return;
  170 + }
  171 +
  172 + /* Resolution */
  173 + width = omap_lcd->width;
  174 + if (width != omap_lcd->state->width ||
  175 + omap_lcd->height != omap_lcd->state->height) {
  176 + dpy_resize(omap_lcd->state,
  177 + omap_lcd->width, omap_lcd->height);
  178 + omap_lcd->invalidate = 1;
  179 + }
  180 +
  181 + if (omap_lcd->dma->current_frame == 0)
  182 + size = omap_lcd->dma->src_f1_bottom - omap_lcd->dma->src_f1_top;
  183 + else
  184 + size = omap_lcd->dma->src_f2_bottom - omap_lcd->dma->src_f2_top;
  185 +
  186 + if (frame_offset + ((width * omap_lcd->height * bpp) >> 3) > size + 2) {
  187 + omap_lcd->sync_error = 1;
  188 + omap_lcd_interrupts(omap_lcd);
  189 + omap_lcd->enable = 0;
  190 + return;
  191 + }
  192 +
  193 + /* Content */
  194 + frame_base = omap_lcd->dma->phys_framebuffer[
  195 + omap_lcd->dma->current_frame] + frame_offset;
  196 + omap_lcd->dma->condition |= 1 << omap_lcd->dma->current_frame;
  197 + if (omap_lcd->dma->interrupts & 1)
  198 + qemu_irq_raise(omap_lcd->dma->irq);
  199 + if (omap_lcd->dma->dual)
  200 + omap_lcd->dma->current_frame ^= 1;
  201 +
  202 + if (!omap_lcd->state->depth)
  203 + return;
  204 +
  205 + line = 0;
  206 + height = omap_lcd->height;
  207 + if (omap_lcd->subpanel & (1 << 31)) {
  208 + if (omap_lcd->subpanel & (1 << 29))
  209 + line = (omap_lcd->subpanel >> 16) & 0x3ff;
  210 + else
  211 + height = (omap_lcd->subpanel >> 16) & 0x3ff;
  212 + /* TODO: fill the rest of the panel with DPD */
  213 + }
  214 + step = width * bpp >> 3;
  215 + scanline = frame_base + step * line;
  216 + s = (uint8_t *) (phys_ram_base + scanline);
  217 + d = omap_lcd->state->data;
  218 + linesize = omap_lcd->state->linesize;
  219 +
  220 + dirty[0] = dirty[1] =
  221 + cpu_physical_memory_get_dirty(scanline, VGA_DIRTY_FLAG);
  222 + minline = height;
  223 + maxline = line;
  224 + for (; line < height; line ++) {
  225 + newline = scanline + step;
  226 + for (x = scanline + TARGET_PAGE_SIZE; x < newline;
  227 + x += TARGET_PAGE_SIZE) {
  228 + dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
  229 + dirty[0] |= dirty[1];
  230 + }
  231 + if (dirty[0] || omap_lcd->invalidate) {
  232 + draw_line(d, s, width, omap_lcd->palette);
  233 + if (line < minline)
  234 + minline = line;
  235 + maxline = line + 1;
  236 + }
  237 + scanline = newline;
  238 + dirty[0] = dirty[1];
  239 + s += step;
  240 + d += linesize;
  241 + }
  242 +
  243 + if (maxline >= minline) {
  244 + dpy_update(omap_lcd->state, 0, minline, width, maxline);
  245 + cpu_physical_memory_reset_dirty(frame_base + step * minline,
  246 + frame_base + step * maxline, VGA_DIRTY_FLAG);
  247 + }
  248 +}
  249 +
  250 +static int ppm_save(const char *filename, uint8_t *data,
  251 + int w, int h, int linesize)
  252 +{
  253 + FILE *f;
  254 + uint8_t *d, *d1;
  255 + unsigned int v;
  256 + int y, x, bpp;
  257 +
  258 + f = fopen(filename, "wb");
  259 + if (!f)
  260 + return -1;
  261 + fprintf(f, "P6\n%d %d\n%d\n", w, h, 255);
  262 + d1 = data;
  263 + bpp = linesize / w;
  264 + for (y = 0; y < h; y ++) {
  265 + d = d1;
  266 + for (x = 0; x < w; x ++) {
  267 + v = *(uint32_t *) d;
  268 + switch (bpp) {
  269 + case 2:
  270 + fputc((v >> 8) & 0xf8, f);
  271 + fputc((v >> 3) & 0xfc, f);
  272 + fputc((v << 3) & 0xf8, f);
  273 + break;
  274 + case 3:
  275 + case 4:
  276 + default:
  277 + fputc((v >> 16) & 0xff, f);
  278 + fputc((v >> 8) & 0xff, f);
  279 + fputc((v) & 0xff, f);
  280 + break;
  281 + }
  282 + d += bpp;
  283 + }
  284 + d1 += linesize;
  285 + }
  286 + fclose(f);
  287 + return 0;
  288 +}
  289 +
  290 +void omap_screen_dump(void *opaque, const char *filename) {
  291 + struct omap_lcd_panel_s *omap_lcd = opaque;
  292 + omap_update_display(opaque);
  293 + if (omap_lcd && omap_lcd->state->data)
  294 + ppm_save(filename, omap_lcd->state->data,
  295 + omap_lcd->width, omap_lcd->height,
  296 + omap_lcd->state->linesize);
  297 +}
  298 +
  299 +void omap_invalidate_display(void *opaque) {
  300 + struct omap_lcd_panel_s *omap_lcd = opaque;
  301 + omap_lcd->invalidate = 1;
  302 +}
  303 +
  304 +void omap_lcd_update(struct omap_lcd_panel_s *s) {
  305 + if (!s->enable) {
  306 + s->dma->current_frame = -1;
  307 + s->sync_error = 0;
  308 + if (s->plm != 1)
  309 + s->frame_done = 1;
  310 + omap_lcd_interrupts(s);
  311 + return;
  312 + }
  313 +
  314 + if (s->dma->current_frame == -1) {
  315 + s->frame_done = 0;
  316 + s->palette_done = 0;
  317 + s->dma->current_frame = 0;
  318 + }
  319 +
  320 + if (!s->dma->mpu->port[s->dma->src].addr_valid(s->dma->mpu,
  321 + s->dma->src_f1_top) ||
  322 + !s->dma->mpu->port[
  323 + s->dma->src].addr_valid(s->dma->mpu,
  324 + s->dma->src_f1_bottom) ||
  325 + (s->dma->dual &&
  326 + (!s->dma->mpu->port[
  327 + s->dma->src].addr_valid(s->dma->mpu,
  328 + s->dma->src_f2_top) ||
  329 + !s->dma->mpu->port[
  330 + s->dma->src].addr_valid(s->dma->mpu,
  331 + s->dma->src_f2_bottom)))) {
  332 + s->dma->condition |= 1 << 2;
  333 + if (s->dma->interrupts & (1 << 1))
  334 + qemu_irq_raise(s->dma->irq);
  335 + s->enable = 0;
  336 + return;
  337 + }
  338 +
  339 + if (s->dma->src == imif) {
  340 + /* Framebuffers are in SRAM */
  341 + s->dma->phys_framebuffer[0] = s->imif_base +
  342 + s->dma->src_f1_top - OMAP_IMIF_BASE;
  343 +
  344 + s->dma->phys_framebuffer[1] = s->imif_base +
  345 + s->dma->src_f2_top - OMAP_IMIF_BASE;
  346 + } else {
  347 + /* Framebuffers are in RAM */
  348 + s->dma->phys_framebuffer[0] = s->emiff_base +
  349 + s->dma->src_f1_top - OMAP_EMIFF_BASE;
  350 +
  351 + s->dma->phys_framebuffer[1] = s->emiff_base +
  352 + s->dma->src_f2_top - OMAP_EMIFF_BASE;
  353 + }
  354 +
  355 + if (s->plm != 2 && !s->palette_done) {
  356 + memcpy(s->palette, phys_ram_base +
  357 + s->dma->phys_framebuffer[s->dma->current_frame], 0x200);
  358 + s->palette_done = 1;
  359 + omap_lcd_interrupts(s);
  360 + }
  361 +}
  362 +
  363 +static uint32_t omap_lcdc_read(void *opaque, target_phys_addr_t addr)
  364 +{
  365 + struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
  366 + int offset = addr - s->base;
  367 +
  368 + switch (offset) {
  369 + case 0x00: /* LCD_CONTROL */
  370 + return (s->tft << 23) | (s->plm << 20) |
  371 + (s->tft << 7) | (s->interrupts << 3) |
  372 + (s->mono << 1) | s->enable | s->ctrl | 0xfe000c34;
  373 +
  374 + case 0x04: /* LCD_TIMING0 */
  375 + return (s->timing[0] << 10) | (s->width - 1) | 0x0000000f;
  376 +
  377 + case 0x08: /* LCD_TIMING1 */
  378 + return (s->timing[1] << 10) | (s->height - 1);
  379 +
  380 + case 0x0c: /* LCD_TIMING2 */
  381 + return s->timing[2] | 0xfc000000;
  382 +
  383 + case 0x10: /* LCD_STATUS */
  384 + return (s->palette_done << 6) | (s->sync_error << 2) | s->frame_done;
  385 +
  386 + case 0x14: /* LCD_SUBPANEL */
  387 + return s->subpanel;
  388 +
  389 + default:
  390 + break;
  391 + }
  392 + OMAP_BAD_REG(addr);
  393 + return 0;
  394 +}
  395 +
  396 +static void omap_lcdc_write(void *opaque, target_phys_addr_t addr,
  397 + uint32_t value)
  398 +{
  399 + struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *) opaque;
  400 + int offset = addr - s->base;
  401 +
  402 + switch (offset) {
  403 + case 0x00: /* LCD_CONTROL */
  404 + s->plm = (value >> 20) & 3;
  405 + s->tft = (value >> 7) & 1;
  406 + s->interrupts = (value >> 3) & 3;
  407 + s->mono = (value >> 1) & 1;
  408 + s->ctrl = value & 0x01cff300;
  409 + if (s->enable != (value & 1)) {
  410 + s->enable = value & 1;
  411 + omap_lcd_update(s);
  412 + }
  413 + break;
  414 +
  415 + case 0x04: /* LCD_TIMING0 */
  416 + s->timing[0] = value >> 10;
  417 + s->width = (value & 0x3ff) + 1;
  418 + break;
  419 +
  420 + case 0x08: /* LCD_TIMING1 */
  421 + s->timing[1] = value >> 10;
  422 + s->height = (value & 0x3ff) + 1;
  423 + break;
  424 +
  425 + case 0x0c: /* LCD_TIMING2 */
  426 + s->timing[2] = value;
  427 + break;
  428 +
  429 + case 0x10: /* LCD_STATUS */
  430 + break;
  431 +
  432 + case 0x14: /* LCD_SUBPANEL */
  433 + s->subpanel = value & 0xa1ffffff;
  434 + break;
  435 +
  436 + default:
  437 + OMAP_BAD_REG(addr);
  438 + }
  439 +}
  440 +
  441 +static CPUReadMemoryFunc *omap_lcdc_readfn[] = {
  442 + omap_lcdc_read,
  443 + omap_lcdc_read,
  444 + omap_lcdc_read,
  445 +};
  446 +
  447 +static CPUWriteMemoryFunc *omap_lcdc_writefn[] = {
  448 + omap_lcdc_write,
  449 + omap_lcdc_write,
  450 + omap_lcdc_write,
  451 +};
  452 +
  453 +void omap_lcdc_reset(struct omap_lcd_panel_s *s)
  454 +{
  455 + s->dma->current_frame = -1;
  456 + s->plm = 0;
  457 + s->tft = 0;
  458 + s->mono = 0;
  459 + s->enable = 0;
  460 + s->width = 0;
  461 + s->height = 0;
  462 + s->interrupts = 0;
  463 + s->timing[0] = 0;
  464 + s->timing[1] = 0;
  465 + s->timing[2] = 0;
  466 + s->subpanel = 0;
  467 + s->palette_done = 0;
  468 + s->frame_done = 0;
  469 + s->sync_error = 0;
  470 + s->invalidate = 1;
  471 + s->subpanel = 0;
  472 + s->ctrl = 0;
  473 +}
  474 +
  475 +struct omap_lcd_panel_s *omap_lcdc_init(target_phys_addr_t base, qemu_irq irq,
  476 + struct omap_dma_lcd_channel_s *dma, DisplayState *ds,
  477 + ram_addr_t imif_base, ram_addr_t emiff_base, omap_clk clk)
  478 +{
  479 + int iomemtype;
  480 + struct omap_lcd_panel_s *s = (struct omap_lcd_panel_s *)
  481 + qemu_mallocz(sizeof(struct omap_lcd_panel_s));
  482 +
  483 + s->irq = irq;
  484 + s->dma = dma;
  485 + s->base = base;
  486 + s->state = ds;
  487 + s->imif_base = imif_base;
  488 + s->emiff_base = emiff_base;
  489 + omap_lcdc_reset(s);
  490 +
  491 + iomemtype = cpu_register_io_memory(0, omap_lcdc_readfn,
  492 + omap_lcdc_writefn, s);
  493 + cpu_register_physical_memory(s->base, 0x100, iomemtype);
  494 +
  495 + graphic_console_init(ds, omap_update_display,
  496 + omap_invalidate_display, omap_screen_dump, s);
  497 +
  498 + return s;
  499 +}
... ...