gwj / at91sam9263 · Commits

Commit 0ca9d3807c8c429f7b21ffcac7f7acdd4d9659b0

Authored by aurel32
1 parent 6b59fc74

Use float32/64 instead of float/double 

The patch below uses the float32 and float64 types instead of the float
and double types in the PPC code. This doesn't change anything when
using softfloat-native as the types are the same, but that helps
compiling the PPC target with softfloat.

It also defines a new union CPU_FloatU in addition to CPU_DoubleU, and
use them instead of identical unions that are defined in numerous
places.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4047 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 6 changed files with 241 additions and 458 deletions
cpu-all.h
  View file @0ca9d38
... ... @@ -116,6 +116,11 @@ static inline void tswap64s(uint64_t *s)
116 116 #define bswaptls(s) bswap64s(s)
117 117 #endif
118 118  
  119 +typedef union {
  120 + float32 f;
  121 + uint32_t l;
  122 +} CPU_FloatU;
  123 +
119 124 /* NOTE: arm FPA is horrible as double 32 bit words are stored in big
120 125 endian ! */
121 126 typedef union {
... ...
target-ppc/op.c
  View file @0ca9d38
... ... @@ -580,47 +580,28 @@ void OPPROTO op_float_check_status (void)
580 580 }
581 581 #endif
582 582  
583   -#if defined(WORDS_BIGENDIAN)
584   -#define WORD0 0
585   -#define WORD1 1
586   -#else
587   -#define WORD0 1
588   -#define WORD1 0
589   -#endif
590 583 void OPPROTO op_load_fpscr_FT0 (void)
591 584 {
592 585 /* The 32 MSB of the target fpr are undefined.
593 586 * They'll be zero...
594 587 */
595   - union {
596   - float64 d;
597   - struct {
598   - uint32_t u[2];
599   - } s;
600   - } u;
601   -
602   - u.s.u[WORD0] = 0;
603   - u.s.u[WORD1] = env->fpscr;
  588 + CPU_DoubleU u;
  589 +
  590 + u.l.upper = 0;
  591 + u.l.lower = env->fpscr;
604 592 FT0 = u.d;
605 593 RETURN();
606 594 }
607 595  
608 596 void OPPROTO op_set_FT0 (void)
609 597 {
610   - union {
611   - float64 d;
612   - struct {
613   - uint32_t u[2];
614   - } s;
615   - } u;
  598 + CPU_DoubleU u;
616 599  
617   - u.s.u[WORD0] = 0;
618   - u.s.u[WORD1] = PARAM1;
  600 + u.l.upper = 0;
  601 + u.l.lower = PARAM1;
619 602 FT0 = u.d;
620 603 RETURN();
621 604 }
622   -#undef WORD0
623   -#undef WORD1
624 605  
625 606 void OPPROTO op_load_fpscr_T0 (void)
626 607 {
... ... @@ -3226,27 +3207,21 @@ void OPPROTO op_efststeq (void)
3226 3207  
3227 3208 void OPPROTO op_efdsub (void)
3228 3209 {
3229   - union {
3230   - uint64_t u;
3231   - float64 f;
3232   - } u1, u2;
3233   - u1.u = T0_64;
3234   - u2.u = T1_64;
3235   - u1.f = float64_sub(u1.f, u2.f, &env->spe_status);
3236   - T0_64 = u1.u;
  3210 + CPU_DoubleU u1, u2;
  3211 + u1.ll = T0_64;
  3212 + u2.ll = T1_64;
  3213 + u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
  3214 + T0_64 = u1.ll;
3237 3215 RETURN();
3238 3216 }
3239 3217  
3240 3218 void OPPROTO op_efdadd (void)
3241 3219 {
3242   - union {
3243   - uint64_t u;
3244   - float64 f;
3245   - } u1, u2;
3246   - u1.u = T0_64;
3247   - u2.u = T1_64;
3248   - u1.f = float64_add(u1.f, u2.f, &env->spe_status);
3249   - T0_64 = u1.u;
  3220 + CPU_DoubleU u1, u2;
  3221 + u1.ll = T0_64;
  3222 + u2.ll = T1_64;
  3223 + u1.d = float64_add(u1.d, u2.d, &env->spe_status);
  3224 + T0_64 = u1.ll;
3250 3225 RETURN();
3251 3226 }
3252 3227  
... ... @@ -3282,27 +3257,21 @@ void OPPROTO op_efdneg (void)
3282 3257  
3283 3258 void OPPROTO op_efddiv (void)
3284 3259 {
3285   - union {
3286   - uint64_t u;
3287   - float64 f;
3288   - } u1, u2;
3289   - u1.u = T0_64;
3290   - u2.u = T1_64;
3291   - u1.f = float64_div(u1.f, u2.f, &env->spe_status);
3292   - T0_64 = u1.u;
  3260 + CPU_DoubleU u1, u2;
  3261 + u1.ll = T0_64;
  3262 + u2.ll = T1_64;
  3263 + u1.d = float64_div(u1.d, u2.d, &env->spe_status);
  3264 + T0_64 = u1.ll;
3293 3265 RETURN();
3294 3266 }
3295 3267  
3296 3268 void OPPROTO op_efdmul (void)
3297 3269 {
3298   - union {
3299   - uint64_t u;
3300   - float64 f;
3301   - } u1, u2;
3302   - u1.u = T0_64;
3303   - u2.u = T1_64;
3304   - u1.f = float64_mul(u1.f, u2.f, &env->spe_status);
3305   - T0_64 = u1.u;
  3270 + CPU_DoubleU u1, u2;
  3271 + u1.ll = T0_64;
  3272 + u2.ll = T1_64;
  3273 + u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
  3274 + T0_64 = u1.ll;
3306 3275 RETURN();
3307 3276 }
3308 3277  
... ...
target-ppc/op_helper.c
  View file @0ca9d38
... ... @@ -455,53 +455,41 @@ void do_popcntb_64 (void)
455 455  
456 456 /*****************************************************************************/
457 457 /* Floating point operations helpers */
458   -static always_inline int fpisneg (float64 f)
  458 +static always_inline int fpisneg (float64 d)
459 459 {
460   - union {
461   - float64 f;
462   - uint64_t u;
463   - } u;
  460 + CPU_DoubleU u;
464 461  
465   - u.f = f;
  462 + u.d = d;
466 463  
467   - return u.u >> 63 != 0;
  464 + return u.ll >> 63 != 0;
468 465 }
469 466  
470   -static always_inline int isden (float f)
  467 +static always_inline int isden (float64 d)
471 468 {
472   - union {
473   - float64 f;
474   - uint64_t u;
475   - } u;
  469 + CPU_DoubleU u;
476 470  
477   - u.f = f;
  471 + u.d = d;
478 472  
479   - return ((u.u >> 52) & 0x7FF) == 0;
  473 + return ((u.ll >> 52) & 0x7FF) == 0;
480 474 }
481 475  
482   -static always_inline int iszero (float64 f)
  476 +static always_inline int iszero (float64 d)
483 477 {
484   - union {
485   - float64 f;
486   - uint64_t u;
487   - } u;
  478 + CPU_DoubleU u;
488 479  
489   - u.f = f;
  480 + u.d = d;
490 481  
491   - return (u.u & ~0x8000000000000000ULL) == 0;
  482 + return (u.ll & ~0x8000000000000000ULL) == 0;
492 483 }
493 484  
494   -static always_inline int isinfinity (float64 f)
  485 +static always_inline int isinfinity (float64 d)
495 486 {
496   - union {
497   - float64 f;
498   - uint64_t u;
499   - } u;
  487 + CPU_DoubleU u;
500 488  
501   - u.f = f;
  489 + u.d = d;
502 490  
503   - return ((u.u >> 52) & 0x7FF) == 0x7FF &&
504   - (u.u & 0x000FFFFFFFFFFFFFULL) == 0;
  491 + return ((u.ll >> 52) & 0x7FF) == 0x7FF &&
  492 + (u.ll & 0x000FFFFFFFFFFFFFULL) == 0;
505 493 }
506 494  
507 495 void do_compute_fprf (int set_fprf)
... ... @@ -638,10 +626,7 @@ static always_inline void fload_invalid_op_excp (int op)
638 626  
639 627 static always_inline void float_zero_divide_excp (void)
640 628 {
641   - union {
642   - float64 f;
643   - uint64_t u;
644   - } u0, u1;
  629 + CPU_DoubleU u0, u1;
645 630  
646 631 env->fpscr |= 1 << FPSCR_ZX;
647 632 env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
... ... @@ -656,11 +641,11 @@ static always_inline void float_zero_divide_excp (void)
656 641 }
657 642 } else {
658 643 /* Set the result to infinity */
659   - u0.f = FT0;
660   - u1.f = FT1;
661   - u0.u = ((u0.u ^ u1.u) & 0x8000000000000000ULL);
662   - u0.u |= 0x7FFULL << 52;
663   - FT0 = u0.f;
  644 + u0.d = FT0;
  645 + u1.d = FT1;
  646 + u0.ll = ((u0.ll ^ u1.ll) & 0x8000000000000000ULL);
  647 + u0.ll |= 0x7FFULL << 52;
  648 + FT0 = u0.d;
664 649 }
665 650 }
666 651  
... ... @@ -865,18 +850,13 @@ void do_store_fpscr (uint32_t mask)
865 850 /*
866 851 * We use only the 32 LSB of the incoming fpr
867 852 */
868   - union {
869   - double d;
870   - struct {
871   - uint32_t u[2];
872   - } s;
873   - } u;
  853 + CPU_DoubleU u;
874 854 uint32_t prev, new;
875 855 int i;
876 856  
877 857 u.d = FT0;
878 858 prev = env->fpscr;
879   - new = u.s.u[WORD1];
  859 + new = u.l.lower;
880 860 new &= ~0x90000000;
881 861 new |= prev & 0x90000000;
882 862 for (i = 0; i < 7; i++) {
... ... @@ -992,10 +972,7 @@ void do_fdiv (void)
992 972  
993 973 void do_fctiw (void)
994 974 {
995   - union {
996   - double d;
997   - uint64_t i;
998   - } p;
  975 + CPU_DoubleU p;
999 976  
1000 977 if (unlikely(float64_is_signaling_nan(FT0))) {
1001 978 /* sNaN conversion */
... ... @@ -1004,12 +981,12 @@ void do_fctiw (void)
1004 981 /* qNan / infinity conversion */
1005 982 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1006 983 } else {
1007   - p.i = float64_to_int32(FT0, &env->fp_status);
  984 + p.ll = float64_to_int32(FT0, &env->fp_status);
1008 985 #if USE_PRECISE_EMULATION
1009 986 /* XXX: higher bits are not supposed to be significant.
1010 987 * to make tests easier, return the same as a real PowerPC 750
1011 988 */
1012   - p.i |= 0xFFF80000ULL << 32;
  989 + p.ll |= 0xFFF80000ULL << 32;
1013 990 #endif
1014 991 FT0 = p.d;
1015 992 }
... ... @@ -1017,10 +994,7 @@ void do_fctiw (void)
1017 994  
1018 995 void do_fctiwz (void)
1019 996 {
1020   - union {
1021   - double d;
1022   - uint64_t i;
1023   - } p;
  997 + CPU_DoubleU p;
1024 998  
1025 999 if (unlikely(float64_is_signaling_nan(FT0))) {
1026 1000 /* sNaN conversion */
... ... @@ -1029,12 +1003,12 @@ void do_fctiwz (void)
1029 1003 /* qNan / infinity conversion */
1030 1004 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1031 1005 } else {
1032   - p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status);
  1006 + p.ll = float64_to_int32_round_to_zero(FT0, &env->fp_status);
1033 1007 #if USE_PRECISE_EMULATION
1034 1008 /* XXX: higher bits are not supposed to be significant.
1035 1009 * to make tests easier, return the same as a real PowerPC 750
1036 1010 */
1037   - p.i |= 0xFFF80000ULL << 32;
  1011 + p.ll |= 0xFFF80000ULL << 32;
1038 1012 #endif
1039 1013 FT0 = p.d;
1040 1014 }
... ... @@ -1043,21 +1017,15 @@ void do_fctiwz (void)
1043 1017 #if defined(TARGET_PPC64)
1044 1018 void do_fcfid (void)
1045 1019 {
1046   - union {
1047   - double d;
1048   - uint64_t i;
1049   - } p;
  1020 + CPU_DoubleU p;
1050 1021  
1051 1022 p.d = FT0;
1052   - FT0 = int64_to_float64(p.i, &env->fp_status);
  1023 + FT0 = int64_to_float64(p.ll, &env->fp_status);
1053 1024 }
1054 1025  
1055 1026 void do_fctid (void)
1056 1027 {
1057   - union {
1058   - double d;
1059   - uint64_t i;
1060   - } p;
  1028 + CPU_DoubleU p;
1061 1029  
1062 1030 if (unlikely(float64_is_signaling_nan(FT0))) {
1063 1031 /* sNaN conversion */
... ... @@ -1066,17 +1034,14 @@ void do_fctid (void)
1066 1034 /* qNan / infinity conversion */
1067 1035 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1068 1036 } else {
1069   - p.i = float64_to_int64(FT0, &env->fp_status);
  1037 + p.ll = float64_to_int64(FT0, &env->fp_status);
1070 1038 FT0 = p.d;
1071 1039 }
1072 1040 }
1073 1041  
1074 1042 void do_fctidz (void)
1075 1043 {
1076   - union {
1077   - double d;
1078   - uint64_t i;
1079   - } p;
  1044 + CPU_DoubleU p;
1080 1045  
1081 1046 if (unlikely(float64_is_signaling_nan(FT0))) {
1082 1047 /* sNaN conversion */
... ... @@ -1085,7 +1050,7 @@ void do_fctidz (void)
1085 1050 /* qNan / infinity conversion */
1086 1051 fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
1087 1052 } else {
1088   - p.i = float64_to_int64_round_to_zero(FT0, &env->fp_status);
  1053 + p.ll = float64_to_int64_round_to_zero(FT0, &env->fp_status);
1089 1054 FT0 = p.d;
1090 1055 }
1091 1056 }
... ... @@ -1271,10 +1236,7 @@ void do_fsqrt (void)
1271 1236  
1272 1237 void do_fre (void)
1273 1238 {
1274   - union {
1275   - double d;
1276   - uint64_t i;
1277   - } p;
  1239 + CPU_DoubleU p;
1278 1240  
1279 1241 if (unlikely(float64_is_signaling_nan(FT0))) {
1280 1242 /* sNaN reciprocal */
... ... @@ -1286,16 +1248,16 @@ void do_fre (void)
1286 1248 FT0 = float64_div(1.0, FT0, &env->fp_status);
1287 1249 } else {
1288 1250 p.d = FT0;
1289   - if (p.i == 0x8000000000000000ULL) {
1290   - p.i = 0xFFF0000000000000ULL;
1291   - } else if (p.i == 0x0000000000000000ULL) {
1292   - p.i = 0x7FF0000000000000ULL;
  1251 + if (p.ll == 0x8000000000000000ULL) {
  1252 + p.ll = 0xFFF0000000000000ULL;
  1253 + } else if (p.ll == 0x0000000000000000ULL) {
  1254 + p.ll = 0x7FF0000000000000ULL;
1293 1255 } else if (isnan(FT0)) {
1294   - p.i = 0x7FF8000000000000ULL;
  1256 + p.ll = 0x7FF8000000000000ULL;
1295 1257 } else if (fpisneg(FT0)) {
1296   - p.i = 0x8000000000000000ULL;
  1258 + p.ll = 0x8000000000000000ULL;
1297 1259 } else {
1298   - p.i = 0x0000000000000000ULL;
  1260 + p.ll = 0x0000000000000000ULL;
1299 1261 }
1300 1262 FT0 = p.d;
1301 1263 }
... ... @@ -1303,10 +1265,7 @@ void do_fre (void)
1303 1265  
1304 1266 void do_fres (void)
1305 1267 {
1306   - union {
1307   - double d;
1308   - uint64_t i;
1309   - } p;
  1268 + CPU_DoubleU p;
1310 1269  
1311 1270 if (unlikely(float64_is_signaling_nan(FT0))) {
1312 1271 /* sNaN reciprocal */
... ... @@ -1323,16 +1282,16 @@ void do_fres (void)
1323 1282 #endif
1324 1283 } else {
1325 1284 p.d = FT0;
1326   - if (p.i == 0x8000000000000000ULL) {
1327   - p.i = 0xFFF0000000000000ULL;
1328   - } else if (p.i == 0x0000000000000000ULL) {
1329   - p.i = 0x7FF0000000000000ULL;
  1285 + if (p.ll == 0x8000000000000000ULL) {
  1286 + p.ll = 0xFFF0000000000000ULL;
  1287 + } else if (p.ll == 0x0000000000000000ULL) {
  1288 + p.ll = 0x7FF0000000000000ULL;
1330 1289 } else if (isnan(FT0)) {
1331   - p.i = 0x7FF8000000000000ULL;
  1290 + p.ll = 0x7FF8000000000000ULL;
1332 1291 } else if (fpisneg(FT0)) {
1333   - p.i = 0x8000000000000000ULL;
  1292 + p.ll = 0x8000000000000000ULL;
1334 1293 } else {
1335   - p.i = 0x0000000000000000ULL;
  1294 + p.ll = 0x0000000000000000ULL;
1336 1295 }
1337 1296 FT0 = p.d;
1338 1297 }
... ... @@ -1340,10 +1299,7 @@ void do_fres (void)
1340 1299  
1341 1300 void do_frsqrte (void)
1342 1301 {
1343   - union {
1344   - double d;
1345   - uint64_t i;
1346   - } p;
  1302 + CPU_DoubleU p;
1347 1303  
1348 1304 if (unlikely(float64_is_signaling_nan(FT0))) {
1349 1305 /* sNaN reciprocal square root */
... ... @@ -1356,16 +1312,16 @@ void do_frsqrte (void)
1356 1312 FT0 = float32_div(1.0, FT0, &env->fp_status);
1357 1313 } else {
1358 1314 p.d = FT0;
1359   - if (p.i == 0x8000000000000000ULL) {
1360   - p.i = 0xFFF0000000000000ULL;
1361   - } else if (p.i == 0x0000000000000000ULL) {
1362   - p.i = 0x7FF0000000000000ULL;
  1315 + if (p.ll == 0x8000000000000000ULL) {
  1316 + p.ll = 0xFFF0000000000000ULL;
  1317 + } else if (p.ll == 0x0000000000000000ULL) {
  1318 + p.ll = 0x7FF0000000000000ULL;
1363 1319 } else if (isnan(FT0)) {
1364   - p.i |= 0x000FFFFFFFFFFFFFULL;
  1320 + p.ll |= 0x000FFFFFFFFFFFFFULL;
1365 1321 } else if (fpisneg(FT0)) {
1366   - p.i = 0x7FF8000000000000ULL;
  1322 + p.ll = 0x7FF8000000000000ULL;
1367 1323 } else {
1368   - p.i = 0x0000000000000000ULL;
  1324 + p.ll = 0x0000000000000000ULL;
1369 1325 }
1370 1326 FT0 = p.d;
1371 1327 }
... ... @@ -2056,36 +2012,27 @@ DO_SPE_CMP(cmpltu);
2056 2012 /* Single precision floating-point conversions from/to integer */
2057 2013 static always_inline uint32_t _do_efscfsi (int32_t val)
2058 2014 {
2059   - union {
2060   - uint32_t u;
2061   - float32 f;
2062   - } u;
  2015 + CPU_FloatU u;
2063 2016  
2064 2017 u.f = int32_to_float32(val, &env->spe_status);
2065 2018  
2066   - return u.u;
  2019 + return u.l;
2067 2020 }
2068 2021  
2069 2022 static always_inline uint32_t _do_efscfui (uint32_t val)
2070 2023 {
2071   - union {
2072   - uint32_t u;
2073   - float32 f;
2074   - } u;
  2024 + CPU_FloatU u;
2075 2025  
2076 2026 u.f = uint32_to_float32(val, &env->spe_status);
2077 2027  
2078   - return u.u;
  2028 + return u.l;
2079 2029 }
2080 2030  
2081 2031 static always_inline int32_t _do_efsctsi (uint32_t val)
2082 2032 {
2083   - union {
2084   - int32_t u;
2085   - float32 f;
2086   - } u;
  2033 + CPU_FloatU u;
2087 2034  
2088   - u.u = val;
  2035 + u.l = val;
2089 2036 /* NaN are not treated the same way IEEE 754 does */
2090 2037 if (unlikely(isnan(u.f)))
2091 2038 return 0;
... ... @@ -2095,12 +2042,9 @@ static always_inline int32_t _do_efsctsi (uint32_t val)
2095 2042  
2096 2043 static always_inline uint32_t _do_efsctui (uint32_t val)
2097 2044 {
2098   - union {
2099   - int32_t u;
2100   - float32 f;
2101   - } u;
  2045 + CPU_FloatU u;
2102 2046  
2103   - u.u = val;
  2047 + u.l = val;
2104 2048 /* NaN are not treated the same way IEEE 754 does */
2105 2049 if (unlikely(isnan(u.f)))
2106 2050 return 0;
... ... @@ -2110,12 +2054,9 @@ static always_inline uint32_t _do_efsctui (uint32_t val)
2110 2054  
2111 2055 static always_inline int32_t _do_efsctsiz (uint32_t val)
2112 2056 {
2113   - union {
2114   - int32_t u;
2115   - float32 f;
2116   - } u;
  2057 + CPU_FloatU u;
2117 2058  
2118   - u.u = val;
  2059 + u.l = val;
2119 2060 /* NaN are not treated the same way IEEE 754 does */
2120 2061 if (unlikely(isnan(u.f)))
2121 2062 return 0;
... ... @@ -2125,12 +2066,9 @@ static always_inline int32_t _do_efsctsiz (uint32_t val)
2125 2066  
2126 2067 static always_inline uint32_t _do_efsctuiz (uint32_t val)
2127 2068 {
2128   - union {
2129   - int32_t u;
2130   - float32 f;
2131   - } u;
  2069 + CPU_FloatU u;
2132 2070  
2133   - u.u = val;
  2071 + u.l = val;
2134 2072 /* NaN are not treated the same way IEEE 754 does */
2135 2073 if (unlikely(isnan(u.f)))
2136 2074 return 0;
... ... @@ -2171,43 +2109,34 @@ void do_efsctuiz (void)
2171 2109 /* Single precision floating-point conversion to/from fractional */
2172 2110 static always_inline uint32_t _do_efscfsf (uint32_t val)
2173 2111 {
2174   - union {
2175   - uint32_t u;
2176   - float32 f;
2177   - } u;
  2112 + CPU_FloatU u;
2178 2113 float32 tmp;
2179 2114  
2180 2115 u.f = int32_to_float32(val, &env->spe_status);
2181 2116 tmp = int64_to_float32(1ULL << 32, &env->spe_status);
2182 2117 u.f = float32_div(u.f, tmp, &env->spe_status);
2183 2118  
2184   - return u.u;
  2119 + return u.l;
2185 2120 }
2186 2121  
2187 2122 static always_inline uint32_t _do_efscfuf (uint32_t val)
2188 2123 {
2189   - union {
2190   - uint32_t u;
2191   - float32 f;
2192   - } u;
  2124 + CPU_FloatU u;
2193 2125 float32 tmp;
2194 2126  
2195 2127 u.f = uint32_to_float32(val, &env->spe_status);
2196 2128 tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
2197 2129 u.f = float32_div(u.f, tmp, &env->spe_status);
2198 2130  
2199   - return u.u;
  2131 + return u.l;
2200 2132 }
2201 2133  
2202 2134 static always_inline int32_t _do_efsctsf (uint32_t val)
2203 2135 {
2204   - union {
2205   - int32_t u;
2206   - float32 f;
2207   - } u;
  2136 + CPU_FloatU u;
2208 2137 float32 tmp;
2209 2138  
2210   - u.u = val;
  2139 + u.l = val;
2211 2140 /* NaN are not treated the same way IEEE 754 does */
2212 2141 if (unlikely(isnan(u.f)))
2213 2142 return 0;
... ... @@ -2219,13 +2148,10 @@ static always_inline int32_t _do_efsctsf (uint32_t val)
2219 2148  
2220 2149 static always_inline uint32_t _do_efsctuf (uint32_t val)
2221 2150 {
2222   - union {
2223   - int32_t u;
2224   - float32 f;
2225   - } u;
  2151 + CPU_FloatU u;
2226 2152 float32 tmp;
2227 2153  
2228   - u.u = val;
  2154 + u.l = val;
2229 2155 /* NaN are not treated the same way IEEE 754 does */
2230 2156 if (unlikely(isnan(u.f)))
2231 2157 return 0;
... ... @@ -2237,13 +2163,10 @@ static always_inline uint32_t _do_efsctuf (uint32_t val)
2237 2163  
2238 2164 static always_inline int32_t _do_efsctsfz (uint32_t val)
2239 2165 {
2240   - union {
2241   - int32_t u;
2242   - float32 f;
2243   - } u;
  2166 + CPU_FloatU u;
2244 2167 float32 tmp;
2245 2168  
2246   - u.u = val;
  2169 + u.l = val;
2247 2170 /* NaN are not treated the same way IEEE 754 does */
2248 2171 if (unlikely(isnan(u.f)))
2249 2172 return 0;
... ... @@ -2255,13 +2178,10 @@ static always_inline int32_t _do_efsctsfz (uint32_t val)
2255 2178  
2256 2179 static always_inline uint32_t _do_efsctufz (uint32_t val)
2257 2180 {
2258   - union {
2259   - int32_t u;
2260   - float32 f;
2261   - } u;
  2181 + CPU_FloatU u;
2262 2182 float32 tmp;
2263 2183  
2264   - u.u = val;
  2184 + u.l = val;
2265 2185 /* NaN are not treated the same way IEEE 754 does */
2266 2186 if (unlikely(isnan(u.f)))
2267 2187 return 0;
... ... @@ -2338,86 +2258,68 @@ void do_efdcmpeq (void)
2338 2258 /* Double precision floating-point conversion to/from integer */
2339 2259 static always_inline uint64_t _do_efdcfsi (int64_t val)
2340 2260 {
2341   - union {
2342   - uint64_t u;
2343   - float64 f;
2344   - } u;
  2261 + CPU_DoubleU u;
2345 2262  
2346   - u.f = int64_to_float64(val, &env->spe_status);
  2263 + u.d = int64_to_float64(val, &env->spe_status);
2347 2264  
2348   - return u.u;
  2265 + return u.ll;
2349 2266 }
2350 2267  
2351 2268 static always_inline uint64_t _do_efdcfui (uint64_t val)
2352 2269 {
2353   - union {
2354   - uint64_t u;
2355   - float64 f;
2356   - } u;
  2270 + CPU_DoubleU u;
2357 2271  
2358   - u.f = uint64_to_float64(val, &env->spe_status);
  2272 + u.d = uint64_to_float64(val, &env->spe_status);
2359 2273  
2360   - return u.u;
  2274 + return u.ll;
2361 2275 }
2362 2276  
2363 2277 static always_inline int64_t _do_efdctsi (uint64_t val)
2364 2278 {
2365   - union {
2366   - int64_t u;
2367   - float64 f;
2368   - } u;
  2279 + CPU_DoubleU u;
2369 2280  
2370   - u.u = val;
  2281 + u.ll = val;
2371 2282 /* NaN are not treated the same way IEEE 754 does */
2372   - if (unlikely(isnan(u.f)))
  2283 + if (unlikely(isnan(u.d)))
2373 2284 return 0;
2374 2285  
2375   - return float64_to_int64(u.f, &env->spe_status);
  2286 + return float64_to_int64(u.d, &env->spe_status);
2376 2287 }
2377 2288  
2378 2289 static always_inline uint64_t _do_efdctui (uint64_t val)
2379 2290 {
2380   - union {
2381   - int64_t u;
2382   - float64 f;
2383   - } u;
  2291 + CPU_DoubleU u;
2384 2292  
2385   - u.u = val;
  2293 + u.ll = val;
2386 2294 /* NaN are not treated the same way IEEE 754 does */
2387   - if (unlikely(isnan(u.f)))
  2295 + if (unlikely(isnan(u.d)))
2388 2296 return 0;
2389 2297  
2390   - return float64_to_uint64(u.f, &env->spe_status);
  2298 + return float64_to_uint64(u.d, &env->spe_status);
2391 2299 }
2392 2300  
2393 2301 static always_inline int64_t _do_efdctsiz (uint64_t val)
2394 2302 {
2395   - union {
2396   - int64_t u;
2397   - float64 f;
2398   - } u;
  2303 + CPU_DoubleU u;
2399 2304  
2400   - u.u = val;
  2305 + u.ll = val;
2401 2306 /* NaN are not treated the same way IEEE 754 does */
2402   - if (unlikely(isnan(u.f)))
  2307 + if (unlikely(isnan(u.d)))
2403 2308 return 0;
2404 2309  
2405   - return float64_to_int64_round_to_zero(u.f, &env->spe_status);
  2310 + return float64_to_int64_round_to_zero(u.d, &env->spe_status);
2406 2311 }
2407 2312  
2408 2313 static always_inline uint64_t _do_efdctuiz (uint64_t val)
2409 2314 {
2410   - union {
2411   - int64_t u;
2412   - float64 f;
2413   - } u;
  2315 + CPU_DoubleU u;
2414 2316  
2415   - u.u = val;
  2317 + u.ll = val;
2416 2318 /* NaN are not treated the same way IEEE 754 does */
2417   - if (unlikely(isnan(u.f)))
  2319 + if (unlikely(isnan(u.d)))
2418 2320 return 0;
2419 2321  
2420   - return float64_to_uint64_round_to_zero(u.f, &env->spe_status);
  2322 + return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
2421 2323 }
2422 2324  
2423 2325 void do_efdcfsi (void)
... ... @@ -2453,104 +2355,86 @@ void do_efdctuiz (void)
2453 2355 /* Double precision floating-point conversion to/from fractional */
2454 2356 static always_inline uint64_t _do_efdcfsf (int64_t val)
2455 2357 {
2456   - union {
2457   - uint64_t u;
2458   - float64 f;
2459   - } u;
  2358 + CPU_DoubleU u;
2460 2359 float64 tmp;
2461 2360  
2462   - u.f = int32_to_float64(val, &env->spe_status);
  2361 + u.d = int32_to_float64(val, &env->spe_status);
2463 2362 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2464   - u.f = float64_div(u.f, tmp, &env->spe_status);
  2363 + u.d = float64_div(u.d, tmp, &env->spe_status);
2465 2364  
2466   - return u.u;
  2365 + return u.ll;
2467 2366 }
2468 2367  
2469 2368 static always_inline uint64_t _do_efdcfuf (uint64_t val)
2470 2369 {
2471   - union {
2472   - uint64_t u;
2473   - float64 f;
2474   - } u;
  2370 + CPU_DoubleU u;
2475 2371 float64 tmp;
2476 2372  
2477   - u.f = uint32_to_float64(val, &env->spe_status);
  2373 + u.d = uint32_to_float64(val, &env->spe_status);
2478 2374 tmp = int64_to_float64(1ULL << 32, &env->spe_status);
2479   - u.f = float64_div(u.f, tmp, &env->spe_status);
  2375 + u.d = float64_div(u.d, tmp, &env->spe_status);
2480 2376  
2481   - return u.u;
  2377 + return u.ll;
2482 2378 }
2483 2379  
2484 2380 static always_inline int64_t _do_efdctsf (uint64_t val)
2485 2381 {
2486   - union {
2487   - int64_t u;
2488   - float64 f;
2489   - } u;
  2382 + CPU_DoubleU u;
2490 2383 float64 tmp;
2491 2384  
2492   - u.u = val;
  2385 + u.ll = val;
2493 2386 /* NaN are not treated the same way IEEE 754 does */
2494   - if (unlikely(isnan(u.f)))
  2387 + if (unlikely(isnan(u.d)))
2495 2388 return 0;
2496 2389 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2497   - u.f = float64_mul(u.f, tmp, &env->spe_status);
  2390 + u.d = float64_mul(u.d, tmp, &env->spe_status);
2498 2391  
2499   - return float64_to_int32(u.f, &env->spe_status);
  2392 + return float64_to_int32(u.d, &env->spe_status);
2500 2393 }
2501 2394  
2502 2395 static always_inline uint64_t _do_efdctuf (uint64_t val)
2503 2396 {
2504   - union {
2505   - int64_t u;
2506   - float64 f;
2507   - } u;
  2397 + CPU_DoubleU u;
2508 2398 float64 tmp;
2509 2399  
2510   - u.u = val;
  2400 + u.ll = val;
2511 2401 /* NaN are not treated the same way IEEE 754 does */
2512   - if (unlikely(isnan(u.f)))
  2402 + if (unlikely(isnan(u.d)))
2513 2403 return 0;
2514 2404 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2515   - u.f = float64_mul(u.f, tmp, &env->spe_status);
  2405 + u.d = float64_mul(u.d, tmp, &env->spe_status);
2516 2406  
2517   - return float64_to_uint32(u.f, &env->spe_status);
  2407 + return float64_to_uint32(u.d, &env->spe_status);
2518 2408 }
2519 2409  
2520 2410 static always_inline int64_t _do_efdctsfz (uint64_t val)
2521 2411 {
2522   - union {
2523   - int64_t u;
2524   - float64 f;
2525   - } u;
  2412 + CPU_DoubleU u;
2526 2413 float64 tmp;
2527 2414  
2528   - u.u = val;
  2415 + u.ll = val;
2529 2416 /* NaN are not treated the same way IEEE 754 does */
2530   - if (unlikely(isnan(u.f)))
  2417 + if (unlikely(isnan(u.d)))
2531 2418 return 0;
2532 2419 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2533   - u.f = float64_mul(u.f, tmp, &env->spe_status);
  2420 + u.d = float64_mul(u.d, tmp, &env->spe_status);
2534 2421  
2535   - return float64_to_int32_round_to_zero(u.f, &env->spe_status);
  2422 + return float64_to_int32_round_to_zero(u.d, &env->spe_status);
2536 2423 }
2537 2424  
2538 2425 static always_inline uint64_t _do_efdctufz (uint64_t val)
2539 2426 {
2540   - union {
2541   - int64_t u;
2542   - float64 f;
2543   - } u;
  2427 + CPU_DoubleU u;
2544 2428 float64 tmp;
2545 2429  
2546   - u.u = val;
  2430 + u.ll = val;
2547 2431 /* NaN are not treated the same way IEEE 754 does */
2548   - if (unlikely(isnan(u.f)))
  2432 + if (unlikely(isnan(u.d)))
2549 2433 return 0;
2550 2434 tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
2551   - u.f = float64_mul(u.f, tmp, &env->spe_status);
  2435 + u.d = float64_mul(u.d, tmp, &env->spe_status);
2552 2436  
2553   - return float64_to_uint32_round_to_zero(u.f, &env->spe_status);
  2437 + return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
2554 2438 }
2555 2439  
2556 2440 void do_efdcfsf (void)
... ... @@ -2586,36 +2470,24 @@ void do_efdctufz (void)
2586 2470 /* Floating point conversion between single and double precision */
2587 2471 static always_inline uint32_t _do_efscfd (uint64_t val)
2588 2472 {
2589   - union {
2590   - uint64_t u;
2591   - float64 f;
2592   - } u1;
2593   - union {
2594   - uint32_t u;
2595   - float32 f;
2596   - } u2;
  2473 + CPU_DoubleU u1;
  2474 + CPU_FloatU u2;
2597 2475  
2598   - u1.u = val;
2599   - u2.f = float64_to_float32(u1.f, &env->spe_status);
  2476 + u1.ll = val;
  2477 + u2.f = float64_to_float32(u1.d, &env->spe_status);
2600 2478  
2601   - return u2.u;
  2479 + return u2.l;
2602 2480 }
2603 2481  
2604 2482 static always_inline uint64_t _do_efdcfs (uint32_t val)
2605 2483 {
2606   - union {
2607   - uint64_t u;
2608   - float64 f;
2609   - } u2;
2610   - union {
2611   - uint32_t u;
2612   - float32 f;
2613   - } u1;
  2484 + CPU_DoubleU u2;
  2485 + CPU_FloatU u1;
2614 2486  
2615   - u1.u = val;
2616   - u2.f = float32_to_float64(u1.f, &env->spe_status);
  2487 + u1.l = val;
  2488 + u2.d = float32_to_float64(u1.f, &env->spe_status);
2617 2489  
2618   - return u2.u;
  2490 + return u2.ll;
2619 2491 }
2620 2492  
2621 2493 void do_efscfd (void)
... ...
target-ppc/op_helper.h
  View file @0ca9d38
... ... @@ -296,108 +296,78 @@ static always_inline uint32_t _do_efsneg (uint32_t val)
296 296 }
297 297 static always_inline uint32_t _do_efsadd (uint32_t op1, uint32_t op2)
298 298 {
299   - union {
300   - uint32_t u;
301   - float32 f;
302   - } u1, u2;
303   - u1.u = op1;
304   - u2.u = op2;
  299 + CPU_FloatU u1, u2;
  300 + u1.l = op1;
  301 + u2.l = op2;
305 302 u1.f = float32_add(u1.f, u2.f, &env->spe_status);
306   - return u1.u;
  303 + return u1.l;
307 304 }
308 305 static always_inline uint32_t _do_efssub (uint32_t op1, uint32_t op2)
309 306 {
310   - union {
311   - uint32_t u;
312   - float32 f;
313   - } u1, u2;
314   - u1.u = op1;
315   - u2.u = op2;
  307 + CPU_FloatU u1, u2;
  308 + u1.l = op1;
  309 + u2.l = op2;
316 310 u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
317   - return u1.u;
  311 + return u1.l;
318 312 }
319 313 static always_inline uint32_t _do_efsmul (uint32_t op1, uint32_t op2)
320 314 {
321   - union {
322   - uint32_t u;
323   - float32 f;
324   - } u1, u2;
325   - u1.u = op1;
326   - u2.u = op2;
  315 + CPU_FloatU u1, u2;
  316 + u1.l = op1;
  317 + u2.l = op2;
327 318 u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
328   - return u1.u;
  319 + return u1.l;
329 320 }
330 321 static always_inline uint32_t _do_efsdiv (uint32_t op1, uint32_t op2)
331 322 {
332   - union {
333   - uint32_t u;
334   - float32 f;
335   - } u1, u2;
336   - u1.u = op1;
337   - u2.u = op2;
  323 + CPU_FloatU u1, u2;
  324 + u1.l = op1;
  325 + u2.l = op2;
338 326 u1.f = float32_div(u1.f, u2.f, &env->spe_status);
339   - return u1.u;
  327 + return u1.l;
340 328 }
341 329  
342 330 static always_inline int _do_efststlt (uint32_t op1, uint32_t op2)
343 331 {
344   - union {
345   - uint32_t u;
346   - float32 f;
347   - } u1, u2;
348   - u1.u = op1;
349   - u2.u = op2;
  332 + CPU_FloatU u1, u2;
  333 + u1.l = op1;
  334 + u2.l = op2;
350 335 return float32_lt(u1.f, u2.f, &env->spe_status) ? 1 : 0;
351 336 }
352 337 static always_inline int _do_efststgt (uint32_t op1, uint32_t op2)
353 338 {
354   - union {
355   - uint32_t u;
356   - float32 f;
357   - } u1, u2;
358   - u1.u = op1;
359   - u2.u = op2;
  339 + CPU_FloatU u1, u2;
  340 + u1.l = op1;
  341 + u2.l = op2;
360 342 return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 1;
361 343 }
362 344 static always_inline int _do_efststeq (uint32_t op1, uint32_t op2)
363 345 {
364   - union {
365   - uint32_t u;
366   - float32 f;
367   - } u1, u2;
368   - u1.u = op1;
369   - u2.u = op2;
  346 + CPU_FloatU u1, u2;
  347 + u1.l = op1;
  348 + u2.l = op2;
370 349 return float32_eq(u1.f, u2.f, &env->spe_status) ? 1 : 0;
371 350 }
372 351 /* Double precision floating-point helpers */
373 352 static always_inline int _do_efdtstlt (uint64_t op1, uint64_t op2)
374 353 {
375   - union {
376   - uint64_t u;
377   - float64 f;
378   - } u1, u2;
379   - u1.u = op1;
380   - u2.u = op2;
381   - return float64_lt(u1.f, u2.f, &env->spe_status) ? 1 : 0;
  354 + CPU_DoubleU u1, u2;
  355 + u1.ll = op1;
  356 + u2.ll = op2;
  357 + return float64_lt(u1.d, u2.d, &env->spe_status) ? 1 : 0;
382 358 }
383 359 static always_inline int _do_efdtstgt (uint64_t op1, uint64_t op2)
384 360 {
385   - union {
386   - uint64_t u;
387   - float64 f;
388   - } u1, u2;
389   - u1.u = op1;
390   - u2.u = op2;
391   - return float64_le(u1.f, u2.f, &env->spe_status) ? 0 : 1;
  361 + CPU_DoubleU u1, u2;
  362 + u1.ll = op1;
  363 + u2.ll = op2;
  364 + return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 1;
392 365 }
393 366 static always_inline int _do_efdtsteq (uint64_t op1, uint64_t op2)
394 367 {
395   - union {
396   - uint64_t u;
397   - float64 f;
398   - } u1, u2;
399   - u1.u = op1;
400   - u2.u = op2;
401   - return float64_eq(u1.f, u2.f, &env->spe_status) ? 1 : 0;
  368 + CPU_DoubleU u1, u2;
  369 + u1.ll = op1;
  370 + u2.ll = op2;
  371 + return float64_eq(u1.d, u2.d, &env->spe_status) ? 1 : 0;
402 372 }
403 373 #endif
... ...
target-ppc/op_helper_mem.h
  View file @0ca9d38
... ... @@ -316,15 +316,12 @@ void glue(do_POWER2_lfq, MEMSUFFIX) (void)
316 316 FT1 = glue(ldfq, MEMSUFFIX)((uint32_t)(T0 + 4));
317 317 }
318 318  
319   -static always_inline double glue(ldfqr, MEMSUFFIX) (target_ulong EA)
  319 +static always_inline float64 glue(ldfqr, MEMSUFFIX) (target_ulong EA)
320 320 {
321   - union {
322   - double d;
323   - uint64_t u;
324   - } u;
  321 + CPU_DoubleU u;
325 322  
326 323 u.d = glue(ldfq, MEMSUFFIX)(EA);
327   - u.u = bswap64(u.u);
  324 + u.ll = bswap64(u.ll);
328 325  
329 326 return u.d;
330 327 }
... ... @@ -341,15 +338,12 @@ void glue(do_POWER2_stfq, MEMSUFFIX) (void)
341 338 glue(stfq, MEMSUFFIX)((uint32_t)(T0 + 4), FT1);
342 339 }
343 340  
344   -static always_inline void glue(stfqr, MEMSUFFIX) (target_ulong EA, double d)
  341 +static always_inline void glue(stfqr, MEMSUFFIX) (target_ulong EA, float64 d)
345 342 {
346   - union {
347   - double d;
348   - uint64_t u;
349   - } u;
  343 + CPU_DoubleU u;
350 344  
351 345 u.d = d;
352   - u.u = bswap64(u.u);
  346 + u.ll = bswap64(u.ll);
353 347 glue(stfq, MEMSUFFIX)(EA, u.d);
354 348 }
355 349  
... ...
target-ppc/op_mem.h
  View file @0ca9d38
... ... @@ -267,31 +267,19 @@ void OPPROTO glue(glue(glue(op_st, name), _64), MEMSUFFIX) (void) \
267 267 }
268 268 #endif
269 269  
270   -static always_inline void glue(stfs, MEMSUFFIX) (target_ulong EA, double d)
  270 +static always_inline void glue(stfs, MEMSUFFIX) (target_ulong EA, float64 d)
271 271 {
272 272 glue(stfl, MEMSUFFIX)(EA, float64_to_float32(d, &env->fp_status));
273 273 }
274 274  
275   -#if defined(WORDS_BIGENDIAN)
276   -#define WORD0 0
277   -#define WORD1 1
278   -#else
279   -#define WORD0 1
280   -#define WORD1 0
281   -#endif
282   -static always_inline void glue(stfiw, MEMSUFFIX) (target_ulong EA, double d)
  275 +static always_inline void glue(stfiw, MEMSUFFIX) (target_ulong EA, float64 d)
283 276 {
284   - union {
285   - double d;
286   - uint32_t u[2];
287   - } u;
  277 + CPU_DoubleU u;
288 278  
289 279 /* Store the low order 32 bits without any conversion */
290 280 u.d = d;
291   - glue(st32, MEMSUFFIX)(EA, u.u[WORD0]);
  281 + glue(st32, MEMSUFFIX)(EA, u.l.lower);
292 282 }
293   -#undef WORD0
294   -#undef WORD1
295 283  
296 284 PPC_STF_OP(fd, stfq);
297 285 PPC_STF_OP(fs, stfs);
... ... @@ -302,41 +290,32 @@ PPC_STF_OP_64(fs, stfs);
302 290 PPC_STF_OP_64(fiw, stfiw);
303 291 #endif
304 292  
305   -static always_inline void glue(stfqr, MEMSUFFIX) (target_ulong EA, double d)
  293 +static always_inline void glue(stfqr, MEMSUFFIX) (target_ulong EA, float64 d)
306 294 {
307   - union {
308   - double d;
309   - uint64_t u;
310   - } u;
  295 + CPU_DoubleU u;
311 296  
312 297 u.d = d;
313   - u.u = bswap64(u.u);
  298 + u.ll = bswap64(u.ll);
314 299 glue(stfq, MEMSUFFIX)(EA, u.d);
315 300 }
316 301  
317   -static always_inline void glue(stfsr, MEMSUFFIX) (target_ulong EA, double d)
  302 +static always_inline void glue(stfsr, MEMSUFFIX) (target_ulong EA, float64 d)
318 303 {
319   - union {
320   - float f;
321   - uint32_t u;
322   - } u;
  304 + CPU_FloatU u;
323 305  
324 306 u.f = float64_to_float32(d, &env->fp_status);
325   - u.u = bswap32(u.u);
  307 + u.l = bswap32(u.l);
326 308 glue(stfl, MEMSUFFIX)(EA, u.f);
327 309 }
328 310  
329   -static always_inline void glue(stfiwr, MEMSUFFIX) (target_ulong EA, double d)
  311 +static always_inline void glue(stfiwr, MEMSUFFIX) (target_ulong EA, float64 d)
330 312 {
331   - union {
332   - double d;
333   - uint64_t u;
334   - } u;
  313 + CPU_DoubleU u;
335 314  
336 315 /* Store the low order 32 bits without any conversion */
337 316 u.d = d;
338   - u.u = bswap32(u.u);
339   - glue(st32, MEMSUFFIX)(EA, u.u);
  317 + u.l.lower = bswap32(u.l.lower);
  318 + glue(st32, MEMSUFFIX)(EA, u.l.lower);
340 319 }
341 320  
342 321 PPC_STF_OP(fd_le, stfqr);
... ... @@ -365,7 +344,7 @@ void OPPROTO glue(glue(glue(op_l, name), _64), MEMSUFFIX) (void) \
365 344 }
366 345 #endif
367 346  
368   -static always_inline double glue(ldfs, MEMSUFFIX) (target_ulong EA)
  347 +static always_inline float64 glue(ldfs, MEMSUFFIX) (target_ulong EA)
369 348 {
370 349 return float32_to_float64(glue(ldfl, MEMSUFFIX)(EA), &env->fp_status);
371 350 }
... ... @@ -377,28 +356,22 @@ PPC_LDF_OP_64(fd, ldfq);
377 356 PPC_LDF_OP_64(fs, ldfs);
378 357 #endif
379 358  
380   -static always_inline double glue(ldfqr, MEMSUFFIX) (target_ulong EA)
  359 +static always_inline float64 glue(ldfqr, MEMSUFFIX) (target_ulong EA)
381 360 {
382   - union {
383   - double d;
384   - uint64_t u;
385   - } u;
  361 + CPU_DoubleU u;
386 362  
387 363 u.d = glue(ldfq, MEMSUFFIX)(EA);
388   - u.u = bswap64(u.u);
  364 + u.ll = bswap64(u.ll);
389 365  
390 366 return u.d;
391 367 }
392 368  
393   -static always_inline double glue(ldfsr, MEMSUFFIX) (target_ulong EA)
  369 +static always_inline float64 glue(ldfsr, MEMSUFFIX) (target_ulong EA)
394 370 {
395   - union {
396   - float f;
397   - uint32_t u;
398   - } u;
  371 + CPU_FloatU u;
399 372  
400 373 u.f = glue(ldfl, MEMSUFFIX)(EA);
401   - u.u = bswap32(u.u);
  374 + u.l = bswap32(u.l);
402 375  
403 376 return float32_to_float64(u.f, &env->fp_status);
404 377 }
... ...