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#ifndef SUN4M_H
#define SUN4M_H
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#include "qemu-common.h"
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/* Devices used by sparc32 system. */
/* iommu.c */
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void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq);
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void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
uint8_t *buf, int len, int is_write);
static inline void sparc_iommu_memory_read(void *opaque,
target_phys_addr_t addr,
uint8_t *buf, int len)
{
sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
}
static inline void sparc_iommu_memory_write(void *opaque,
target_phys_addr_t addr,
uint8_t *buf, int len)
{
sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
}
/* tcx.c */
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void tcx_init(target_phys_addr_t addr, int vram_size, int width, int height,
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int depth);
/* slavio_intctl.c */
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DeviceState *slavio_intctl_init(target_phys_addr_t addr,
target_phys_addr_t addrg,
const uint32_t *intbit_to_level,
qemu_irq **parent_irq, unsigned int cputimer);
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void slavio_pic_info(Monitor *mon, void *opaque);
void slavio_irq_info(Monitor *mon, void *opaque);
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/* sbi.c */
void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
qemu_irq **parent_irq);
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/* sun4c_intctl.c */
void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,
qemu_irq *parent_irq);
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void sun4c_pic_info(Monitor *mon, void *opaque);
void sun4c_irq_info(Monitor *mon, void *opaque);
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/* slavio_timer.c */
void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
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qemu_irq *cpu_irqs, unsigned int num_cpus);
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/* slavio_misc.c */
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void *slavio_misc_init(target_phys_addr_t base,
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target_phys_addr_t aux1_base,
target_phys_addr_t aux2_base, qemu_irq irq,
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qemu_irq fdc_tc);
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void slavio_set_power_fail(void *opaque, int power_failing);
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void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt);
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/* sparc32_dma.c */
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#include "sparc32_dma.h"
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/* eccmemctl.c */
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void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version);
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#endif
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