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/*
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* QEMU ESCC ( Z8030 / Z8530 / Z85C30 / SCC / ESCC ) serial port emulation
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*
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* Copyright ( c ) 2003 - 2005 Fabrice Bellard
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*
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* Permission is hereby granted , free of charge , to any person obtaining a copy
* of this software and associated documentation files ( the "Software" ), to deal
* in the Software without restriction , including without limitation the rights
* to use , copy , modify , merge , publish , distribute , sublicense , and / or sell
* copies of the Software , and to permit persons to whom the Software is
* furnished to do so , subject to the following conditions :
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software .
*
* THE SOFTWARE IS PROVIDED "AS IS" , WITHOUT WARRANTY OF ANY KIND , EXPRESS OR
* IMPLIED , INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY ,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT . IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM , DAMAGES OR OTHER
* LIABILITY , WHETHER IN AN ACTION OF CONTRACT , TORT OR OTHERWISE , ARISING FROM ,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE .
*/
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# include "hw.h"
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# include "sysbus.h"
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# include "escc.h"
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# include "qemu-char.h"
# include "console.h"
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/* debug serial */
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// # define DEBUG_SERIAL
/* debug keyboard */
// # define DEBUG_KBD
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/* debug mouse */
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// # define DEBUG_MOUSE
/*
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* On Sparc32 this is the serial port , mouse and keyboard part of chip STP2001
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* ( Slave I / O ), also produced as NCR89C105 . See
* http :// www . ibiblio . org / pub / historic - linux / early - ports / Sparc / NCR / NCR89C105 . txt
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*
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* The serial ports implement full AMD AM8530 or Zilog Z8530 chips ,
* mouse and keyboard ports don ' t implement all functions and they are
* only asynchronous . There is no DMA .
*
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* Z85C30 is also used on PowerMacs . There are some small differences
* between Sparc version ( sunzilog ) and PowerMac ( pmac ) :
* Offset between control and data registers
* There is some kind of lockup bug , but we can ignore it
* CTS is inverted
* DMA on pmac using DBDMA chip
* pmac can do IRDA and faster rates , sunzilog can only do 38400
* pmac baud rate generator clock is 3 . 6864 MHz , sunzilog 4 . 9152 MHz
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*/
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/*
* Modifications :
* 2006 - Aug - 10 Igor Kovalenko : Renamed KBDQueue to SERIOQueue , implemented
* serial mouse queue .
* Implemented serial mouse protocol .
*/
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# ifdef DEBUG_SERIAL
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# define SER_DPRINTF ( fmt , ...) \
do { printf ( "SER: " fmt , ## __VA_ARGS__ ); } while ( 0 )
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# else
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# define SER_DPRINTF ( fmt , ...)
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# endif
# ifdef DEBUG_KBD
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# define KBD_DPRINTF ( fmt , ...) \
do { printf ( "KBD: " fmt , ## __VA_ARGS__ ); } while ( 0 )
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# else
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# define KBD_DPRINTF ( fmt , ...)
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# endif
# ifdef DEBUG_MOUSE
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# define MS_DPRINTF ( fmt , ...) \
do { printf ( "MSC: " fmt , ## __VA_ARGS__ ); } while ( 0 )
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# else
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# define MS_DPRINTF ( fmt , ...)
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# endif
typedef enum {
chn_a , chn_b ,
} chn_id_t ;
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# define CHN_C ( s ) (( s ) -> chn == chn_b ? 'b' : 'a' )
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typedef enum {
ser , kbd , mouse ,
} chn_type_t ;
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# define SERIO_QUEUE_SIZE 256
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typedef struct {
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uint8_t data [ SERIO_QUEUE_SIZE ];
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int rptr , wptr , count ;
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} SERIOQueue ;
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# define SERIAL_REGS 16
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typedef struct ChannelState {
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qemu_irq irq ;
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uint32_t reg ;
uint32_t rxint , txint , rxint_under_svc , txint_under_svc ;
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chn_id_t chn ; // this channel , A ( base + 4 ) or B ( base + 0 )
chn_type_t type ;
struct ChannelState * otherchn ;
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uint8_t rx , tx , wregs [ SERIAL_REGS ], rregs [ SERIAL_REGS ];
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SERIOQueue queue ;
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CharDriverState * chr ;
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int e0_mode , led_mode , caps_lock_mode , num_lock_mode ;
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int disabled ;
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int clock ;
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} ChannelState ;
struct SerialState {
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SysBusDevice busdev ;
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struct ChannelState chn [ 2 ];
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int it_shift ;
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int mmio_index ;
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uint32_t disabled ;
uint32_t frequency ;
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};
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# define SERIAL_CTRL 0
# define SERIAL_DATA 1
# define W_CMD 0
# define CMD_PTR_MASK 0x07
# define CMD_CMD_MASK 0x38
# define CMD_HI 0x08
# define CMD_CLR_TXINT 0x28
# define CMD_CLR_IUS 0x38
# define W_INTR 1
# define INTR_INTALL 0x01
# define INTR_TXINT 0x02
# define INTR_RXMODEMSK 0x18
# define INTR_RXINT1ST 0x08
# define INTR_RXINTALL 0x10
# define W_IVEC 2
# define W_RXCTRL 3
# define RXCTRL_RXEN 0x01
# define W_TXCTRL1 4
# define TXCTRL1_PAREN 0x01
# define TXCTRL1_PAREV 0x02
# define TXCTRL1_1STOP 0x04
# define TXCTRL1_1HSTOP 0x08
# define TXCTRL1_2STOP 0x0c
# define TXCTRL1_STPMSK 0x0c
# define TXCTRL1_CLK1X 0x00
# define TXCTRL1_CLK16X 0x40
# define TXCTRL1_CLK32X 0x80
# define TXCTRL1_CLK64X 0xc0
# define TXCTRL1_CLKMSK 0xc0
# define W_TXCTRL2 5
# define TXCTRL2_TXEN 0x08
# define TXCTRL2_BITMSK 0x60
# define TXCTRL2_5BITS 0x00
# define TXCTRL2_7BITS 0x20
# define TXCTRL2_6BITS 0x40
# define TXCTRL2_8BITS 0x60
# define W_SYNC1 6
# define W_SYNC2 7
# define W_TXBUF 8
# define W_MINTR 9
# define MINTR_STATUSHI 0x10
# define MINTR_RST_MASK 0xc0
# define MINTR_RST_B 0x40
# define MINTR_RST_A 0x80
# define MINTR_RST_ALL 0xc0
# define W_MISC1 10
# define W_CLOCK 11
# define CLOCK_TRXC 0x08
# define W_BRGLO 12
# define W_BRGHI 13
# define W_MISC2 14
# define MISC2_PLLDIS 0x30
# define W_EXTINT 15
# define EXTINT_DCD 0x08
# define EXTINT_SYNCINT 0x10
# define EXTINT_CTSINT 0x20
# define EXTINT_TXUNDRN 0x40
# define EXTINT_BRKINT 0x80
# define R_STATUS 0
# define STATUS_RXAV 0x01
# define STATUS_ZERO 0x02
# define STATUS_TXEMPTY 0x04
# define STATUS_DCD 0x08
# define STATUS_SYNC 0x10
# define STATUS_CTS 0x20
# define STATUS_TXUNDRN 0x40
# define STATUS_BRK 0x80
# define R_SPEC 1
# define SPEC_ALLSENT 0x01
# define SPEC_BITS8 0x06
# define R_IVEC 2
# define IVEC_TXINTB 0x00
# define IVEC_LONOINT 0x06
# define IVEC_LORXINTA 0x0c
# define IVEC_LORXINTB 0x04
# define IVEC_LOTXINTA 0x08
# define IVEC_HINOINT 0x60
# define IVEC_HIRXINTA 0x30
# define IVEC_HIRXINTB 0x20
# define IVEC_HITXINTA 0x10
# define R_INTR 3
# define INTR_EXTINTB 0x01
# define INTR_TXINTB 0x02
# define INTR_RXINTB 0x04
# define INTR_EXTINTA 0x08
# define INTR_TXINTA 0x10
# define INTR_RXINTA 0x20
# define R_IPEN 4
# define R_TXCTRL1 5
# define R_TXCTRL2 6
# define R_BC 7
# define R_RXBUF 8
# define R_RXCTRL 9
# define R_MISC 10
# define R_MISC1 11
# define R_BRGLO 12
# define R_BRGHI 13
# define R_MISC1I 14
# define R_EXTINT 15
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static void handle_kbd_command ( ChannelState * s , int val );
static int serial_can_receive ( void * opaque );
static void serial_receive_byte ( ChannelState * s , int ch );
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static void clear_queue ( void * opaque )
{
ChannelState * s = opaque ;
SERIOQueue * q = & s -> queue ;
q -> rptr = q -> wptr = q -> count = 0 ;
}
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static void put_queue ( void * opaque , int b )
{
ChannelState * s = opaque ;
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SERIOQueue * q = & s -> queue ;
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SER_DPRINTF ( "channel %c put: 0x%02x \n " , CHN_C ( s ), b );
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if ( q -> count >= SERIO_QUEUE_SIZE )
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return ;
q -> data [ q -> wptr ] = b ;
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if ( ++ q -> wptr == SERIO_QUEUE_SIZE )
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q -> wptr = 0 ;
q -> count ++ ;
serial_receive_byte ( s , 0 );
}
static uint32_t get_queue ( void * opaque )
{
ChannelState * s = opaque ;
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SERIOQueue * q = & s -> queue ;
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int val ;
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if ( q -> count == 0 ) {
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return 0 ;
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} else {
val = q -> data [ q -> rptr ];
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if ( ++ q -> rptr == SERIO_QUEUE_SIZE )
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q -> rptr = 0 ;
q -> count -- ;
}
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SER_DPRINTF ( "channel %c get 0x%02x \n " , CHN_C ( s ), val );
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if ( q -> count > 0 )
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serial_receive_byte ( s , 0 );
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return val ;
}
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static int escc_update_irq_chn ( ChannelState * s )
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{
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if (((( s -> wregs [ W_INTR ] & INTR_TXINT ) && s -> txint == 1 ) ||
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// tx ints enabled , pending
(((( s -> wregs [ W_INTR ] & INTR_RXMODEMSK ) == INTR_RXINT1ST ) ||
(( s -> wregs [ W_INTR ] & INTR_RXMODEMSK ) == INTR_RXINTALL )) &&
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s -> rxint == 1 ) || // rx ints enabled , pending
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(( s -> wregs [ W_EXTINT ] & EXTINT_BRKINT ) &&
( s -> rregs [ R_STATUS ] & STATUS_BRK )))) { // break int e & p
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return 1 ;
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}
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return 0 ;
}
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static void escc_update_irq ( ChannelState * s )
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{
int irq ;
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irq = escc_update_irq_chn ( s );
irq |= escc_update_irq_chn ( s -> otherchn );
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SER_DPRINTF ( "IRQ = %d \n " , irq );
qemu_set_irq ( s -> irq , irq );
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}
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static void escc_reset_chn ( ChannelState * s )
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{
int i ;
s -> reg = 0 ;
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for ( i = 0 ; i < SERIAL_REGS ; i ++ ) {
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s -> rregs [ i ] = 0 ;
s -> wregs [ i ] = 0 ;
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}
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s -> wregs [ W_TXCTRL1 ] = TXCTRL1_1STOP ; // 1 X divisor , 1 stop bit , no parity
s -> wregs [ W_MINTR ] = MINTR_RST_ALL ;
s -> wregs [ W_CLOCK ] = CLOCK_TRXC ; // Synch mode tx clock = TRxC
s -> wregs [ W_MISC2 ] = MISC2_PLLDIS ; // PLL disabled
s -> wregs [ W_EXTINT ] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT |
EXTINT_TXUNDRN | EXTINT_BRKINT ; // Enable most interrupts
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if ( s -> disabled )
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s -> rregs [ R_STATUS ] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC |
STATUS_CTS | STATUS_TXUNDRN ;
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else
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s -> rregs [ R_STATUS ] = STATUS_TXEMPTY | STATUS_TXUNDRN ;
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s -> rregs [ R_SPEC ] = SPEC_BITS8 | SPEC_ALLSENT ;
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s -> rx = s -> tx = 0 ;
s -> rxint = s -> txint = 0 ;
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s -> rxint_under_svc = s -> txint_under_svc = 0 ;
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s -> e0_mode = s -> led_mode = s -> caps_lock_mode = s -> num_lock_mode = 0 ;
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clear_queue ( s );
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}
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static void escc_reset ( void * opaque )
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{
SerialState * s = opaque ;
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escc_reset_chn ( & s -> chn [ 0 ]);
escc_reset_chn ( & s -> chn [ 1 ]);
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}
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static inline void set_rxint ( ChannelState * s )
{
s -> rxint = 1 ;
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if ( ! s -> txint_under_svc ) {
s -> rxint_under_svc = 1 ;
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if ( s -> chn == chn_a ) {
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if ( s -> wregs [ W_MINTR ] & MINTR_STATUSHI )
s -> otherchn -> rregs [ R_IVEC ] = IVEC_HIRXINTA ;
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else
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s -> otherchn -> rregs [ R_IVEC ] = IVEC_LORXINTA ;
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} else {
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if ( s -> wregs [ W_MINTR ] & MINTR_STATUSHI )
s -> rregs [ R_IVEC ] = IVEC_HIRXINTB ;
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else
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s -> rregs [ R_IVEC ] = IVEC_LORXINTB ;
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}
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}
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if ( s -> chn == chn_a )
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s -> rregs [ R_INTR ] |= INTR_RXINTA ;
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else
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s -> otherchn -> rregs [ R_INTR ] |= INTR_RXINTB ;
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escc_update_irq ( s );
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}
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static inline void set_txint ( ChannelState * s )
{
s -> txint = 1 ;
if ( ! s -> rxint_under_svc ) {
s -> txint_under_svc = 1 ;
if ( s -> chn == chn_a ) {
if ( s -> wregs [ W_MINTR ] & MINTR_STATUSHI )
s -> otherchn -> rregs [ R_IVEC ] = IVEC_HITXINTA ;
else
s -> otherchn -> rregs [ R_IVEC ] = IVEC_LOTXINTA ;
} else {
s -> rregs [ R_IVEC ] = IVEC_TXINTB ;
}
}
if ( s -> chn == chn_a )
s -> rregs [ R_INTR ] |= INTR_TXINTA ;
else
s -> otherchn -> rregs [ R_INTR ] |= INTR_TXINTB ;
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escc_update_irq ( s );
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}
static inline void clr_rxint ( ChannelState * s )
{
s -> rxint = 0 ;
s -> rxint_under_svc = 0 ;
if ( s -> chn == chn_a ) {
if ( s -> wregs [ W_MINTR ] & MINTR_STATUSHI )
s -> otherchn -> rregs [ R_IVEC ] = IVEC_HINOINT ;
else
s -> otherchn -> rregs [ R_IVEC ] = IVEC_LONOINT ;
s -> rregs [ R_INTR ] &= ~ INTR_RXINTA ;
} else {
if ( s -> wregs [ W_MINTR ] & MINTR_STATUSHI )
s -> rregs [ R_IVEC ] = IVEC_HINOINT ;
else
s -> rregs [ R_IVEC ] = IVEC_LONOINT ;
s -> otherchn -> rregs [ R_INTR ] &= ~ INTR_RXINTB ;
}
if ( s -> txint )
set_txint ( s );
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escc_update_irq ( s );
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}
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static inline void clr_txint ( ChannelState * s )
{
s -> txint = 0 ;
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s -> txint_under_svc = 0 ;
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if ( s -> chn == chn_a ) {
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if ( s -> wregs [ W_MINTR ] & MINTR_STATUSHI )
s -> otherchn -> rregs [ R_IVEC ] = IVEC_HINOINT ;
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else
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s -> otherchn -> rregs [ R_IVEC ] = IVEC_LONOINT ;
s -> rregs [ R_INTR ] &= ~ INTR_TXINTA ;
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} else {
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if ( s -> wregs [ W_MINTR ] & MINTR_STATUSHI )
s -> rregs [ R_IVEC ] = IVEC_HINOINT ;
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else
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s -> rregs [ R_IVEC ] = IVEC_LONOINT ;
s -> otherchn -> rregs [ R_INTR ] &= ~ INTR_TXINTB ;
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}
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if ( s -> rxint )
set_rxint ( s );
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escc_update_irq ( s );
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}
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static void escc_update_parameters ( ChannelState * s )
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{
int speed , parity , data_bits , stop_bits ;
QEMUSerialSetParams ssp ;
if ( ! s -> chr || s -> type != ser )
return ;
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if ( s -> wregs [ W_TXCTRL1 ] & TXCTRL1_PAREN ) {
if ( s -> wregs [ W_TXCTRL1 ] & TXCTRL1_PAREV )
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parity = 'E' ;
else
parity = 'O' ;
} else {
parity = 'N' ;
}
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if (( s -> wregs [ W_TXCTRL1 ] & TXCTRL1_STPMSK ) == TXCTRL1_2STOP )
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stop_bits = 2 ;
else
stop_bits = 1 ;
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switch ( s -> wregs [ W_TXCTRL2 ] & TXCTRL2_BITMSK ) {
case TXCTRL2_5BITS :
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data_bits = 5 ;
break ;
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case TXCTRL2_7BITS :
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data_bits = 7 ;
break ;
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case TXCTRL2_6BITS :
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data_bits = 6 ;
break ;
default :
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case TXCTRL2_8BITS :
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data_bits = 8 ;
break ;
}
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speed = s -> clock / (( s -> wregs [ W_BRGLO ] | ( s -> wregs [ W_BRGHI ] << 8 )) + 2 );
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switch ( s -> wregs [ W_TXCTRL1 ] & TXCTRL1_CLKMSK ) {
case TXCTRL1_CLK1X :
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break ;
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case TXCTRL1_CLK16X :
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speed /= 16 ;
break ;
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case TXCTRL1_CLK32X :
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speed /= 32 ;
break ;
default :
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case TXCTRL1_CLK64X :
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speed /= 64 ;
break ;
}
ssp . speed = speed ;
ssp . parity = parity ;
ssp . data_bits = data_bits ;
ssp . stop_bits = stop_bits ;
SER_DPRINTF ( "channel %c: speed=%d parity=%c data=%d stop=%d \n " , CHN_C ( s ),
speed , parity , data_bits , stop_bits );
qemu_chr_ioctl ( s -> chr , CHR_IOCTL_SERIAL_SET_PARAMS , & ssp );
}
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static void escc_mem_writeb ( void * opaque , target_phys_addr_t addr , uint32_t val )
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{
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SerialState * serial = opaque ;
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ChannelState * s ;
uint32_t saddr ;
int newreg , channel ;
val &= 0xff ;
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saddr = ( addr >> serial -> it_shift ) & 1 ;
channel = ( addr >> ( serial -> it_shift + 1 )) & 1 ;
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s = & serial -> chn [ channel ];
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switch ( saddr ) {
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case SERIAL_CTRL :
SER_DPRINTF ( "Write channel %c, reg[%d] = %2.2x \n " , CHN_C ( s ), s -> reg ,
val & 0xff );
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newreg = 0 ;
switch ( s -> reg ) {
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case W_CMD :
newreg = val & CMD_PTR_MASK ;
val &= CMD_CMD_MASK ;
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switch ( val ) {
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case CMD_HI :
newreg |= CMD_HI ;
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break ;
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case CMD_CLR_TXINT :
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clr_txint ( s );
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break ;
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case CMD_CLR_IUS :
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if ( s -> rxint_under_svc )
clr_rxint ( s );
else if ( s -> txint_under_svc )
clr_txint ( s );
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break ;
default :
break ;
}
break ;
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case W_INTR ... W_RXCTRL :
case W_SYNC1 ... W_TXBUF :
case W_MISC1 ... W_CLOCK :
case W_MISC2 ... W_EXTINT :
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s -> wregs [ s -> reg ] = val ;
break ;
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case W_TXCTRL1 :
case W_TXCTRL2 :
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s -> wregs [ s -> reg ] = val ;
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escc_update_parameters ( s );
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break ;
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case W_BRGLO :
case W_BRGHI :
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s -> wregs [ s -> reg ] = val ;
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s -> rregs [ s -> reg ] = val ;
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escc_update_parameters ( s );
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break ;
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case W_MINTR :
switch ( val & MINTR_RST_MASK ) {
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case 0 :
default :
break ;
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case MINTR_RST_B :
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escc_reset_chn ( & serial -> chn [ 0 ]);
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return ;
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case MINTR_RST_A :
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escc_reset_chn ( & serial -> chn [ 1 ]);
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return ;
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case MINTR_RST_ALL :
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escc_reset ( serial );
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return ;
}
break ;
default :
break ;
}
if ( s -> reg == 0 )
s -> reg = newreg ;
else
s -> reg = 0 ;
break ;
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case SERIAL_DATA :
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SER_DPRINTF ( "Write channel %c, ch %d \n " , CHN_C ( s ), val );
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s -> tx = val ;
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if ( s -> wregs [ W_TXCTRL2 ] & TXCTRL2_TXEN ) { // tx enabled
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if ( s -> chr )
qemu_chr_write ( s -> chr , & s -> tx , 1 );
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else if ( s -> type == kbd && ! s -> disabled ) {
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handle_kbd_command ( s , val );
}
}
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s -> rregs [ R_STATUS ] |= STATUS_TXEMPTY ; // Tx buffer empty
s -> rregs [ R_SPEC ] |= SPEC_ALLSENT ; // All sent
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set_txint ( s );
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break ;
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default :
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break ;
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}
}
581
static uint32_t escc_mem_readb ( void * opaque , target_phys_addr_t addr )
582
{
583
SerialState * serial = opaque ;
584
585
586
587
588
ChannelState * s ;
uint32_t saddr ;
uint32_t ret ;
int channel ;
589
590
saddr = ( addr >> serial -> it_shift ) & 1 ;
channel = ( addr >> ( serial -> it_shift + 1 )) & 1 ;
591
s = & serial -> chn [ channel ];
592
switch ( saddr ) {
593
594
595
case SERIAL_CTRL :
SER_DPRINTF ( "Read channel %c, reg[%d] = %2.2x \n " , CHN_C ( s ), s -> reg ,
s -> rregs [ s -> reg ]);
596
597
598
ret = s -> rregs [ s -> reg ];
s -> reg = 0 ;
return ret ;
599
600
case SERIAL_DATA :
s -> rregs [ R_STATUS ] &= ~ STATUS_RXAV ;
601
clr_rxint ( s );
602
603
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605
606
if ( s -> type == kbd || s -> type == mouse )
ret = get_queue ( s );
else
ret = s -> rx ;
SER_DPRINTF ( "Read channel %c, ch %d \n " , CHN_C ( s ), ret );
607
608
if ( s -> chr )
qemu_chr_accept_input ( s -> chr );
609
return ret ;
610
default :
611
break ;
612
613
614
615
616
617
618
}
return 0 ;
}
static int serial_can_receive ( void * opaque )
{
ChannelState * s = opaque ;
619
620
int ret ;
621
622
623
if ((( s -> wregs [ W_RXCTRL ] & RXCTRL_RXEN ) == 0 ) // Rx not enabled
|| (( s -> rregs [ R_STATUS ] & STATUS_RXAV ) == STATUS_RXAV ))
// char already available
624
ret = 0 ;
625
else
626
ret = 1 ;
627
return ret ;
628
629
630
631
}
static void serial_receive_byte ( ChannelState * s , int ch )
{
632
SER_DPRINTF ( "channel %c put ch %d \n " , CHN_C ( s ), ch );
633
s -> rregs [ R_STATUS ] |= STATUS_RXAV ;
634
s -> rx = ch ;
635
set_rxint ( s );
636
637
638
639
}
static void serial_receive_break ( ChannelState * s )
{
640
s -> rregs [ R_STATUS ] |= STATUS_BRK ;
641
escc_update_irq ( s );
642
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645
646
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648
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650
651
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654
655
656
}
static void serial_receive1 ( void * opaque , const uint8_t * buf , int size )
{
ChannelState * s = opaque ;
serial_receive_byte ( s , buf [ 0 ]);
}
static void serial_event ( void * opaque , int event )
{
ChannelState * s = opaque ;
if ( event == CHR_EVENT_BREAK )
serial_receive_break ( s );
}
657
658
static CPUReadMemoryFunc * escc_mem_read [ 3 ] = {
escc_mem_readb ,
659
660
NULL ,
NULL ,
661
662
};
663
664
static CPUWriteMemoryFunc * escc_mem_write [ 3 ] = {
escc_mem_writeb ,
665
666
NULL ,
NULL ,
667
668
};
669
static void escc_save_chn ( QEMUFile * f , ChannelState * s )
670
{
671
672
uint32_t tmp = 0 ;
673
qemu_put_be32s ( f , & tmp ); /* unused, was IRQ. */
674
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qemu_put_be32s ( f , & s -> reg );
qemu_put_be32s ( f , & s -> rxint );
qemu_put_be32s ( f , & s -> txint );
677
678
qemu_put_be32s ( f , & s -> rxint_under_svc );
qemu_put_be32s ( f , & s -> txint_under_svc );
679
680
qemu_put_8s ( f , & s -> rx );
qemu_put_8s ( f , & s -> tx );
681
682
qemu_put_buffer ( f , s -> wregs , SERIAL_REGS );
qemu_put_buffer ( f , s -> rregs , SERIAL_REGS );
683
684
}
685
static void escc_save ( QEMUFile * f , void * opaque )
686
687
688
{
SerialState * s = opaque ;
689
690
escc_save_chn ( f , & s -> chn [ 0 ]);
escc_save_chn ( f , & s -> chn [ 1 ]);
691
692
}
693
static int escc_load_chn ( QEMUFile * f , ChannelState * s , int version_id )
694
{
695
uint32_t tmp ;
696
697
if ( version_id > 2 )
698
699
return - EINVAL ;
700
qemu_get_be32s ( f , & tmp ); /* unused */
701
702
703
qemu_get_be32s ( f , & s -> reg );
qemu_get_be32s ( f , & s -> rxint );
qemu_get_be32s ( f , & s -> txint );
704
705
706
707
if ( version_id >= 2 ) {
qemu_get_be32s ( f , & s -> rxint_under_svc );
qemu_get_be32s ( f , & s -> txint_under_svc );
}
708
709
qemu_get_8s ( f , & s -> rx );
qemu_get_8s ( f , & s -> tx );
710
711
qemu_get_buffer ( f , s -> wregs , SERIAL_REGS );
qemu_get_buffer ( f , s -> rregs , SERIAL_REGS );
712
713
714
return 0 ;
}
715
static int escc_load ( QEMUFile * f , void * opaque , int version_id )
716
717
718
719
{
SerialState * s = opaque ;
int ret ;
720
ret = escc_load_chn ( f , & s -> chn [ 0 ], version_id );
721
if ( ret != 0 )
722
return ret ;
723
ret = escc_load_chn ( f , & s -> chn [ 1 ], version_id );
724
725
726
727
return ret ;
}
728
729
730
int escc_init ( target_phys_addr_t base , qemu_irq irqA , qemu_irq irqB ,
CharDriverState * chrA , CharDriverState * chrB ,
int clock , int it_shift )
731
{
732
733
734
735
736
DeviceState * dev ;
SysBusDevice * s ;
SerialState * d ;
dev = qdev_create ( NULL , "escc" );
737
738
739
740
741
742
743
qdev_prop_set_uint32 ( dev , "disabled" , 0 );
qdev_prop_set_uint32 ( dev , "frequency" , clock );
qdev_prop_set_uint32 ( dev , "it_shift" , it_shift );
qdev_prop_set_ptr ( dev , "chrB" , chrB );
qdev_prop_set_ptr ( dev , "chrA" , chrA );
qdev_prop_set_uint32 ( dev , "chnBtype" , ser );
qdev_prop_set_uint32 ( dev , "chnAtype" , ser );
744
745
746
747
748
749
qdev_init ( dev );
s = sysbus_from_qdev ( dev );
sysbus_connect_irq ( s , 0 , irqA );
sysbus_connect_irq ( s , 1 , irqB );
if ( base ) {
sysbus_mmio_map ( s , 0 , base );
750
}
751
752
753
d = FROM_SYSBUS ( SerialState , s );
return d -> mmio_index ;
754
755
}
756
757
758
759
760
761
762
763
764
765
766
static const uint8_t keycodes [ 128 ] = {
127 , 29 , 30 , 31 , 32 , 33 , 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 , 43 , 53 ,
54 , 55 , 56 , 57 , 58 , 59 , 60 , 61 , 62 , 63 , 64 , 65 , 89 , 76 , 77 , 78 ,
79 , 80 , 81 , 82 , 83 , 84 , 85 , 86 , 87 , 42 , 99 , 88 , 100 , 101 , 102 , 103 ,
104 , 105 , 106 , 107 , 108 , 109 , 110 , 47 , 19 , 121 , 119 , 5 , 6 , 8 , 10 , 12 ,
14 , 16 , 17 , 18 , 7 , 98 , 23 , 68 , 69 , 70 , 71 , 91 , 92 , 93 , 125 , 112 ,
113 , 114 , 94 , 50 , 0 , 0 , 124 , 9 , 11 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
90 , 0 , 46 , 22 , 13 , 111 , 52 , 20 , 96 , 24 , 28 , 74 , 27 , 123 , 44 , 66 ,
0 , 45 , 2 , 4 , 48 , 0 , 0 , 21 , 0 , 0 , 0 , 0 , 0 , 120 , 122 , 67 ,
};
767
768
769
770
771
772
773
774
static const uint8_t e0_keycodes [ 128 ] = {
0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 90 , 76 , 0 , 0 ,
0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
0 , 0 , 0 , 0 , 0 , 109 , 0 , 0 , 13 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
0 , 0 , 0 , 0 , 0 , 0 , 0 , 68 , 69 , 70 , 0 , 91 , 0 , 93 , 0 , 112 ,
113 , 114 , 94 , 50 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
775
1 , 3 , 25 , 26 , 49 , 52 , 72 , 73 , 97 , 99 , 111 , 118 , 120 , 122 , 67 , 0 ,
776
777
};
778
779
780
static void sunkbd_event ( void * opaque , int ch )
{
ChannelState * s = opaque ;
781
782
int release = ch & 0x80 ;
783
784
KBD_DPRINTF ( "Untranslated keycode %2.2x (%s) \n " , ch , release ? "release" :
"press" );
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
switch ( ch ) {
case 58 : // Caps lock press
s -> caps_lock_mode ^= 1 ;
if ( s -> caps_lock_mode == 2 )
return ; // Drop second press
break ;
case 69 : // Num lock press
s -> num_lock_mode ^= 1 ;
if ( s -> num_lock_mode == 2 )
return ; // Drop second press
break ;
case 186 : // Caps lock release
s -> caps_lock_mode ^= 2 ;
if ( s -> caps_lock_mode == 3 )
return ; // Drop first release
break ;
case 197 : // Num lock release
s -> num_lock_mode ^= 2 ;
if ( s -> num_lock_mode == 3 )
return ; // Drop first release
break ;
case 0xe0 :
807
808
s -> e0_mode = 1 ;
return ;
809
810
default :
break ;
811
812
813
814
815
816
817
818
}
if ( s -> e0_mode ) {
s -> e0_mode = 0 ;
ch = e0_keycodes [ ch & 0x7f ];
} else {
ch = keycodes [ ch & 0x7f ];
}
KBD_DPRINTF ( "Translated keycode %2.2x \n " , ch );
819
820
821
822
823
824
put_queue ( s , ch | release );
}
static void handle_kbd_command ( ChannelState * s , int val )
{
KBD_DPRINTF ( "Command %d \n " , val );
825
826
827
828
if ( s -> led_mode ) { // Ignore led byte
s -> led_mode = 0 ;
return ;
}
829
830
switch ( val ) {
case 1 : // Reset , return type code
831
clear_queue ( s );
832
833
834
835
put_queue ( s , 0xff );
put_queue ( s , 4 ); // Type 4
put_queue ( s , 0x7f );
break ;
836
837
838
case 0xe : // Set leds
s -> led_mode = 1 ;
break ;
839
case 7 : // Query layout
840
841
case 0xf :
clear_queue ( s );
842
843
844
put_queue ( s , 0xfe );
put_queue ( s , 0 ); // XXX , layout ?
break ;
845
default :
846
break ;
847
}
848
849
}
ths
authored
18 years ago
850
static void sunmouse_event ( void * opaque ,
851
852
853
854
855
int dx , int dy , int dz , int buttons_state )
{
ChannelState * s = opaque ;
int ch ;
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
MS_DPRINTF ( "dx=%d dy=%d buttons=%01x \n " , dx , dy , buttons_state );
ch = 0x80 | 0x7 ; /* protocol start byte, no buttons pressed */
if ( buttons_state & MOUSE_EVENT_LBUTTON )
ch ^= 0x4 ;
if ( buttons_state & MOUSE_EVENT_MBUTTON )
ch ^= 0x2 ;
if ( buttons_state & MOUSE_EVENT_RBUTTON )
ch ^= 0x1 ;
put_queue ( s , ch );
ch = dx ;
if ( ch > 127 )
ch = 127 ;
else if ( ch < - 127 )
ch =- 127 ;
put_queue ( s , ch & 0xff );
ch = - dy ;
if ( ch > 127 )
ch = 127 ;
else if ( ch < - 127 )
ch =- 127 ;
put_queue ( s , ch & 0xff );
// MSC protocol specify two extra motion bytes
put_queue ( s , 0 );
put_queue ( s , 0 );
891
892
}
893
void slavio_serial_ms_kbd_init ( target_phys_addr_t base , qemu_irq irq ,
894
int disabled , int clock , int it_shift )
895
{
896
897
898
899
DeviceState * dev ;
SysBusDevice * s ;
dev = qdev_create ( NULL , "escc" );
900
901
902
903
904
905
906
qdev_prop_set_uint32 ( dev , "disabled" , disabled );
qdev_prop_set_uint32 ( dev , "frequency" , clock );
qdev_prop_set_uint32 ( dev , "it_shift" , it_shift );
qdev_prop_set_ptr ( dev , "chrB" , NULL );
qdev_prop_set_ptr ( dev , "chrA" , NULL );
qdev_prop_set_uint32 ( dev , "chnBtype" , mouse );
qdev_prop_set_uint32 ( dev , "chnAtype" , kbd );
907
908
909
910
911
912
qdev_init ( dev );
s = sysbus_from_qdev ( dev );
sysbus_connect_irq ( s , 0 , irq );
sysbus_connect_irq ( s , 1 , irq );
sysbus_mmio_map ( s , 0 , base );
}
913
914
915
916
917
918
static void escc_init1 ( SysBusDevice * dev )
{
SerialState * s = FROM_SYSBUS ( SerialState , dev );
int io ;
unsigned int i ;
919
920
921
s -> chn [ 0 ]. disabled = s -> disabled ;
s -> chn [ 1 ]. disabled = s -> disabled ;
922
for ( i = 0 ; i < 2 ; i ++ ) {
923
sysbus_init_irq ( dev , & s -> chn [ i ]. irq );
924
s -> chn [ i ]. chn = 1 - i ;
925
s -> chn [ i ]. clock = s -> frequency / 2 ;
926
927
928
929
if ( s -> chn [ i ]. chr ) {
qemu_chr_add_handlers ( s -> chn [ i ]. chr , serial_can_receive ,
serial_receive1 , serial_event , & s -> chn [ i ]);
}
930
931
932
}
s -> chn [ 0 ]. otherchn = & s -> chn [ 1 ];
s -> chn [ 1 ]. otherchn = & s -> chn [ 0 ];
933
934
935
936
io = cpu_register_io_memory ( escc_mem_read , escc_mem_write , s );
sysbus_init_mmio ( dev , ESCC_SIZE << s -> it_shift , io );
s -> mmio_index = io ;
937
938
939
940
941
942
943
944
945
if ( s -> chn [ 0 ]. type == mouse ) {
qemu_add_mouse_event_handler ( sunmouse_event , & s -> chn [ 0 ], 0 ,
"QEMU Sun Mouse" );
}
if ( s -> chn [ 1 ]. type == kbd ) {
qemu_add_kbd_event_handler ( sunkbd_event , & s -> chn [ 1 ]);
}
register_savevm ( "escc" , - 1 , 2 , escc_save , escc_load , s );
946
qemu_register_reset ( escc_reset , s );
947
escc_reset ( s );
948
}
949
950
951
952
953
static SysBusDeviceInfo escc_info = {
. init = escc_init1 ,
. qdev . name = "escc" ,
. qdev . size = sizeof ( SerialState ),
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
. qdev . props = ( Property []) {
{
. name = "frequency" ,
. info = & qdev_prop_uint32 ,
. offset = offsetof ( SerialState , frequency ),
},
{
. name = "it_shift" ,
. info = & qdev_prop_uint32 ,
. offset = offsetof ( SerialState , it_shift ),
},
{
. name = "disabled" ,
. info = & qdev_prop_uint32 ,
. offset = offsetof ( SerialState , disabled ),
},
{
. name = "chrB" ,
. info = & qdev_prop_ptr ,
973
. offset = offsetof ( SerialState , chn [ 0 ]. chr ),
974
975
976
977
},
{
. name = "chrA" ,
. info = & qdev_prop_ptr ,
978
. offset = offsetof ( SerialState , chn [ 1 ]. chr ),
979
980
981
982
},
{
. name = "chnBtype" ,
. info = & qdev_prop_uint32 ,
983
. offset = offsetof ( SerialState , chn [ 0 ]. type ),
984
985
986
987
},
{
. name = "chnAtype" ,
. info = & qdev_prop_uint32 ,
988
. offset = offsetof ( SerialState , chn [ 1 ]. type ),
989
990
},
{ /* end of list */ }
991
992
993
994
995
996
997
998
999
}
};
static void escc_register_devices ( void )
{
sysbus_register_withprop ( & escc_info );
}
device_init ( escc_register_devices )