• Add the parameter 'order' to qemu_register_reset and sort callbacks on
    registration. On system reset, callbacks with lower order will be
    invoked before those with higher order. Update all existing users to the
    standard order 0.
    
    Note: At least for x86, the existing users seem to assume that handlers
    are called in their registration order. Therefore, the patch preserves
    this property. If someone feels bored, (s)he could try to identify this
    dependency and express it properly on callback registration.
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    Jan Kiszka authored
     
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  • While Intel's spec is not that clear here, latest changes to Linux' HPET
    code (commit c23e253e67c9d8a91a0ffa33c1f571a17f0a2403, "x86: hpet: stop
    HPET_COUNTER when programming periodic mode") strongly suggest that
    HPET_TN_SETVAL rather means: Set _both_ the comparator value and
    register.
    
    With this patch applied, I'm again able to boot 2.6.30-rc kernels as
    they no longer panic like this (which was due to the comparator
    register remaining 0):
    
    ENABLING IO-APIC IRQs
    ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
    ..MP-BIOS bug: 8254 timer not connected to IO-APIC
    ...trying to set up timer (IRQ0) through the 8259A ...
    ..... (found apic 0 pin 2) ...
    ....... failed.
    ...trying to set up timer as Virtual Wire IRQ...
    ..... failed.
    ...trying to set up timer as ExtINT IRQ...
    ..... failed :(.
    Kernel panic - not syncing: IO-APIC + timer doesn't work! [...]
    
    Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    
    
    git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7168 c046a42c-6fe2-441c-8c8c-71466251a162
    aliguori authored
     
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