gwj / at91sam9263 · Commits

Commit c50c2d6847b18b4e8983c8a7bbd5f184282ad7a4

Authored by aurel32
1 parent bf4f74c0

Remove trailing spaces introduced by commit 6081 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6085 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 4 changed files with 49 additions and 49 deletions
hw/hpet.c
  View file @c50c2d6
... ... @@ -48,7 +48,7 @@ uint32_t hpet_in_legacy_mode(void)
48 48 return 0;
49 49 }
50 50  
51   -static uint32_t timer_int_route(struct HPETTimer *timer)
  51 +static uint32_t timer_int_route(struct HPETTimer *timer)
52 52 {
53 53 uint32_t route;
54 54 route = (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
... ... @@ -80,12 +80,12 @@ static uint32_t hpet_time_after64(uint64_t a, uint64_t b)
80 80 return ((int64_t)(b) - (int64_t)(a) < 0);
81 81 }
82 82  
83   -static uint64_t ticks_to_ns(uint64_t value)
  83 +static uint64_t ticks_to_ns(uint64_t value)
84 84 {
85 85 return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS));
86 86 }
87 87  
88   -static uint64_t ns_to_ticks(uint64_t value)
  88 +static uint64_t ns_to_ticks(uint64_t value)
89 89 {
90 90 return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD));
91 91 }
... ... @@ -99,27 +99,27 @@ static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask)
99 99  
100 100 static int activating_bit(uint64_t old, uint64_t new, uint64_t mask)
101 101 {
102   - return (!(old & mask) && (new & mask));
  102 + return (!(old & mask) && (new & mask));
103 103 }
104 104  
105 105 static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
106 106 {
107   - return ((old & mask) && !(new & mask));
  107 + return ((old & mask) && !(new & mask));
108 108 }
109 109  
110   -static uint64_t hpet_get_ticks(void)
  110 +static uint64_t hpet_get_ticks(void)
111 111 {
112 112 uint64_t ticks;
113 113 ticks = ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset);
114 114 return ticks;
115 115 }
116 116  
117   -/*
118   - * calculate diff between comparator value and current ticks
  117 +/*
  118 + * calculate diff between comparator value and current ticks
119 119 */
120 120 static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current)
121 121 {
122   -
  122 +
123 123 if (t->config & HPET_TN_32BIT) {
124 124 uint32_t diff, cmp;
125 125 cmp = (uint32_t)t->cmp;
... ... @@ -143,7 +143,7 @@ static void update_irq(struct HPETTimer *timer)
143 143 if (timer->tn <= 1 && hpet_in_legacy_mode()) {
144 144 /* if LegacyReplacementRoute bit is set, HPET specification requires
145 145 * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
146   - * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
  146 + * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
147 147 */
148 148 if (timer->tn == 0) {
149 149 irq=timer->state->irqs[0];
... ... @@ -165,7 +165,7 @@ static void hpet_save(QEMUFile *f, void *opaque)
165 165 qemu_put_be64s(f, &s->config);
166 166 qemu_put_be64s(f, &s->isr);
167 167 /* save current counter value */
168   - s->hpet_counter = hpet_get_ticks();
  168 + s->hpet_counter = hpet_get_ticks();
169 169 qemu_put_be64s(f, &s->hpet_counter);
170 170  
171 171 for (i = 0; i < HPET_NUM_TIMERS; i++) {
... ... @@ -185,7 +185,7 @@ static int hpet_load(QEMUFile *f, void *opaque, int version_id)
185 185 {
186 186 HPETState *s = opaque;
187 187 int i;
188   -
  188 +
189 189 if (version_id != 1)
190 190 return -EINVAL;
191 191  
... ... @@ -209,7 +209,7 @@ static int hpet_load(QEMUFile *f, void *opaque, int version_id)
209 209 return 0;
210 210 }
211 211  
212   -/*
  212 +/*
213 213 * timer expiration callback
214 214 */
215 215 static void hpet_timer(void *opaque)
... ... @@ -229,12 +229,12 @@ static void hpet_timer(void *opaque)
229 229 t->cmp += period;
230 230  
231 231 diff = hpet_calculate_diff(t, cur_tick);
232   - qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
  232 + qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
233 233 + (int64_t)ticks_to_ns(diff));
234 234 } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
235 235 if (t->wrap_flag) {
236 236 diff = hpet_calculate_diff(t, cur_tick);
237   - qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
  237 + qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
238 238 + (int64_t)ticks_to_ns(diff));
239 239 t->wrap_flag = 0;
240 240 }
... ... @@ -247,22 +247,22 @@ static void hpet_set_timer(HPETTimer *t)
247 247 uint64_t diff;
248 248 uint32_t wrap_diff; /* how many ticks until we wrap? */
249 249 uint64_t cur_tick = hpet_get_ticks();
250   -
  250 +
251 251 /* whenever new timer is being set up, make sure wrap_flag is 0 */
252 252 t->wrap_flag = 0;
253 253 diff = hpet_calculate_diff(t, cur_tick);
254 254  
255   - /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
  255 + /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
256 256 * counter wraps in addition to an interrupt with comparator match.
257   - */
  257 + */
258 258 if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) {
259 259 wrap_diff = 0xffffffff - (uint32_t)cur_tick;
260 260 if (wrap_diff < (uint32_t)diff) {
261 261 diff = wrap_diff;
262   - t->wrap_flag = 1;
  262 + t->wrap_flag = 1;
263 263 }
264 264 }
265   - qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
  265 + qemu_mod_timer(t->qemu_timer, qemu_get_clock(vm_clock)
266 266 + (int64_t)ticks_to_ns(diff));
267 267 }
268 268  
... ... @@ -321,23 +321,23 @@ static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
321 321 case HPET_ID:
322 322 return s->capability;
323 323 case HPET_PERIOD:
324   - return s->capability >> 32;
  324 + return s->capability >> 32;
325 325 case HPET_CFG:
326 326 return s->config;
327 327 case HPET_CFG + 4:
328 328 dprintf("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
329 329 return 0;
330   - case HPET_COUNTER:
  330 + case HPET_COUNTER:
331 331 if (hpet_enabled())
332 332 cur_tick = hpet_get_ticks();
333   - else
  333 + else
334 334 cur_tick = s->hpet_counter;
335 335 dprintf("qemu: reading counter = %" PRIx64 "\n", cur_tick);
336 336 return cur_tick;
337 337 case HPET_COUNTER + 4:
338 338 if (hpet_enabled())
339 339 cur_tick = hpet_get_ticks();
340   - else
  340 + else
341 341 cur_tick = s->hpet_counter;
342 342 dprintf("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick);
343 343 return cur_tick >> 32;
... ... @@ -352,17 +352,17 @@ static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
352 352 }
353 353  
354 354 #ifdef HPET_DEBUG
355   -static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
  355 +static void hpet_ram_writeb(void *opaque, target_phys_addr_t addr,
356 356 uint32_t value)
357 357 {
358   - printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
  358 + printf("qemu: invalid hpet_write b at %" PRIx64 " = %#x\n",
359 359 addr, value);
360 360 }
361 361  
362   -static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
  362 +static void hpet_ram_writew(void *opaque, target_phys_addr_t addr,
363 363 uint32_t value)
364 364 {
365   - printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
  365 + printf("qemu: invalid hpet_write w at %" PRIx64 " = %#x\n",
366 366 addr, value);
367 367 }
368 368 #endif
... ... @@ -384,7 +384,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
384 384 uint8_t timer_id = (addr - 0x100) / 0x20;
385 385 dprintf("qemu: hpet_ram_writel timer_id = %#x \n", timer_id);
386 386 HPETTimer *timer = &s->timer[timer_id];
387   -
  387 +
388 388 switch ((addr - 0x100) % 0x20) {
389 389 case HPET_TN_CFG:
390 390 dprintf("qemu: hpet_ram_writel HPET_TN_CFG\n");
... ... @@ -434,7 +434,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
434 434 * FIXME: Clamp period to reasonable min value?
435 435 * Clamp period to reasonable max value
436 436 */
437   - new_val &= (timer->config
  437 + new_val &= (timer->config
438 438 & HPET_TN_32BIT ? ~0u : ~0ull) >> 1;
439 439 timer->period = (timer->period & 0xffffffffULL)
440 440 | new_val << 32;
... ... @@ -467,7 +467,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
467 467 }
468 468 else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
469 469 /* Halt main counter and disable interrupt generation. */
470   - s->hpet_counter = hpet_get_ticks();
  470 + s->hpet_counter = hpet_get_ticks();
471 471 for (i = 0; i < HPET_NUM_TIMERS; i++)
472 472 hpet_del_timer(&s->timer[i]);
473 473 }
... ... @@ -478,24 +478,24 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
478 478 hpet_pit_enable();
479 479 }
480 480 break;
481   - case HPET_CFG + 4:
  481 + case HPET_CFG + 4:
482 482 dprintf("qemu: invalid HPET_CFG+4 write \n");
483 483 break;
484 484 case HPET_STATUS:
485 485 /* FIXME: need to handle level-triggered interrupts */
486 486 break;
487 487 case HPET_COUNTER:
488   - if (hpet_enabled())
489   - printf("qemu: Writing counter while HPET enabled!\n");
490   - s->hpet_counter = (s->hpet_counter & 0xffffffff00000000ULL)
  488 + if (hpet_enabled())
  489 + printf("qemu: Writing counter while HPET enabled!\n");
  490 + s->hpet_counter = (s->hpet_counter & 0xffffffff00000000ULL)
491 491 | value;
492 492 dprintf("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n",
493 493 value, s->hpet_counter);
494 494 break;
495 495 case HPET_COUNTER + 4:
496   - if (hpet_enabled())
497   - printf("qemu: Writing counter while HPET enabled!\n");
498   - s->hpet_counter = (s->hpet_counter & 0xffffffffULL)
  496 + if (hpet_enabled())
  497 + printf("qemu: Writing counter while HPET enabled!\n");
  498 + s->hpet_counter = (s->hpet_counter & 0xffffffffULL)
499 499 | (((uint64_t)value) << 32);
500 500 dprintf("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n",
501 501 value, s->hpet_counter);
... ... @@ -553,10 +553,10 @@ static void hpet_reset(void *opaque) {
553 553 s->capability = 0x8086a201ULL;
554 554 s->capability |= ((HPET_CLK_PERIOD) << 32);
555 555 if (count > 0)
556   - /* we don't enable pit when hpet_reset is first called (by hpet_init)
  556 + /* we don't enable pit when hpet_reset is first called (by hpet_init)
557 557 * because hpet is taking over for pit here. On subsequent invocations,
558 558 * hpet_reset is called due to system reset. At this point control must
559   - * be returned to pit until SW reenables hpet.
  559 + * be returned to pit until SW reenables hpet.
560 560 */
561 561 hpet_pit_enable();
562 562 count = 1;
... ... @@ -566,7 +566,7 @@ static void hpet_reset(void *opaque) {
566 566 void hpet_init(qemu_irq *irq) {
567 567 int i, iomemtype;
568 568 HPETState *s;
569   -
  569 +
570 570 dprintf ("hpet_init\n");
571 571  
572 572 s = qemu_mallocz(sizeof(HPETState));
... ...
hw/hpet_emul.h
  View file @c50c2d6
... ... @@ -60,9 +60,9 @@ typedef struct HPETTimer { /* timers */
60 60 uint64_t fsb; /* FSB route, not supported now */
61 61 /* Hidden register state */
62 62 uint64_t period; /* Last value written to comparator */
63   - uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit
  63 + uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit
64 64 * mode. Next pop will be actual timer expiration.
65   - */
  65 + */
66 66 } HPETTimer;
67 67  
68 68 typedef struct HPETState {
... ...
hw/i8254.c
  View file @c50c2d6
... ... @@ -470,7 +470,7 @@ void hpet_pit_disable(void) {
470 470 qemu_del_timer(s->irq_timer);
471 471 }
472 472  
473   -/* When HPET is reset or leaving legacy mode, it must reenable i8254
  473 +/* When HPET is reset or leaving legacy mode, it must reenable i8254
474 474 * timer 0
475 475 */
476 476  
... ...
hw/mc146818rtc.c
  View file @c50c2d6
... ... @@ -71,13 +71,13 @@ struct RTCState {
71 71 };
72 72  
73 73 static void rtc_irq_raise(qemu_irq irq) {
74   - /* When HPET is operating in legacy mode, RTC interrupts are disabled
  74 + /* When HPET is operating in legacy mode, RTC interrupts are disabled
75 75 * We block qemu_irq_raise, but not qemu_irq_lower, in case legacy
76   - * mode is established while interrupt is raised. We want it to
  76 + * mode is established while interrupt is raised. We want it to
77 77 * be lowered in any case
78   - */
  78 + */
79 79 #if defined TARGET_I386 || defined TARGET_X86_64
80   - if (!hpet_in_legacy_mode())
  80 + if (!hpet_in_legacy_mode())
81 81 #endif
82 82 qemu_irq_raise(irq);
83 83 }
... ... @@ -92,7 +92,7 @@ static void rtc_timer_update(RTCState *s, int64_t current_time)
92 92  
93 93 period_code = s->cmos_data[RTC_REG_A] & 0x0f;
94 94 #if defined TARGET_I386 || defined TARGET_X86_64
95   - /* disable periodic timer if hpet is in legacy mode, since interrupts are
  95 + /* disable periodic timer if hpet is in legacy mode, since interrupts are
96 96 * disabled anyway.
97 97 */
98 98 if (period_code != 0 && (s->cmos_data[RTC_REG_B] & REG_B_PIE) && !hpet_in_legacy_mode()) {
... ...