gwj / at91sam9263 · Commits

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3653 c046a42c-6fe2-441c-8c8c-71466251a162

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r172: Enable boot mode in the exception handler for both SuperSparc and TurboSparc
r173: More CPU definitions
r174: Add Sparc64 CPU identification
r175: Add SPARCserver 600MP emulation
r176: Update OHW interface to version 3.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3649 c046a42c-6fe2-441c-8c8c-71466251a162

Use common ABI description file with OpenBIOS.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3648 c046a42c-6fe2-441c-8c8c-71466251a162

now that the SPE extension is available for all targets,
 we always need to have some 64 bits temporary registers.


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flags.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3637 c046a42c-6fe2-441c-8c8c-71466251a162

Fix frsqrtes instruction opcode.


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ADS7846 is partially compatible with TSC2046.


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running in 32 bits mode.


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adding gprh registers to store GPR MSBs when GPRs are 32 bits.
Remove not-needed-anymore ppcemb-linux-user target.
Keep ppcemb-softmmu target, which provides 1kB pages support
  and 36 bits physical address space.


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fix invalid size casts and/or sign-extensions.


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