gwj / at91sam9263 · Commits

Commit 65d6c0f33c1a496d2a782bb0ef2ef18d4ed6b763

Authored by j_mayer
1 parent 4f6cf9e8

PowerPC SPE extension fix: must always preserve GPR high bits when 

running in 32 bits mode.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3631 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 6 additions and 6 deletions
target-ppc/cpu.h
  View file @65d6c0f
... ... @@ -530,7 +530,7 @@ struct CPUPPCState {
530 530  
531 531 /* general purpose registers */
532 532 ppc_gpr_t gpr[32];
533   -#if TARGET_GPR_BITS < 64
  533 +#if !defined(TARGET_PPC64)
534 534 /* Storage for GPR MSB, used by the SPE extension */
535 535 ppc_gpr_t gprh[32];
536 536 #endif
... ...
target-ppc/op_template.h
  View file @65d6c0f
... ... @@ -58,7 +58,7 @@ void OPPROTO glue(op_store_T2_gpr_gpr, REG) (void)
58 58 #endif
59 59  
60 60 /* General purpose registers containing vector operands moves */
61   -#if TARGET_GPR_BITS < 64
  61 +#if !defined(TARGET_PPC64)
62 62 void OPPROTO glue(op_load_gpr64_T0_gpr, REG) (void)
63 63 {
64 64 T0_64 = (uint64_t)env->gpr[REG] | ((uint64_t)env->gprh[REG] << 32);
... ... @@ -101,7 +101,7 @@ void OPPROTO glue(op_store_T2_gpr64_gpr, REG) (void)
101 101 RETURN();
102 102 }
103 103 #endif
104   -#endif /* TARGET_GPR_BITS < 64 */
  104 +#endif /* !defined(TARGET_PPC64) */
105 105  
106 106 /* Altivec registers moves */
107 107 void OPPROTO glue(op_load_avr_A0_avr, REG) (void)
... ...
target-ppc/translate.c
  View file @65d6c0f
... ... @@ -5822,7 +5822,7 @@ GEN_VR_STX(vxl, 0x07, 0x0F);
5822 5822 /*** SPE extension ***/
5823 5823  
5824 5824 /* Register moves */
5825   -#if TARGET_GPR_BITS < 64
  5825 +#if !defined(TARGET_PPC64)
5826 5826  
5827 5827 GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr);
5828 5828 GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr);
... ... @@ -5836,7 +5836,7 @@ GEN32(gen_op_store_T1_gpr64, gen_op_store_T1_gpr64_gpr);
5836 5836 GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
5837 5837 #endif
5838 5838  
5839   -#else /* TARGET_GPR_BITS < 64 */
  5839 +#else /* !defined(TARGET_PPC64) */
5840 5840  
5841 5841 /* No specific load/store functions: GPRs are already 64 bits */
5842 5842 #define gen_op_load_gpr64_T0 gen_op_load_gpr_T0
... ... @@ -5851,7 +5851,7 @@ GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
5851 5851 #define gen_op_store_T2_gpr64 gen_op_store_T2_gpr
5852 5852 #endif
5853 5853  
5854   -#endif /* TARGET_GPR_BITS < 64 */
  5854 +#endif /* !defined(TARGET_PPC64) */
5855 5855  
5856 5856 #define GEN_SPE(name0, name1, opc2, opc3, inval, type) \
5857 5857 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type) \
... ...