gwj / at91sam9263 · Commits

Commit e3a79bcadd9792c6efd4b7379fed026061bdfdbb

Authored by blueswir1
1 parent 045380be

Fix Debian serial console boot problem reported by Aurelien Jarno 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3883 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 15 additions and 13 deletions
hw/slavio_intctl.c
  View file @e3a79bc
@@ -59,7 +59,7 @@ typedef struct SLAVIO_INTCTLState { @@ -59,7 +59,7 @@ typedef struct SLAVIO_INTCTLState {
59 #endif 59 #endif
60 qemu_irq *cpu_irqs[MAX_CPUS]; 60 qemu_irq *cpu_irqs[MAX_CPUS];
61 const uint32_t *intbit_to_level; 61 const uint32_t *intbit_to_level;
62 - uint32_t cputimer_bit; 62 + uint32_t cputimer_lbit, cputimer_mbit;
63 uint32_t pil_out[MAX_CPUS]; 63 uint32_t pil_out[MAX_CPUS];
64 } SLAVIO_INTCTLState; 64 } SLAVIO_INTCTLState;
65 65
@@ -257,7 +257,6 @@ static void slavio_check_interrupts(void *opaque) @@ -257,7 +257,6 @@ static void slavio_check_interrupts(void *opaque)
257 if (pending & (1 << j)) 257 if (pending & (1 << j))
258 pil_pending |= 1 << s->intbit_to_level[j]; 258 pil_pending |= 1 << s->intbit_to_level[j];
259 } 259 }
260 - pil_pending |= s->intreg_pending[i] & CPU_HARDIRQ_MASK;  
261 } 260 }
262 pil_pending |= (s->intreg_pending[i] & CPU_SOFTIRQ_MASK) >> 16; 261 pil_pending |= (s->intreg_pending[i] & CPU_SOFTIRQ_MASK) >> 16;
263 262
@@ -307,10 +306,13 @@ static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level) @@ -307,10 +306,13 @@ static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
307 306
308 DPRINTF("Set cpu %d local timer level %d\n", cpu, level); 307 DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
309 308
310 - if (level)  
311 - s->intreg_pending[cpu] |= s->cputimer_bit;  
312 - else  
313 - s->intreg_pending[cpu] &= ~s->cputimer_bit; 309 + if (level) {
  310 + s->intregm_pending |= s->cputimer_mbit;
  311 + s->intreg_pending[cpu] |= s->cputimer_lbit;
  312 + } else {
  313 + s->intregm_pending &= ~s->cputimer_mbit;
  314 + s->intreg_pending[cpu] &= ~s->cputimer_lbit;
  315 + }
314 316
315 slavio_check_interrupts(s); 317 slavio_check_interrupts(s);
316 } 318 }
@@ -388,7 +390,8 @@ void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg, @@ -388,7 +390,8 @@ void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
388 *irq = qemu_allocate_irqs(slavio_set_irq, s, 32); 390 *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
389 391
390 *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS); 392 *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
391 - s->cputimer_bit = 1 << cputimer; 393 + s->cputimer_mbit = 1 << cputimer;
  394 + s->cputimer_lbit = 1 << intbit_to_level[cputimer];
392 slavio_intctl_reset(s); 395 slavio_intctl_reset(s);
393 return s; 396 return s;
394 } 397 }
hw/sun4m.c
  View file @e3a79bc
@@ -89,8 +89,7 @@ struct hwdef { @@ -89,8 +89,7 @@ struct hwdef {
89 target_phys_addr_t sun4c_intctl_base, sun4c_counter_base; 89 target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
90 long vram_size, nvram_size; 90 long vram_size, nvram_size;
91 // IRQ numbers are not PIL ones, but master interrupt controller 91 // IRQ numbers are not PIL ones, but master interrupt controller
92 - // register bit numbers except for clock_irq, which indexes cpu  
93 - // interrupt controller register 92 + // register bit numbers
94 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq; 93 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
95 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq; 94 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq;
96 int machine_id; // For NVRAM 95 int machine_id; // For NVRAM
@@ -695,7 +694,7 @@ static const struct hwdef hwdefs[] = { @@ -695,7 +694,7 @@ static const struct hwdef hwdefs[] = {
695 .nvram_size = 0x2000, 694 .nvram_size = 0x2000,
696 .esp_irq = 18, 695 .esp_irq = 18,
697 .le_irq = 16, 696 .le_irq = 16,
698 - .clock_irq = 14, 697 + .clock_irq = 7,
699 .clock1_irq = 19, 698 .clock1_irq = 19,
700 .ms_kb_irq = 14, 699 .ms_kb_irq = 14,
701 .ser_irq = 15, 700 .ser_irq = 15,
@@ -736,7 +735,7 @@ static const struct hwdef hwdefs[] = { @@ -736,7 +735,7 @@ static const struct hwdef hwdefs[] = {
736 .nvram_size = 0x2000, 735 .nvram_size = 0x2000,
737 .esp_irq = 18, 736 .esp_irq = 18,
738 .le_irq = 16, 737 .le_irq = 16,
739 - .clock_irq = 14, 738 + .clock_irq = 7,
740 .clock1_irq = 19, 739 .clock1_irq = 19,
741 .ms_kb_irq = 14, 740 .ms_kb_irq = 14,
742 .ser_irq = 15, 741 .ser_irq = 15,
@@ -777,7 +776,7 @@ static const struct hwdef hwdefs[] = { @@ -777,7 +776,7 @@ static const struct hwdef hwdefs[] = {
777 .nvram_size = 0x2000, 776 .nvram_size = 0x2000,
778 .esp_irq = 18, 777 .esp_irq = 18,
779 .le_irq = 16, 778 .le_irq = 16,
780 - .clock_irq = 14, 779 + .clock_irq = 7,
781 .clock1_irq = 19, 780 .clock1_irq = 19,
782 .ms_kb_irq = 14, 781 .ms_kb_irq = 14,
783 .ser_irq = 15, 782 .ser_irq = 15,
@@ -818,7 +817,7 @@ static const struct hwdef hwdefs[] = { @@ -818,7 +817,7 @@ static const struct hwdef hwdefs[] = {
818 .nvram_size = 0x2000, 817 .nvram_size = 0x2000,
819 .esp_irq = 18, 818 .esp_irq = 18,
820 .le_irq = 16, 819 .le_irq = 16,
821 - .clock_irq = 14, 820 + .clock_irq = 7,
822 .clock1_irq = 19, 821 .clock1_irq = 19,
823 .ms_kb_irq = 14, 822 .ms_kb_irq = 14,
824 .ser_irq = 15, 823 .ser_irq = 15,