Commit 045380be94a96dc8dc2d31cb23d1fc634440f53b
1 parent
7c560456
More ASIs
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3882 c046a42c-6fe2-441c-8c8c-71466251a162
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18 additions
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6 deletions
target-sparc/op_helper.c
| ... | ... | @@ -337,6 +337,10 @@ void helper_ld_asi(int asi, int size, int sign) |
| 337 | 337 | DPRINTF_MMU("mmu_read: reg[%d] = 0x%08x\n", reg, ret); |
| 338 | 338 | } |
| 339 | 339 | break; |
| 340 | + case 5: // Turbosparc ITLB Diagnostic | |
| 341 | + case 6: // Turbosparc DTLB Diagnostic | |
| 342 | + case 7: // Turbosparc IOTLB Diagnostic | |
| 343 | + break; | |
| 340 | 344 | case 9: /* Supervisor code access */ |
| 341 | 345 | switch(size) { |
| 342 | 346 | case 1: |
| ... | ... | @@ -441,9 +445,13 @@ void helper_ld_asi(int asi, int size, int sign) |
| 441 | 445 | break; |
| 442 | 446 | } |
| 443 | 447 | break; |
| 448 | + case 0x30: // Turbosparc secondary cache diagnostic | |
| 449 | + case 0x31: // Turbosparc RAM snoop | |
| 450 | + case 0x32: // Turbosparc page table descriptor diagnostic | |
| 444 | 451 | case 0x39: /* data cache diagnostic register */ |
| 445 | 452 | ret = 0; |
| 446 | 453 | break; |
| 454 | + case 8: /* User code access, XXX */ | |
| 447 | 455 | default: |
| 448 | 456 | do_unassigned_access(T0, 0, 0, asi); |
| 449 | 457 | ret = 0; |
| ... | ... | @@ -621,6 +629,10 @@ void helper_st_asi(int asi, int size) |
| 621 | 629 | #endif |
| 622 | 630 | } |
| 623 | 631 | break; |
| 632 | + case 5: // Turbosparc ITLB Diagnostic | |
| 633 | + case 6: // Turbosparc DTLB Diagnostic | |
| 634 | + case 7: // Turbosparc IOTLB Diagnostic | |
| 635 | + break; | |
| 624 | 636 | case 0xa: /* User data access */ |
| 625 | 637 | switch(size) { |
| 626 | 638 | case 1: |
| ... | ... | @@ -713,8 +725,7 @@ void helper_st_asi(int asi, int size) |
| 713 | 725 | } |
| 714 | 726 | } |
| 715 | 727 | break; |
| 716 | - case 0x2e: /* MMU passthrough, 0xexxxxxxxx */ | |
| 717 | - case 0x2f: /* MMU passthrough, 0xfxxxxxxxx */ | |
| 728 | + case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ | |
| 718 | 729 | { |
| 719 | 730 | switch(size) { |
| 720 | 731 | case 1: |
| ... | ... | @@ -738,16 +749,17 @@ void helper_st_asi(int asi, int size) |
| 738 | 749 | } |
| 739 | 750 | } |
| 740 | 751 | break; |
| 741 | - case 0x30: /* store buffer tags */ | |
| 742 | - case 0x31: /* store buffer data or Ross RT620 I-cache flush */ | |
| 743 | - case 0x32: /* store buffer control */ | |
| 752 | + case 0x30: // store buffer tags or Turbosparc secondary cache diagnostic | |
| 753 | + case 0x31: // store buffer data, Ross RT620 I-cache flush or | |
| 754 | + // Turbosparc snoop RAM | |
| 755 | + case 0x32: // store buffer control or Turbosparc page table descriptor diagnostic | |
| 744 | 756 | case 0x36: /* I-cache flash clear */ |
| 745 | 757 | case 0x37: /* D-cache flash clear */ |
| 746 | 758 | case 0x38: /* breakpoint diagnostics */ |
| 747 | 759 | case 0x4c: /* breakpoint action */ |
| 748 | 760 | break; |
| 761 | + case 8: /* User code access, XXX */ | |
| 749 | 762 | case 9: /* Supervisor code access, XXX */ |
| 750 | - case 0x21 ... 0x2d: /* MMU passthrough, unassigned */ | |
| 751 | 763 | default: |
| 752 | 764 | do_unassigned_access(T0, 1, 0, asi); |
| 753 | 765 | break; | ... | ... |