gwj / at91sam9263 · Commits

Commit 4af984a76a7d1b021b91027d5c4219882ea6cbdf

Authored by blueswir1
1 parent ce5b3c3d

Concentrate cpu_T[012] use to one function 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4110 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 318 additions and 337 deletions
target-sparc/translate.c
  View file @4af984a
@@ -471,75 +471,75 @@ static inline void gen_tag_tv(TCGv src1, TCGv src2) @@ -471,75 +471,75 @@ static inline void gen_tag_tv(TCGv src1, TCGv src2)
471 gen_set_label(l1); 471 gen_set_label(l1);
472 } 472 }
473 473
474 -static inline void gen_op_add_T1_T0_cc(void) 474 +static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
475 { 475 {
476 - tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);  
477 - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 476 + tcg_gen_mov_tl(cpu_cc_src, src1);
  477 + tcg_gen_add_tl(dst, src1, src2);
478 gen_cc_clear_icc(); 478 gen_cc_clear_icc();
479 - gen_cc_NZ_icc(cpu_T[0]);  
480 - gen_cc_C_add_icc(cpu_T[0], cpu_cc_src);  
481 - gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_T[1]); 479 + gen_cc_NZ_icc(dst);
  480 + gen_cc_C_add_icc(dst, cpu_cc_src);
  481 + gen_cc_V_add_icc(dst, cpu_cc_src, src2);
482 #ifdef TARGET_SPARC64 482 #ifdef TARGET_SPARC64
483 gen_cc_clear_xcc(); 483 gen_cc_clear_xcc();
484 - gen_cc_NZ_xcc(cpu_T[0]);  
485 - gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src);  
486 - gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); 484 + gen_cc_NZ_xcc(dst);
  485 + gen_cc_C_add_xcc(dst, cpu_cc_src);
  486 + gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
487 #endif 487 #endif
488 } 488 }
489 489
490 -static inline void gen_op_addx_T1_T0_cc(void) 490 +static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
491 { 491 {
492 - tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); 492 + tcg_gen_mov_tl(cpu_cc_src, src1);
493 gen_mov_reg_C(cpu_tmp0, cpu_psr); 493 gen_mov_reg_C(cpu_tmp0, cpu_psr);
494 - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp0); 494 + tcg_gen_add_tl(dst, src1, cpu_tmp0);
495 gen_cc_clear_icc(); 495 gen_cc_clear_icc();
496 - gen_cc_C_add_icc(cpu_T[0], cpu_cc_src); 496 + gen_cc_C_add_icc(dst, cpu_cc_src);
497 #ifdef TARGET_SPARC64 497 #ifdef TARGET_SPARC64
498 gen_cc_clear_xcc(); 498 gen_cc_clear_xcc();
499 - gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src); 499 + gen_cc_C_add_xcc(dst, cpu_cc_src);
500 #endif 500 #endif
501 - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);  
502 - gen_cc_NZ_icc(cpu_T[0]);  
503 - gen_cc_C_add_icc(cpu_T[0], cpu_cc_src);  
504 - gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_T[1]); 501 + tcg_gen_add_tl(dst, dst, src2);
  502 + gen_cc_NZ_icc(dst);
  503 + gen_cc_C_add_icc(dst, cpu_cc_src);
  504 + gen_cc_V_add_icc(dst, cpu_cc_src, src2);
505 #ifdef TARGET_SPARC64 505 #ifdef TARGET_SPARC64
506 - gen_cc_NZ_xcc(cpu_T[0]);  
507 - gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src);  
508 - gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); 506 + gen_cc_NZ_xcc(dst);
  507 + gen_cc_C_add_xcc(dst, cpu_cc_src);
  508 + gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
509 #endif 509 #endif
510 } 510 }
511 511
512 -static inline void gen_op_tadd_T1_T0_cc(void) 512 +static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
513 { 513 {
514 - tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);  
515 - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 514 + tcg_gen_mov_tl(cpu_cc_src, src1);
  515 + tcg_gen_add_tl(dst, src1, src2);
516 gen_cc_clear_icc(); 516 gen_cc_clear_icc();
517 - gen_cc_NZ_icc(cpu_T[0]);  
518 - gen_cc_C_add_icc(cpu_T[0], cpu_cc_src);  
519 - gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_T[1]);  
520 - gen_cc_V_tag(cpu_cc_src, cpu_T[1]); 517 + gen_cc_NZ_icc(dst);
  518 + gen_cc_C_add_icc(dst, cpu_cc_src);
  519 + gen_cc_V_add_icc(dst, cpu_cc_src, src2);
  520 + gen_cc_V_tag(cpu_cc_src, src2);
521 #ifdef TARGET_SPARC64 521 #ifdef TARGET_SPARC64
522 gen_cc_clear_xcc(); 522 gen_cc_clear_xcc();
523 - gen_cc_NZ_xcc(cpu_T[0]);  
524 - gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src);  
525 - gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); 523 + gen_cc_NZ_xcc(dst);
  524 + gen_cc_C_add_xcc(dst, cpu_cc_src);
  525 + gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
526 #endif 526 #endif
527 } 527 }
528 528
529 -static inline void gen_op_tadd_T1_T0_ccTV(void) 529 +static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
530 { 530 {
531 - gen_tag_tv(cpu_T[0], cpu_T[1]);  
532 - tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);  
533 - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);  
534 - gen_add_tv(cpu_T[0], cpu_cc_src, cpu_T[1]); 531 + gen_tag_tv(src1, src2);
  532 + tcg_gen_mov_tl(cpu_cc_src, src1);
  533 + tcg_gen_add_tl(dst, src1, src2);
  534 + gen_add_tv(dst, cpu_cc_src, src2);
535 gen_cc_clear_icc(); 535 gen_cc_clear_icc();
536 - gen_cc_NZ_icc(cpu_T[0]);  
537 - gen_cc_C_add_icc(cpu_T[0], cpu_cc_src); 536 + gen_cc_NZ_icc(dst);
  537 + gen_cc_C_add_icc(dst, cpu_cc_src);
538 #ifdef TARGET_SPARC64 538 #ifdef TARGET_SPARC64
539 gen_cc_clear_xcc(); 539 gen_cc_clear_xcc();
540 - gen_cc_NZ_xcc(cpu_T[0]);  
541 - gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src);  
542 - gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); 540 + gen_cc_NZ_xcc(dst);
  541 + gen_cc_C_add_xcc(dst, cpu_cc_src);
  542 + gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
543 #endif 543 #endif
544 } 544 }
545 545
@@ -632,79 +632,79 @@ static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) @@ -632,79 +632,79 @@ static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
632 tcg_gen_discard_tl(r_temp); 632 tcg_gen_discard_tl(r_temp);
633 } 633 }
634 634
635 -static inline void gen_op_sub_T1_T0_cc(void) 635 +static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
636 { 636 {
637 - tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);  
638 - tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 637 + tcg_gen_mov_tl(cpu_cc_src, src1);
  638 + tcg_gen_sub_tl(dst, src1, src2);
639 gen_cc_clear_icc(); 639 gen_cc_clear_icc();
640 - gen_cc_NZ_icc(cpu_T[0]);  
641 - gen_cc_C_sub_icc(cpu_cc_src, cpu_T[1]);  
642 - gen_cc_V_sub_icc(cpu_T[0], cpu_cc_src, cpu_T[1]); 640 + gen_cc_NZ_icc(dst);
  641 + gen_cc_C_sub_icc(cpu_cc_src, src2);
  642 + gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
643 #ifdef TARGET_SPARC64 643 #ifdef TARGET_SPARC64
644 gen_cc_clear_xcc(); 644 gen_cc_clear_xcc();
645 - gen_cc_NZ_xcc(cpu_T[0]);  
646 - gen_cc_C_sub_xcc(cpu_cc_src, cpu_T[1]);  
647 - gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); 645 + gen_cc_NZ_xcc(dst);
  646 + gen_cc_C_sub_xcc(cpu_cc_src, src2);
  647 + gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
648 #endif 648 #endif
649 } 649 }
650 650
651 -static inline void gen_op_subx_T1_T0_cc(void) 651 +static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
652 { 652 {
653 - tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); 653 + tcg_gen_mov_tl(cpu_cc_src, src1);
654 gen_mov_reg_C(cpu_tmp0, cpu_psr); 654 gen_mov_reg_C(cpu_tmp0, cpu_psr);
655 - tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp0); 655 + tcg_gen_sub_tl(dst, src1, cpu_tmp0);
656 gen_cc_clear_icc(); 656 gen_cc_clear_icc();
657 - gen_cc_C_sub_icc(cpu_T[0], cpu_cc_src); 657 + gen_cc_C_sub_icc(dst, cpu_cc_src);
658 #ifdef TARGET_SPARC64 658 #ifdef TARGET_SPARC64
659 gen_cc_clear_xcc(); 659 gen_cc_clear_xcc();
660 - gen_cc_C_sub_xcc(cpu_T[0], cpu_cc_src); 660 + gen_cc_C_sub_xcc(dst, cpu_cc_src);
661 #endif 661 #endif
662 - tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);  
663 - gen_cc_NZ_icc(cpu_T[0]);  
664 - gen_cc_C_sub_icc(cpu_T[0], cpu_cc_src);  
665 - gen_cc_V_sub_icc(cpu_T[0], cpu_cc_src, cpu_T[1]); 662 + tcg_gen_sub_tl(dst, dst, src2);
  663 + gen_cc_NZ_icc(dst);
  664 + gen_cc_C_sub_icc(dst, cpu_cc_src);
  665 + gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
666 #ifdef TARGET_SPARC64 666 #ifdef TARGET_SPARC64
667 - gen_cc_NZ_xcc(cpu_T[0]);  
668 - gen_cc_C_sub_xcc(cpu_T[0], cpu_cc_src);  
669 - gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); 667 + gen_cc_NZ_xcc(dst);
  668 + gen_cc_C_sub_xcc(dst, cpu_cc_src);
  669 + gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
670 #endif 670 #endif
671 } 671 }
672 672
673 -static inline void gen_op_tsub_T1_T0_cc(void) 673 +static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
674 { 674 {
675 - tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);  
676 - tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 675 + tcg_gen_mov_tl(cpu_cc_src, src1);
  676 + tcg_gen_sub_tl(dst, src1, src2);
677 gen_cc_clear_icc(); 677 gen_cc_clear_icc();
678 - gen_cc_NZ_icc(cpu_T[0]);  
679 - gen_cc_C_sub_icc(cpu_cc_src, cpu_T[1]);  
680 - gen_cc_V_sub_icc(cpu_T[0], cpu_cc_src, cpu_T[1]);  
681 - gen_cc_V_tag(cpu_cc_src, cpu_T[1]); 678 + gen_cc_NZ_icc(dst);
  679 + gen_cc_C_sub_icc(cpu_cc_src, src2);
  680 + gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
  681 + gen_cc_V_tag(cpu_cc_src, src2);
682 #ifdef TARGET_SPARC64 682 #ifdef TARGET_SPARC64
683 gen_cc_clear_xcc(); 683 gen_cc_clear_xcc();
684 - gen_cc_NZ_xcc(cpu_T[0]);  
685 - gen_cc_C_sub_xcc(cpu_cc_src, cpu_T[1]);  
686 - gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); 684 + gen_cc_NZ_xcc(dst);
  685 + gen_cc_C_sub_xcc(cpu_cc_src, src2);
  686 + gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
687 #endif 687 #endif
688 } 688 }
689 689
690 -static inline void gen_op_tsub_T1_T0_ccTV(void) 690 +static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
691 { 691 {
692 - gen_tag_tv(cpu_T[0], cpu_T[1]);  
693 - tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);  
694 - tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);  
695 - gen_sub_tv(cpu_T[0], cpu_cc_src, cpu_T[1]); 692 + gen_tag_tv(src1, src2);
  693 + tcg_gen_mov_tl(cpu_cc_src, src1);
  694 + tcg_gen_sub_tl(dst, src1, src2);
  695 + gen_sub_tv(dst, cpu_cc_src, src2);
696 gen_cc_clear_icc(); 696 gen_cc_clear_icc();
697 - gen_cc_NZ_icc(cpu_T[0]);  
698 - gen_cc_C_sub_icc(cpu_cc_src, cpu_T[1]); 697 + gen_cc_NZ_icc(dst);
  698 + gen_cc_C_sub_icc(cpu_cc_src, src2);
699 #ifdef TARGET_SPARC64 699 #ifdef TARGET_SPARC64
700 gen_cc_clear_xcc(); 700 gen_cc_clear_xcc();
701 - gen_cc_NZ_xcc(cpu_T[0]);  
702 - gen_cc_C_sub_xcc(cpu_cc_src, cpu_T[1]);  
703 - gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); 701 + gen_cc_NZ_xcc(dst);
  702 + gen_cc_C_sub_xcc(cpu_cc_src, src2);
  703 + gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
704 #endif 704 #endif
705 } 705 }
706 706
707 -static inline void gen_op_mulscc_T1_T0(void) 707 +static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
708 { 708 {
709 TCGv r_temp, r_temp2; 709 TCGv r_temp, r_temp2;
710 int l1, l2; 710 int l1, l2;
@@ -722,7 +722,7 @@ static inline void gen_op_mulscc_T1_T0(void) @@ -722,7 +722,7 @@ static inline void gen_op_mulscc_T1_T0(void)
722 tcg_gen_trunc_tl_i32(r_temp2, r_temp); 722 tcg_gen_trunc_tl_i32(r_temp2, r_temp);
723 tcg_gen_andi_i32(r_temp2, r_temp2, 0x1); 723 tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
724 tcg_gen_brcond_i32(TCG_COND_EQ, r_temp2, tcg_const_i32(0), l1); 724 tcg_gen_brcond_i32(TCG_COND_EQ, r_temp2, tcg_const_i32(0), l1);
725 - tcg_gen_mov_tl(cpu_cc_src2, cpu_T[1]); 725 + tcg_gen_mov_tl(cpu_cc_src2, src2);
726 tcg_gen_br(l2); 726 tcg_gen_br(l2);
727 gen_set_label(l1); 727 gen_set_label(l1);
728 tcg_gen_movi_tl(cpu_cc_src2, 0); 728 tcg_gen_movi_tl(cpu_cc_src2, 0);
@@ -730,7 +730,7 @@ static inline void gen_op_mulscc_T1_T0(void) @@ -730,7 +730,7 @@ static inline void gen_op_mulscc_T1_T0(void)
730 730
731 // b2 = T0 & 1; 731 // b2 = T0 & 1;
732 // env->y = (b2 << 31) | (env->y >> 1); 732 // env->y = (b2 << 31) | (env->y >> 1);
733 - tcg_gen_trunc_tl_i32(r_temp2, cpu_T[0]); 733 + tcg_gen_trunc_tl_i32(r_temp2, src1);
734 tcg_gen_andi_i32(r_temp2, r_temp2, 0x1); 734 tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
735 tcg_gen_shli_i32(r_temp2, r_temp2, 31); 735 tcg_gen_shli_i32(r_temp2, r_temp2, 31);
736 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y)); 736 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
@@ -746,61 +746,61 @@ static inline void gen_op_mulscc_T1_T0(void) @@ -746,61 +746,61 @@ static inline void gen_op_mulscc_T1_T0(void)
746 // T0 = (b1 << 31) | (T0 >> 1); 746 // T0 = (b1 << 31) | (T0 >> 1);
747 // src1 = T0; 747 // src1 = T0;
748 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31); 748 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
749 - tcg_gen_shri_tl(cpu_cc_src, cpu_T[0], 1); 749 + tcg_gen_shri_tl(cpu_cc_src, src1, 1);
750 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0); 750 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
751 751
752 /* do addition and update flags */ 752 /* do addition and update flags */
753 - tcg_gen_add_tl(cpu_T[0], cpu_cc_src, cpu_cc_src2); 753 + tcg_gen_add_tl(dst, cpu_cc_src, cpu_cc_src2);
754 tcg_gen_discard_tl(r_temp); 754 tcg_gen_discard_tl(r_temp);
755 755
756 gen_cc_clear_icc(); 756 gen_cc_clear_icc();
757 - gen_cc_NZ_icc(cpu_T[0]);  
758 - gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_cc_src2);  
759 - gen_cc_C_add_icc(cpu_T[0], cpu_cc_src); 757 + gen_cc_NZ_icc(dst);
  758 + gen_cc_V_add_icc(dst, cpu_cc_src, cpu_cc_src2);
  759 + gen_cc_C_add_icc(dst, cpu_cc_src);
760 } 760 }
761 761
762 -static inline void gen_op_umul_T1_T0(void) 762 +static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
763 { 763 {
764 TCGv r_temp, r_temp2; 764 TCGv r_temp, r_temp2;
765 765
766 r_temp = tcg_temp_new(TCG_TYPE_I64); 766 r_temp = tcg_temp_new(TCG_TYPE_I64);
767 r_temp2 = tcg_temp_new(TCG_TYPE_I64); 767 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
768 768
769 - tcg_gen_extu_tl_i64(r_temp, cpu_T[1]);  
770 - tcg_gen_extu_tl_i64(r_temp2, cpu_T[0]); 769 + tcg_gen_extu_tl_i64(r_temp, src2);
  770 + tcg_gen_extu_tl_i64(r_temp2, src1);
771 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); 771 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
772 772
773 tcg_gen_shri_i64(r_temp, r_temp2, 32); 773 tcg_gen_shri_i64(r_temp, r_temp2, 32);
774 tcg_gen_trunc_i64_i32(r_temp, r_temp); 774 tcg_gen_trunc_i64_i32(r_temp, r_temp);
775 tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); 775 tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
776 #ifdef TARGET_SPARC64 776 #ifdef TARGET_SPARC64
777 - tcg_gen_mov_i64(cpu_T[0], r_temp2); 777 + tcg_gen_mov_i64(dst, r_temp2);
778 #else 778 #else
779 - tcg_gen_trunc_i64_tl(cpu_T[0], r_temp2); 779 + tcg_gen_trunc_i64_tl(dst, r_temp2);
780 #endif 780 #endif
781 781
782 tcg_gen_discard_i64(r_temp); 782 tcg_gen_discard_i64(r_temp);
783 tcg_gen_discard_i64(r_temp2); 783 tcg_gen_discard_i64(r_temp2);
784 } 784 }
785 785
786 -static inline void gen_op_smul_T1_T0(void) 786 +static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
787 { 787 {
788 TCGv r_temp, r_temp2; 788 TCGv r_temp, r_temp2;
789 789
790 r_temp = tcg_temp_new(TCG_TYPE_I64); 790 r_temp = tcg_temp_new(TCG_TYPE_I64);
791 r_temp2 = tcg_temp_new(TCG_TYPE_I64); 791 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
792 792
793 - tcg_gen_ext_tl_i64(r_temp, cpu_T[1]);  
794 - tcg_gen_ext_tl_i64(r_temp2, cpu_T[0]); 793 + tcg_gen_ext_tl_i64(r_temp, src2);
  794 + tcg_gen_ext_tl_i64(r_temp2, src1);
795 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2); 795 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
796 796
797 tcg_gen_shri_i64(r_temp, r_temp2, 32); 797 tcg_gen_shri_i64(r_temp, r_temp2, 32);
798 tcg_gen_trunc_i64_i32(r_temp, r_temp); 798 tcg_gen_trunc_i64_i32(r_temp, r_temp);
799 tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y)); 799 tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
800 #ifdef TARGET_SPARC64 800 #ifdef TARGET_SPARC64
801 - tcg_gen_mov_i64(cpu_T[0], r_temp2); 801 + tcg_gen_mov_i64(dst, r_temp2);
802 #else 802 #else
803 - tcg_gen_trunc_i64_tl(cpu_T[0], r_temp2); 803 + tcg_gen_trunc_i64_tl(dst, r_temp2);
804 #endif 804 #endif
805 805
806 tcg_gen_discard_i64(r_temp); 806 tcg_gen_discard_i64(r_temp);
@@ -818,29 +818,29 @@ static inline void gen_trap_ifdivzero_tl(TCGv divisor) @@ -818,29 +818,29 @@ static inline void gen_trap_ifdivzero_tl(TCGv divisor)
818 gen_set_label(l1); 818 gen_set_label(l1);
819 } 819 }
820 820
821 -static inline void gen_op_sdivx_T1_T0(void) 821 +static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
822 { 822 {
823 int l1, l2; 823 int l1, l2;
824 824
825 l1 = gen_new_label(); 825 l1 = gen_new_label();
826 l2 = gen_new_label(); 826 l2 = gen_new_label();
827 - gen_trap_ifdivzero_tl(cpu_T[1]);  
828 - tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[0], tcg_const_tl(INT64_MIN), l1);  
829 - tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[1], tcg_const_tl(-1), l1);  
830 - tcg_gen_movi_i64(cpu_T[0], INT64_MIN); 827 + gen_trap_ifdivzero_tl(src2);
  828 + tcg_gen_brcond_tl(TCG_COND_NE, src1, tcg_const_tl(INT64_MIN), l1);
  829 + tcg_gen_brcond_tl(TCG_COND_NE, src2, tcg_const_tl(-1), l1);
  830 + tcg_gen_movi_i64(dst, INT64_MIN);
831 tcg_gen_br(l2); 831 tcg_gen_br(l2);
832 gen_set_label(l1); 832 gen_set_label(l1);
833 - tcg_gen_div_i64(cpu_T[0], cpu_T[0], cpu_T[1]); 833 + tcg_gen_div_i64(dst, src1, src2);
834 gen_set_label(l2); 834 gen_set_label(l2);
835 } 835 }
836 #endif 836 #endif
837 837
838 -static inline void gen_op_div_cc(void) 838 +static inline void gen_op_div_cc(TCGv dst)
839 { 839 {
840 int l1; 840 int l1;
841 841
842 gen_cc_clear_icc(); 842 gen_cc_clear_icc();
843 - gen_cc_NZ_icc(cpu_T[0]); 843 + gen_cc_NZ_icc(dst);
844 l1 = gen_new_label(); 844 l1 = gen_new_label();
845 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2)); 845 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2));
846 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1); 846 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
@@ -848,13 +848,13 @@ static inline void gen_op_div_cc(void) @@ -848,13 +848,13 @@ static inline void gen_op_div_cc(void)
848 gen_set_label(l1); 848 gen_set_label(l1);
849 } 849 }
850 850
851 -static inline void gen_op_logic_T0_cc(void) 851 +static inline void gen_op_logic_cc(TCGv dst)
852 { 852 {
853 gen_cc_clear_icc(); 853 gen_cc_clear_icc();
854 - gen_cc_NZ_icc(cpu_T[0]); 854 + gen_cc_NZ_icc(dst);
855 #ifdef TARGET_SPARC64 855 #ifdef TARGET_SPARC64
856 gen_cc_clear_xcc(); 856 gen_cc_clear_xcc();
857 - gen_cc_NZ_xcc(cpu_T[0]); 857 + gen_cc_NZ_xcc(dst);
858 #endif 858 #endif
859 } 859 }
860 860
@@ -1177,35 +1177,36 @@ static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2, @@ -1177,35 +1177,36 @@ static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1177 gen_set_label(l2); 1177 gen_set_label(l2);
1178 } 1178 }
1179 1179
1180 -/* call this function before using T2 as it may have been set for a jump */  
1181 -static inline void flush_T2(DisasContext * dc) 1180 +/* call this function before using the condition register as it may
  1181 + have been set for a jump */
  1182 +static inline void flush_cond(DisasContext *dc, TCGv cond)
1182 { 1183 {
1183 if (dc->npc == JUMP_PC) { 1184 if (dc->npc == JUMP_PC) {
1184 - gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); 1185 + gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1185 dc->npc = DYNAMIC_PC; 1186 dc->npc = DYNAMIC_PC;
1186 } 1187 }
1187 } 1188 }
1188 1189
1189 -static inline void save_npc(DisasContext * dc) 1190 +static inline void save_npc(DisasContext *dc, TCGv cond)
1190 { 1191 {
1191 if (dc->npc == JUMP_PC) { 1192 if (dc->npc == JUMP_PC) {
1192 - gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); 1193 + gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1193 dc->npc = DYNAMIC_PC; 1194 dc->npc = DYNAMIC_PC;
1194 } else if (dc->npc != DYNAMIC_PC) { 1195 } else if (dc->npc != DYNAMIC_PC) {
1195 tcg_gen_movi_tl(cpu_npc, dc->npc); 1196 tcg_gen_movi_tl(cpu_npc, dc->npc);
1196 } 1197 }
1197 } 1198 }
1198 1199
1199 -static inline void save_state(DisasContext * dc) 1200 +static inline void save_state(DisasContext *dc, TCGv cond)
1200 { 1201 {
1201 tcg_gen_movi_tl(cpu_pc, dc->pc); 1202 tcg_gen_movi_tl(cpu_pc, dc->pc);
1202 - save_npc(dc); 1203 + save_npc(dc, cond);
1203 } 1204 }
1204 1205
1205 -static inline void gen_mov_pc_npc(DisasContext * dc) 1206 +static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1206 { 1207 {
1207 if (dc->npc == JUMP_PC) { 1208 if (dc->npc == JUMP_PC) {
1208 - gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]); 1209 + gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1209 tcg_gen_mov_tl(cpu_pc, cpu_npc); 1210 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1210 dc->pc = DYNAMIC_PC; 1211 dc->pc = DYNAMIC_PC;
1211 } else if (dc->npc == DYNAMIC_PC) { 1212 } else if (dc->npc == DYNAMIC_PC) {
@@ -1371,20 +1372,21 @@ static const int gen_tcg_cond_reg[8] = { @@ -1371,20 +1372,21 @@ static const int gen_tcg_cond_reg[8] = {
1371 TCG_COND_LT, 1372 TCG_COND_LT,
1372 }; 1373 };
1373 1374
1374 -static inline void gen_cond_reg(TCGv r_dst, int cond) 1375 +static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1375 { 1376 {
1376 int l1; 1377 int l1;
1377 1378
1378 l1 = gen_new_label(); 1379 l1 = gen_new_label();
1379 tcg_gen_movi_tl(r_dst, 0); 1380 tcg_gen_movi_tl(r_dst, 0);
1380 - tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], tcg_const_tl(0), l1); 1381 + tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], r_src, tcg_const_tl(0), l1);
1381 tcg_gen_movi_tl(r_dst, 1); 1382 tcg_gen_movi_tl(r_dst, 1);
1382 gen_set_label(l1); 1383 gen_set_label(l1);
1383 } 1384 }
1384 #endif 1385 #endif
1385 1386
1386 /* XXX: potentially incorrect if dynamic npc */ 1387 /* XXX: potentially incorrect if dynamic npc */
1387 -static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) 1388 +static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
  1389 + TCGv r_cond)
1388 { 1390 {
1389 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); 1391 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1390 target_ulong target = dc->pc + offset; 1392 target_ulong target = dc->pc + offset;
@@ -1408,10 +1410,10 @@ static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) @@ -1408,10 +1410,10 @@ static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
1408 dc->npc = target; 1410 dc->npc = target;
1409 } 1411 }
1410 } else { 1412 } else {
1411 - flush_T2(dc);  
1412 - gen_cond(cpu_T[2], cc, cond); 1413 + flush_cond(dc, r_cond);
  1414 + gen_cond(r_cond, cc, cond);
1413 if (a) { 1415 if (a) {
1414 - gen_branch_a(dc, target, dc->npc, cpu_T[2]); 1416 + gen_branch_a(dc, target, dc->npc, r_cond);
1415 dc->is_br = 1; 1417 dc->is_br = 1;
1416 } else { 1418 } else {
1417 dc->pc = dc->npc; 1419 dc->pc = dc->npc;
@@ -1423,7 +1425,8 @@ static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) @@ -1423,7 +1425,8 @@ static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
1423 } 1425 }
1424 1426
1425 /* XXX: potentially incorrect if dynamic npc */ 1427 /* XXX: potentially incorrect if dynamic npc */
1426 -static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) 1428 +static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
  1429 + TCGv r_cond)
1427 { 1430 {
1428 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29)); 1431 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1429 target_ulong target = dc->pc + offset; 1432 target_ulong target = dc->pc + offset;
@@ -1447,10 +1450,10 @@ static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) @@ -1447,10 +1450,10 @@ static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
1447 dc->npc = target; 1450 dc->npc = target;
1448 } 1451 }
1449 } else { 1452 } else {
1450 - flush_T2(dc);  
1451 - gen_fcond(cpu_T[2], cc, cond); 1453 + flush_cond(dc, r_cond);
  1454 + gen_fcond(r_cond, cc, cond);
1452 if (a) { 1455 if (a) {
1453 - gen_branch_a(dc, target, dc->npc, cpu_T[2]); 1456 + gen_branch_a(dc, target, dc->npc, r_cond);
1454 dc->is_br = 1; 1457 dc->is_br = 1;
1455 } else { 1458 } else {
1456 dc->pc = dc->npc; 1459 dc->pc = dc->npc;
@@ -1463,15 +1466,16 @@ static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc) @@ -1463,15 +1466,16 @@ static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
1463 1466
1464 #ifdef TARGET_SPARC64 1467 #ifdef TARGET_SPARC64
1465 /* XXX: potentially incorrect if dynamic npc */ 1468 /* XXX: potentially incorrect if dynamic npc */
1466 -static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn) 1469 +static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
  1470 + TCGv r_cond, TCGv r_reg)
1467 { 1471 {
1468 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29)); 1472 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1469 target_ulong target = dc->pc + offset; 1473 target_ulong target = dc->pc + offset;
1470 1474
1471 - flush_T2(dc);  
1472 - gen_cond_reg(cpu_T[2], cond); 1475 + flush_cond(dc, r_cond);
  1476 + gen_cond_reg(r_cond, cond, r_reg);
1473 if (a) { 1477 if (a) {
1474 - gen_branch_a(dc, target, dc->npc, cpu_T[2]); 1478 + gen_branch_a(dc, target, dc->npc, r_cond);
1475 dc->is_br = 1; 1479 dc->is_br = 1;
1476 } else { 1480 } else {
1477 dc->pc = dc->npc; 1481 dc->pc = dc->npc;
@@ -1606,11 +1610,11 @@ static inline void gen_op_fpexception_im(int fsr_flags) @@ -1606,11 +1610,11 @@ static inline void gen_op_fpexception_im(int fsr_flags)
1606 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_FP_EXCP)); 1610 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_FP_EXCP));
1607 } 1611 }
1608 1612
1609 -static int gen_trap_ifnofpu(DisasContext * dc) 1613 +static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1610 { 1614 {
1611 #if !defined(CONFIG_USER_ONLY) 1615 #if !defined(CONFIG_USER_ONLY)
1612 if (!dc->fpu_enabled) { 1616 if (!dc->fpu_enabled) {
1613 - save_state(dc); 1617 + save_state(dc, r_cond);
1614 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NFPU_INSN)); 1618 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NFPU_INSN));
1615 dc->is_br = 1; 1619 dc->is_br = 1;
1616 return 1; 1620 return 1;
@@ -1629,26 +1633,6 @@ static inline void gen_clear_float_exceptions(void) @@ -1629,26 +1633,6 @@ static inline void gen_clear_float_exceptions(void)
1629 tcg_gen_helper_0_0(helper_clear_float_exceptions); 1633 tcg_gen_helper_0_0(helper_clear_float_exceptions);
1630 } 1634 }
1631 1635
1632 -static inline void gen_check_align(TCGv r_addr, int align)  
1633 -{  
1634 - tcg_gen_helper_0_2(helper_check_align, r_addr, tcg_const_i32(align));  
1635 -}  
1636 -  
1637 -static inline void gen_op_check_align_T0_1(void)  
1638 -{  
1639 - gen_check_align(cpu_T[0], 1);  
1640 -}  
1641 -  
1642 -static inline void gen_op_check_align_T0_3(void)  
1643 -{  
1644 - gen_check_align(cpu_T[0], 3);  
1645 -}  
1646 -  
1647 -static inline void gen_op_check_align_T0_7(void)  
1648 -{  
1649 - gen_check_align(cpu_T[0], 7);  
1650 -}  
1651 -  
1652 /* asi moves */ 1636 /* asi moves */
1653 #ifdef TARGET_SPARC64 1637 #ifdef TARGET_SPARC64
1654 static inline TCGv gen_get_asi(int insn, TCGv r_addr) 1638 static inline TCGv gen_get_asi(int insn, TCGv r_addr)
@@ -1668,37 +1652,36 @@ static inline TCGv gen_get_asi(int insn, TCGv r_addr) @@ -1668,37 +1652,36 @@ static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1668 return r_asi; 1652 return r_asi;
1669 } 1653 }
1670 1654
1671 -static inline void gen_ld_asi(int insn, int size, int sign) 1655 +static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
1672 { 1656 {
1673 TCGv r_asi; 1657 TCGv r_asi;
1674 1658
1675 - r_asi = gen_get_asi(insn, cpu_T[0]);  
1676 - tcg_gen_helper_1_4(helper_ld_asi, cpu_T[1], cpu_T[0], r_asi, 1659 + r_asi = gen_get_asi(insn, addr);
  1660 + tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi,
1677 tcg_const_i32(size), tcg_const_i32(sign)); 1661 tcg_const_i32(size), tcg_const_i32(sign));
1678 tcg_gen_discard_i32(r_asi); 1662 tcg_gen_discard_i32(r_asi);
1679 } 1663 }
1680 1664
1681 -static inline void gen_st_asi(int insn, int size) 1665 +static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1682 { 1666 {
1683 TCGv r_asi; 1667 TCGv r_asi;
1684 1668
1685 - r_asi = gen_get_asi(insn, cpu_T[0]);  
1686 - tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_asi,  
1687 - tcg_const_i32(size)); 1669 + r_asi = gen_get_asi(insn, addr);
  1670 + tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, tcg_const_i32(size));
1688 tcg_gen_discard_i32(r_asi); 1671 tcg_gen_discard_i32(r_asi);
1689 } 1672 }
1690 1673
1691 -static inline void gen_ldf_asi(int insn, int size, int rd) 1674 +static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1692 { 1675 {
1693 TCGv r_asi; 1676 TCGv r_asi;
1694 1677
1695 - r_asi = gen_get_asi(insn, cpu_T[0]);  
1696 - tcg_gen_helper_0_4(helper_ldf_asi, cpu_T[0], r_asi, tcg_const_i32(size), 1678 + r_asi = gen_get_asi(insn, addr);
  1679 + tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, tcg_const_i32(size),
1697 tcg_const_i32(rd)); 1680 tcg_const_i32(rd));
1698 tcg_gen_discard_i32(r_asi); 1681 tcg_gen_discard_i32(r_asi);
1699 } 1682 }
1700 1683
1701 -static inline void gen_stf_asi(int insn, int size, int rd) 1684 +static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1702 { 1685 {
1703 TCGv r_asi; 1686 TCGv r_asi;
1704 1687
@@ -1708,145 +1691,143 @@ static inline void gen_stf_asi(int insn, int size, int rd) @@ -1708,145 +1691,143 @@ static inline void gen_stf_asi(int insn, int size, int rd)
1708 tcg_gen_discard_i32(r_asi); 1691 tcg_gen_discard_i32(r_asi);
1709 } 1692 }
1710 1693
1711 -static inline void gen_swap_asi(int insn) 1694 +static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1712 { 1695 {
1713 TCGv r_temp, r_asi; 1696 TCGv r_temp, r_asi;
1714 1697
1715 r_temp = tcg_temp_new(TCG_TYPE_I32); 1698 r_temp = tcg_temp_new(TCG_TYPE_I32);
1716 - r_asi = gen_get_asi(insn, cpu_T[0]);  
1717 - tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], r_asi, 1699 + r_asi = gen_get_asi(insn, addr);
  1700 + tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, r_asi,
1718 tcg_const_i32(4), tcg_const_i32(0)); 1701 tcg_const_i32(4), tcg_const_i32(0));
1719 - tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_temp, r_asi, 1702 + tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi,
1720 tcg_const_i32(4)); 1703 tcg_const_i32(4));
1721 - tcg_gen_extu_i32_tl(cpu_T[1], r_temp); 1704 + tcg_gen_extu_i32_tl(dst, r_temp);
1722 tcg_gen_discard_i32(r_asi); 1705 tcg_gen_discard_i32(r_asi);
1723 tcg_gen_discard_i32(r_temp); 1706 tcg_gen_discard_i32(r_temp);
1724 } 1707 }
1725 1708
1726 -static inline void gen_ldda_asi(int insn) 1709 +static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1727 { 1710 {
1728 TCGv r_asi; 1711 TCGv r_asi;
1729 1712
1730 - r_asi = gen_get_asi(insn, cpu_T[0]);  
1731 - tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, cpu_T[0], r_asi, 1713 + r_asi = gen_get_asi(insn, addr);
  1714 + tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi,
1732 tcg_const_i32(8), tcg_const_i32(0)); 1715 tcg_const_i32(8), tcg_const_i32(0));
1733 - tcg_gen_andi_i64(cpu_T[0], cpu_tmp64, 0xffffffffULL); 1716 + tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL);
1734 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32); 1717 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1735 - tcg_gen_andi_i64(cpu_T[1], cpu_tmp64, 0xffffffffULL); 1718 + tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL);
1736 tcg_gen_discard_i32(r_asi); 1719 tcg_gen_discard_i32(r_asi);
1737 } 1720 }
1738 1721
1739 -static inline void gen_stda_asi(int insn, int rd) 1722 +static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1740 { 1723 {
1741 TCGv r_temp, r_asi; 1724 TCGv r_temp, r_asi;
1742 1725
1743 r_temp = tcg_temp_new(TCG_TYPE_I32); 1726 r_temp = tcg_temp_new(TCG_TYPE_I32);
1744 gen_movl_reg_TN(rd + 1, r_temp); 1727 gen_movl_reg_TN(rd + 1, r_temp);
1745 - tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_T[1], 1728 + tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1746 r_temp); 1729 r_temp);
1747 - r_asi = gen_get_asi(insn, cpu_T[0]);  
1748 - tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_tmp64, r_asi, 1730 + r_asi = gen_get_asi(insn, addr);
  1731 + tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi,
1749 tcg_const_i32(8)); 1732 tcg_const_i32(8));
1750 tcg_gen_discard_i32(r_asi); 1733 tcg_gen_discard_i32(r_asi);
1751 tcg_gen_discard_i32(r_temp); 1734 tcg_gen_discard_i32(r_temp);
1752 } 1735 }
1753 1736
1754 -static inline void gen_cas_asi(int insn, int rd) 1737 +static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
1755 { 1738 {
1756 TCGv r_val1, r_asi; 1739 TCGv r_val1, r_asi;
1757 1740
1758 r_val1 = tcg_temp_new(TCG_TYPE_I32); 1741 r_val1 = tcg_temp_new(TCG_TYPE_I32);
1759 gen_movl_reg_TN(rd, r_val1); 1742 gen_movl_reg_TN(rd, r_val1);
1760 - r_asi = gen_get_asi(insn, cpu_T[0]);  
1761 - tcg_gen_helper_1_4(helper_cas_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],  
1762 - r_asi); 1743 + r_asi = gen_get_asi(insn, addr);
  1744 + tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1763 tcg_gen_discard_i32(r_asi); 1745 tcg_gen_discard_i32(r_asi);
1764 tcg_gen_discard_i32(r_val1); 1746 tcg_gen_discard_i32(r_val1);
1765 } 1747 }
1766 1748
1767 -static inline void gen_casx_asi(int insn, int rd) 1749 +static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
1768 { 1750 {
1769 TCGv r_asi; 1751 TCGv r_asi;
1770 1752
1771 gen_movl_reg_TN(rd, cpu_tmp64); 1753 gen_movl_reg_TN(rd, cpu_tmp64);
1772 - r_asi = gen_get_asi(insn, cpu_T[0]);  
1773 - tcg_gen_helper_1_4(helper_casx_asi, cpu_T[1], cpu_T[0], cpu_tmp64, cpu_T[1],  
1774 - r_asi); 1754 + r_asi = gen_get_asi(insn, addr);
  1755 + tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1775 tcg_gen_discard_i32(r_asi); 1756 tcg_gen_discard_i32(r_asi);
1776 } 1757 }
1777 1758
1778 #elif !defined(CONFIG_USER_ONLY) 1759 #elif !defined(CONFIG_USER_ONLY)
1779 1760
1780 -static inline void gen_ld_asi(int insn, int size, int sign) 1761 +static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
1781 { 1762 {
1782 int asi; 1763 int asi;
1783 1764
1784 asi = GET_FIELD(insn, 19, 26); 1765 asi = GET_FIELD(insn, 19, 26);
1785 - tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, cpu_T[0], tcg_const_i32(asi), 1766 + tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
1786 tcg_const_i32(size), tcg_const_i32(sign)); 1767 tcg_const_i32(size), tcg_const_i32(sign));
1787 - tcg_gen_trunc_i64_tl(cpu_T[1], cpu_tmp64); 1768 + tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1788 } 1769 }
1789 1770
1790 -static inline void gen_st_asi(int insn, int size) 1771 +static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1791 { 1772 {
1792 int asi; 1773 int asi;
1793 1774
1794 - tcg_gen_extu_tl_i64(cpu_tmp64, cpu_T[1]); 1775 + tcg_gen_extu_tl_i64(cpu_tmp64, src);
1795 asi = GET_FIELD(insn, 19, 26); 1776 asi = GET_FIELD(insn, 19, 26);
1796 - tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_tmp64, tcg_const_i32(asi), 1777 + tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
1797 tcg_const_i32(size)); 1778 tcg_const_i32(size));
1798 } 1779 }
1799 1780
1800 -static inline void gen_swap_asi(int insn) 1781 +static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1801 { 1782 {
1802 int asi; 1783 int asi;
1803 TCGv r_temp; 1784 TCGv r_temp;
1804 1785
1805 r_temp = tcg_temp_new(TCG_TYPE_I32); 1786 r_temp = tcg_temp_new(TCG_TYPE_I32);
1806 asi = GET_FIELD(insn, 19, 26); 1787 asi = GET_FIELD(insn, 19, 26);
1807 - tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], tcg_const_i32(asi), 1788 + tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, tcg_const_i32(asi),
1808 tcg_const_i32(4), tcg_const_i32(0)); 1789 tcg_const_i32(4), tcg_const_i32(0));
1809 - tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], tcg_const_i32(asi), 1790 + tcg_gen_helper_0_4(helper_st_asi, addr, dst, tcg_const_i32(asi),
1810 tcg_const_i32(4)); 1791 tcg_const_i32(4));
1811 - tcg_gen_extu_i32_tl(cpu_T[1], r_temp); 1792 + tcg_gen_extu_i32_tl(dst, r_temp);
1812 tcg_gen_discard_i32(r_temp); 1793 tcg_gen_discard_i32(r_temp);
1813 } 1794 }
1814 1795
1815 -static inline void gen_ldda_asi(int insn) 1796 +static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1816 { 1797 {
1817 int asi; 1798 int asi;
1818 1799
1819 asi = GET_FIELD(insn, 19, 26); 1800 asi = GET_FIELD(insn, 19, 26);
1820 - tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, cpu_T[0], tcg_const_i32(asi), 1801 + tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
1821 tcg_const_i32(8), tcg_const_i32(0)); 1802 tcg_const_i32(8), tcg_const_i32(0));
1822 - tcg_gen_trunc_i64_tl(cpu_T[0], cpu_tmp64); 1803 + tcg_gen_trunc_i64_tl(lo, cpu_tmp64);
1823 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32); 1804 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1824 - tcg_gen_trunc_i64_tl(cpu_T[1], cpu_tmp64); 1805 + tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1825 } 1806 }
1826 1807
1827 -static inline void gen_stda_asi(int insn, int rd) 1808 +static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1828 { 1809 {
1829 int asi; 1810 int asi;
1830 TCGv r_temp; 1811 TCGv r_temp;
1831 1812
1832 r_temp = tcg_temp_new(TCG_TYPE_I32); 1813 r_temp = tcg_temp_new(TCG_TYPE_I32);
1833 gen_movl_reg_TN(rd + 1, r_temp); 1814 gen_movl_reg_TN(rd + 1, r_temp);
1834 - tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_T[1], r_temp); 1815 + tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1835 asi = GET_FIELD(insn, 19, 26); 1816 asi = GET_FIELD(insn, 19, 26);
1836 - tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_tmp64, tcg_const_i32(asi), 1817 + tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
1837 tcg_const_i32(8)); 1818 tcg_const_i32(8));
1838 } 1819 }
1839 #endif 1820 #endif
1840 1821
1841 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) 1822 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1842 -static inline void gen_ldstub_asi(int insn) 1823 +static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1843 { 1824 {
1844 int asi; 1825 int asi;
1845 1826
1846 - gen_ld_asi(insn, 1, 0); 1827 + gen_ld_asi(dst, addr, insn, 1, 0);
1847 1828
1848 asi = GET_FIELD(insn, 19, 26); 1829 asi = GET_FIELD(insn, 19, 26);
1849 - tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], tcg_const_i64(0xffULL), 1830 + tcg_gen_helper_0_4(helper_st_asi, addr, tcg_const_i64(0xffULL),
1850 tcg_const_i32(asi), tcg_const_i32(1)); 1831 tcg_const_i32(asi), tcg_const_i32(1));
1851 } 1832 }
1852 #endif 1833 #endif
@@ -1876,9 +1857,9 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1876,9 +1857,9 @@ static void disas_sparc_insn(DisasContext * dc)
1876 target <<= 2; 1857 target <<= 2;
1877 cc = GET_FIELD_SP(insn, 20, 21); 1858 cc = GET_FIELD_SP(insn, 20, 21);
1878 if (cc == 0) 1859 if (cc == 0)
1879 - do_branch(dc, target, insn, 0); 1860 + do_branch(dc, target, insn, 0, cpu_T[2]);
1880 else if (cc == 2) 1861 else if (cc == 2)
1881 - do_branch(dc, target, insn, 1); 1862 + do_branch(dc, target, insn, 1, cpu_T[2]);
1882 else 1863 else
1883 goto illegal_insn; 1864 goto illegal_insn;
1884 goto jmp_insn; 1865 goto jmp_insn;
@@ -1891,18 +1872,18 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1891,18 +1872,18 @@ static void disas_sparc_insn(DisasContext * dc)
1891 target <<= 2; 1872 target <<= 2;
1892 rs1 = GET_FIELD(insn, 13, 17); 1873 rs1 = GET_FIELD(insn, 13, 17);
1893 gen_movl_reg_TN(rs1, cpu_T[0]); 1874 gen_movl_reg_TN(rs1, cpu_T[0]);
1894 - do_branch_reg(dc, target, insn); 1875 + do_branch_reg(dc, target, insn, cpu_T[2], cpu_T[0]);
1895 goto jmp_insn; 1876 goto jmp_insn;
1896 } 1877 }
1897 case 0x5: /* V9 FBPcc */ 1878 case 0x5: /* V9 FBPcc */
1898 { 1879 {
1899 int cc = GET_FIELD_SP(insn, 20, 21); 1880 int cc = GET_FIELD_SP(insn, 20, 21);
1900 - if (gen_trap_ifnofpu(dc)) 1881 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
1901 goto jmp_insn; 1882 goto jmp_insn;
1902 target = GET_FIELD_SP(insn, 0, 18); 1883 target = GET_FIELD_SP(insn, 0, 18);
1903 target = sign_extend(target, 19); 1884 target = sign_extend(target, 19);
1904 target <<= 2; 1885 target <<= 2;
1905 - do_fbranch(dc, target, insn, cc); 1886 + do_fbranch(dc, target, insn, cc, cpu_T[2]);
1906 goto jmp_insn; 1887 goto jmp_insn;
1907 } 1888 }
1908 #else 1889 #else
@@ -1916,17 +1897,17 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1916,17 +1897,17 @@ static void disas_sparc_insn(DisasContext * dc)
1916 target = GET_FIELD(insn, 10, 31); 1897 target = GET_FIELD(insn, 10, 31);
1917 target = sign_extend(target, 22); 1898 target = sign_extend(target, 22);
1918 target <<= 2; 1899 target <<= 2;
1919 - do_branch(dc, target, insn, 0); 1900 + do_branch(dc, target, insn, 0, cpu_T[2]);
1920 goto jmp_insn; 1901 goto jmp_insn;
1921 } 1902 }
1922 case 0x6: /* FBN+x */ 1903 case 0x6: /* FBN+x */
1923 { 1904 {
1924 - if (gen_trap_ifnofpu(dc)) 1905 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
1925 goto jmp_insn; 1906 goto jmp_insn;
1926 target = GET_FIELD(insn, 10, 31); 1907 target = GET_FIELD(insn, 10, 31);
1927 target = sign_extend(target, 22); 1908 target = sign_extend(target, 22);
1928 target <<= 2; 1909 target <<= 2;
1929 - do_fbranch(dc, target, insn, 0); 1910 + do_fbranch(dc, target, insn, 0, cpu_T[2]);
1930 goto jmp_insn; 1911 goto jmp_insn;
1931 } 1912 }
1932 case 0x4: /* SETHI */ 1913 case 0x4: /* SETHI */
@@ -1954,7 +1935,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1954,7 +1935,7 @@ static void disas_sparc_insn(DisasContext * dc)
1954 1935
1955 gen_movl_TN_reg(15, tcg_const_tl(dc->pc)); 1936 gen_movl_TN_reg(15, tcg_const_tl(dc->pc));
1956 target += dc->pc; 1937 target += dc->pc;
1957 - gen_mov_pc_npc(dc); 1938 + gen_mov_pc_npc(dc, cpu_T[2]);
1958 dc->npc = target; 1939 dc->npc = target;
1959 } 1940 }
1960 goto jmp_insn; 1941 goto jmp_insn;
@@ -1982,7 +1963,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1982,7 +1963,7 @@ static void disas_sparc_insn(DisasContext * dc)
1982 } 1963 }
1983 cond = GET_FIELD(insn, 3, 6); 1964 cond = GET_FIELD(insn, 3, 6);
1984 if (cond == 0x8) { 1965 if (cond == 0x8) {
1985 - save_state(dc); 1966 + save_state(dc, cpu_T[2]);
1986 tcg_gen_helper_0_1(helper_trap, cpu_T[0]); 1967 tcg_gen_helper_0_1(helper_trap, cpu_T[0]);
1987 } else if (cond != 0) { 1968 } else if (cond != 0) {
1988 TCGv r_cond = tcg_temp_new(TCG_TYPE_TL); 1969 TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
@@ -1990,7 +1971,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1990,7 +1971,7 @@ static void disas_sparc_insn(DisasContext * dc)
1990 /* V9 icc/xcc */ 1971 /* V9 icc/xcc */
1991 int cc = GET_FIELD_SP(insn, 11, 12); 1972 int cc = GET_FIELD_SP(insn, 11, 12);
1992 1973
1993 - save_state(dc); 1974 + save_state(dc, cpu_T[2]);
1994 if (cc == 0) 1975 if (cc == 0)
1995 gen_cond(r_cond, 0, cond); 1976 gen_cond(r_cond, 0, cond);
1996 else if (cc == 2) 1977 else if (cc == 2)
@@ -1998,7 +1979,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -1998,7 +1979,7 @@ static void disas_sparc_insn(DisasContext * dc)
1998 else 1979 else
1999 goto illegal_insn; 1980 goto illegal_insn;
2000 #else 1981 #else
2001 - save_state(dc); 1982 + save_state(dc, cpu_T[2]);
2002 gen_cond(r_cond, 0, cond); 1983 gen_cond(r_cond, 0, cond);
2003 #endif 1984 #endif
2004 tcg_gen_helper_0_2(helper_trapcc, cpu_T[0], r_cond); 1985 tcg_gen_helper_0_2(helper_trapcc, cpu_T[0], r_cond);
@@ -2060,7 +2041,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2060,7 +2041,7 @@ static void disas_sparc_insn(DisasContext * dc)
2060 case 0xf: /* V9 membar */ 2041 case 0xf: /* V9 membar */
2061 break; /* no effect */ 2042 break; /* no effect */
2062 case 0x13: /* Graphics Status */ 2043 case 0x13: /* Graphics Status */
2063 - if (gen_trap_ifnofpu(dc)) 2044 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
2064 goto jmp_insn; 2045 goto jmp_insn;
2065 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, gsr)); 2046 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, gsr));
2066 gen_movl_TN_reg(rd, cpu_T[0]); 2047 gen_movl_TN_reg(rd, cpu_T[0]);
@@ -2275,7 +2256,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2275,7 +2256,7 @@ static void disas_sparc_insn(DisasContext * dc)
2275 break; 2256 break;
2276 #endif 2257 #endif
2277 } else if (xop == 0x34) { /* FPU Operations */ 2258 } else if (xop == 0x34) { /* FPU Operations */
2278 - if (gen_trap_ifnofpu(dc)) 2259 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
2279 goto jmp_insn; 2260 goto jmp_insn;
2280 gen_op_clear_ieee_excp_and_FTT(); 2261 gen_op_clear_ieee_excp_and_FTT();
2281 rs1 = GET_FIELD(insn, 13, 17); 2262 rs1 = GET_FIELD(insn, 13, 17);
@@ -2650,7 +2631,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2650,7 +2631,7 @@ static void disas_sparc_insn(DisasContext * dc)
2650 #ifdef TARGET_SPARC64 2631 #ifdef TARGET_SPARC64
2651 int cond; 2632 int cond;
2652 #endif 2633 #endif
2653 - if (gen_trap_ifnofpu(dc)) 2634 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
2654 goto jmp_insn; 2635 goto jmp_insn;
2655 gen_op_clear_ieee_excp_and_FTT(); 2636 gen_op_clear_ieee_excp_and_FTT();
2656 rs1 = GET_FIELD(insn, 13, 17); 2637 rs1 = GET_FIELD(insn, 13, 17);
@@ -2977,28 +2958,28 @@ static void disas_sparc_insn(DisasContext * dc) @@ -2977,28 +2958,28 @@ static void disas_sparc_insn(DisasContext * dc)
2977 switch (xop & ~0x10) { 2958 switch (xop & ~0x10) {
2978 case 0x0: 2959 case 0x0:
2979 if (xop & 0x10) 2960 if (xop & 0x10)
2980 - gen_op_add_T1_T0_cc(); 2961 + gen_op_add_cc(cpu_T[0], cpu_T[0], cpu_T[1]);
2981 else 2962 else
2982 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 2963 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2983 break; 2964 break;
2984 case 0x1: 2965 case 0x1:
2985 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 2966 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2986 if (xop & 0x10) 2967 if (xop & 0x10)
2987 - gen_op_logic_T0_cc(); 2968 + gen_op_logic_cc(cpu_T[0]);
2988 break; 2969 break;
2989 case 0x2: 2970 case 0x2:
2990 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 2971 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2991 if (xop & 0x10) 2972 if (xop & 0x10)
2992 - gen_op_logic_T0_cc(); 2973 + gen_op_logic_cc(cpu_T[0]);
2993 break; 2974 break;
2994 case 0x3: 2975 case 0x3:
2995 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 2976 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2996 if (xop & 0x10) 2977 if (xop & 0x10)
2997 - gen_op_logic_T0_cc(); 2978 + gen_op_logic_cc(cpu_T[0]);
2998 break; 2979 break;
2999 case 0x4: 2980 case 0x4:
3000 if (xop & 0x10) 2981 if (xop & 0x10)
3001 - gen_op_sub_T1_T0_cc(); 2982 + gen_op_sub_cc(cpu_T[0], cpu_T[0], cpu_T[1]);
3002 else 2983 else
3003 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 2984 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3004 break; 2985 break;
@@ -3006,23 +2987,23 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3006,23 +2987,23 @@ static void disas_sparc_insn(DisasContext * dc)
3006 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); 2987 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
3007 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 2988 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3008 if (xop & 0x10) 2989 if (xop & 0x10)
3009 - gen_op_logic_T0_cc(); 2990 + gen_op_logic_cc(cpu_T[0]);
3010 break; 2991 break;
3011 case 0x6: 2992 case 0x6:
3012 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); 2993 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
3013 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 2994 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3014 if (xop & 0x10) 2995 if (xop & 0x10)
3015 - gen_op_logic_T0_cc(); 2996 + gen_op_logic_cc(cpu_T[0]);
3016 break; 2997 break;
3017 case 0x7: 2998 case 0x7:
3018 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1); 2999 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
3019 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 3000 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3020 if (xop & 0x10) 3001 if (xop & 0x10)
3021 - gen_op_logic_T0_cc(); 3002 + gen_op_logic_cc(cpu_T[0]);
3022 break; 3003 break;
3023 case 0x8: 3004 case 0x8:
3024 if (xop & 0x10) 3005 if (xop & 0x10)
3025 - gen_op_addx_T1_T0_cc(); 3006 + gen_op_addx_cc(cpu_T[0], cpu_T[0], cpu_T[1]);
3026 else { 3007 else {
3027 gen_mov_reg_C(cpu_tmp0, cpu_psr); 3008 gen_mov_reg_C(cpu_tmp0, cpu_psr);
3028 tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0); 3009 tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
@@ -3035,18 +3016,18 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3035,18 +3016,18 @@ static void disas_sparc_insn(DisasContext * dc)
3035 break; 3016 break;
3036 #endif 3017 #endif
3037 case 0xa: 3018 case 0xa:
3038 - gen_op_umul_T1_T0(); 3019 + gen_op_umul(cpu_T[0], cpu_T[0], cpu_T[1]);
3039 if (xop & 0x10) 3020 if (xop & 0x10)
3040 - gen_op_logic_T0_cc(); 3021 + gen_op_logic_cc(cpu_T[0]);
3041 break; 3022 break;
3042 case 0xb: 3023 case 0xb:
3043 - gen_op_smul_T1_T0(); 3024 + gen_op_smul(cpu_T[0], cpu_T[0], cpu_T[1]);
3044 if (xop & 0x10) 3025 if (xop & 0x10)
3045 - gen_op_logic_T0_cc(); 3026 + gen_op_logic_cc(cpu_T[0]);
3046 break; 3027 break;
3047 case 0xc: 3028 case 0xc:
3048 if (xop & 0x10) 3029 if (xop & 0x10)
3049 - gen_op_subx_T1_T0_cc(); 3030 + gen_op_subx_cc(cpu_T[0], cpu_T[0], cpu_T[1]);
3050 else { 3031 else {
3051 gen_mov_reg_C(cpu_tmp0, cpu_psr); 3032 gen_mov_reg_C(cpu_tmp0, cpu_psr);
3052 tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0); 3033 tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
@@ -3062,12 +3043,12 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3062,12 +3043,12 @@ static void disas_sparc_insn(DisasContext * dc)
3062 case 0xe: 3043 case 0xe:
3063 tcg_gen_helper_1_2(helper_udiv, cpu_T[0], cpu_T[0], cpu_T[1]); 3044 tcg_gen_helper_1_2(helper_udiv, cpu_T[0], cpu_T[0], cpu_T[1]);
3064 if (xop & 0x10) 3045 if (xop & 0x10)
3065 - gen_op_div_cc(); 3046 + gen_op_div_cc(cpu_T[0]);
3066 break; 3047 break;
3067 case 0xf: 3048 case 0xf:
3068 tcg_gen_helper_1_2(helper_sdiv, cpu_T[0], cpu_T[0], cpu_T[1]); 3049 tcg_gen_helper_1_2(helper_sdiv, cpu_T[0], cpu_T[0], cpu_T[1]);
3069 if (xop & 0x10) 3050 if (xop & 0x10)
3070 - gen_op_div_cc(); 3051 + gen_op_div_cc(cpu_T[0]);
3071 break; 3052 break;
3072 default: 3053 default:
3073 goto illegal_insn; 3054 goto illegal_insn;
@@ -3076,25 +3057,25 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3076,25 +3057,25 @@ static void disas_sparc_insn(DisasContext * dc)
3076 } else { 3057 } else {
3077 switch (xop) { 3058 switch (xop) {
3078 case 0x20: /* taddcc */ 3059 case 0x20: /* taddcc */
3079 - gen_op_tadd_T1_T0_cc(); 3060 + gen_op_tadd_cc(cpu_T[0], cpu_T[0], cpu_T[1]);
3080 gen_movl_TN_reg(rd, cpu_T[0]); 3061 gen_movl_TN_reg(rd, cpu_T[0]);
3081 break; 3062 break;
3082 case 0x21: /* tsubcc */ 3063 case 0x21: /* tsubcc */
3083 - gen_op_tsub_T1_T0_cc(); 3064 + gen_op_tsub_cc(cpu_T[0], cpu_T[0], cpu_T[1]);
3084 gen_movl_TN_reg(rd, cpu_T[0]); 3065 gen_movl_TN_reg(rd, cpu_T[0]);
3085 break; 3066 break;
3086 case 0x22: /* taddcctv */ 3067 case 0x22: /* taddcctv */
3087 - save_state(dc);  
3088 - gen_op_tadd_T1_T0_ccTV(); 3068 + save_state(dc, cpu_T[2]);
  3069 + gen_op_tadd_ccTV(cpu_T[0], cpu_T[0], cpu_T[1]);
3089 gen_movl_TN_reg(rd, cpu_T[0]); 3070 gen_movl_TN_reg(rd, cpu_T[0]);
3090 break; 3071 break;
3091 case 0x23: /* tsubcctv */ 3072 case 0x23: /* tsubcctv */
3092 - save_state(dc);  
3093 - gen_op_tsub_T1_T0_ccTV(); 3073 + save_state(dc, cpu_T[2]);
  3074 + gen_op_tsub_ccTV(cpu_T[0], cpu_T[0], cpu_T[1]);
3094 gen_movl_TN_reg(rd, cpu_T[0]); 3075 gen_movl_TN_reg(rd, cpu_T[0]);
3095 break; 3076 break;
3096 case 0x24: /* mulscc */ 3077 case 0x24: /* mulscc */
3097 - gen_op_mulscc_T1_T0(); 3078 + gen_op_mulscc(cpu_T[0], cpu_T[0], cpu_T[1]);
3098 gen_movl_TN_reg(rd, cpu_T[0]); 3079 gen_movl_TN_reg(rd, cpu_T[0]);
3099 break; 3080 break;
3100 #ifndef TARGET_SPARC64 3081 #ifndef TARGET_SPARC64
@@ -3145,7 +3126,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3145,7 +3126,7 @@ static void disas_sparc_insn(DisasContext * dc)
3145 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 3126 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3146 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]); 3127 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
3147 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs)); 3128 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
3148 - save_state(dc); 3129 + save_state(dc, cpu_T[2]);
3149 gen_op_next_insn(); 3130 gen_op_next_insn();
3150 tcg_gen_exit_tb(0); 3131 tcg_gen_exit_tb(0);
3151 dc->is_br = 1; 3132 dc->is_br = 1;
@@ -3157,7 +3138,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3157,7 +3138,7 @@ static void disas_sparc_insn(DisasContext * dc)
3157 #endif 3138 #endif
3158 break; 3139 break;
3159 case 0x13: /* Graphics Status */ 3140 case 0x13: /* Graphics Status */
3160 - if (gen_trap_ifnofpu(dc)) 3141 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
3161 goto jmp_insn; 3142 goto jmp_insn;
3162 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 3143 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3163 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, gsr)); 3144 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, gsr));
@@ -3257,7 +3238,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3257,7 +3238,7 @@ static void disas_sparc_insn(DisasContext * dc)
3257 #else 3238 #else
3258 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]); 3239 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3259 tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]); 3240 tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]);
3260 - save_state(dc); 3241 + save_state(dc, cpu_T[2]);
3261 gen_op_next_insn(); 3242 gen_op_next_insn();
3262 tcg_gen_exit_tb(0); 3243 tcg_gen_exit_tb(0);
3263 dc->is_br = 1; 3244 dc->is_br = 1;
@@ -3335,7 +3316,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3335,7 +3316,7 @@ static void disas_sparc_insn(DisasContext * dc)
3335 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, tbr)); 3316 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, tbr));
3336 break; 3317 break;
3337 case 6: // pstate 3318 case 6: // pstate
3338 - save_state(dc); 3319 + save_state(dc, cpu_T[2]);
3339 tcg_gen_helper_0_1(helper_wrpstate, cpu_T[0]); 3320 tcg_gen_helper_0_1(helper_wrpstate, cpu_T[0]);
3340 gen_op_next_insn(); 3321 gen_op_next_insn();
3341 tcg_gen_exit_tb(0); 3322 tcg_gen_exit_tb(0);
@@ -3406,7 +3387,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3406,7 +3387,7 @@ static void disas_sparc_insn(DisasContext * dc)
3406 switch (rd) { 3387 switch (rd) {
3407 case 0: // hpstate 3388 case 0: // hpstate
3408 // XXX gen_op_wrhpstate(); 3389 // XXX gen_op_wrhpstate();
3409 - save_state(dc); 3390 + save_state(dc, cpu_T[2]);
3410 gen_op_next_insn(); 3391 gen_op_next_insn();
3411 tcg_gen_exit_tb(0); 3392 tcg_gen_exit_tb(0);
3412 dc->is_br = 1; 3393 dc->is_br = 1;
@@ -3481,7 +3462,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3481,7 +3462,7 @@ static void disas_sparc_insn(DisasContext * dc)
3481 break; 3462 break;
3482 } 3463 }
3483 case 0x2d: /* V9 sdivx */ 3464 case 0x2d: /* V9 sdivx */
3484 - gen_op_sdivx_T1_T0(); 3465 + gen_op_sdivx(cpu_T[0], cpu_T[0], cpu_T[1]);
3485 gen_movl_TN_reg(rd, cpu_T[0]); 3466 gen_movl_TN_reg(rd, cpu_T[0]);
3486 break; 3467 break;
3487 case 0x2e: /* V9 popc */ 3468 case 0x2e: /* V9 popc */
@@ -3532,7 +3513,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3532,7 +3513,7 @@ static void disas_sparc_insn(DisasContext * dc)
3532 int opf = GET_FIELD_SP(insn, 5, 13); 3513 int opf = GET_FIELD_SP(insn, 5, 13);
3533 rs1 = GET_FIELD(insn, 13, 17); 3514 rs1 = GET_FIELD(insn, 13, 17);
3534 rs2 = GET_FIELD(insn, 27, 31); 3515 rs2 = GET_FIELD(insn, 27, 31);
3535 - if (gen_trap_ifnofpu(dc)) 3516 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
3536 goto jmp_insn; 3517 goto jmp_insn;
3537 3518
3538 switch (opf) { 3519 switch (opf) {
@@ -3940,7 +3921,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3940,7 +3921,7 @@ static void disas_sparc_insn(DisasContext * dc)
3940 #ifdef TARGET_SPARC64 3921 #ifdef TARGET_SPARC64
3941 } else if (xop == 0x39) { /* V9 return */ 3922 } else if (xop == 0x39) { /* V9 return */
3942 rs1 = GET_FIELD(insn, 13, 17); 3923 rs1 = GET_FIELD(insn, 13, 17);
3943 - save_state(dc); 3924 + save_state(dc, cpu_T[2]);
3944 gen_movl_reg_TN(rs1, cpu_T[0]); 3925 gen_movl_reg_TN(rs1, cpu_T[0]);
3945 if (IS_IMM) { /* immediate */ 3926 if (IS_IMM) { /* immediate */
3946 rs2 = GET_FIELDs(insn, 19, 31); 3927 rs2 = GET_FIELDs(insn, 19, 31);
@@ -3957,8 +3938,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3957,8 +3938,8 @@ static void disas_sparc_insn(DisasContext * dc)
3957 #endif 3938 #endif
3958 } 3939 }
3959 tcg_gen_helper_0_0(helper_restore); 3940 tcg_gen_helper_0_0(helper_restore);
3960 - gen_mov_pc_npc(dc);  
3961 - gen_op_check_align_T0_3(); 3941 + gen_mov_pc_npc(dc, cpu_T[2]);
  3942 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
3962 tcg_gen_mov_tl(cpu_npc, cpu_T[0]); 3943 tcg_gen_mov_tl(cpu_npc, cpu_T[0]);
3963 dc->npc = DYNAMIC_PC; 3944 dc->npc = DYNAMIC_PC;
3964 goto jmp_insn; 3945 goto jmp_insn;
@@ -3987,8 +3968,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3987,8 +3968,8 @@ static void disas_sparc_insn(DisasContext * dc)
3987 tcg_gen_movi_tl(cpu_T[1], dc->pc); 3968 tcg_gen_movi_tl(cpu_T[1], dc->pc);
3988 gen_movl_TN_reg(rd, cpu_T[1]); 3969 gen_movl_TN_reg(rd, cpu_T[1]);
3989 } 3970 }
3990 - gen_mov_pc_npc(dc);  
3991 - gen_op_check_align_T0_3(); 3971 + gen_mov_pc_npc(dc, cpu_T[2]);
  3972 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
3992 tcg_gen_mov_tl(cpu_npc, cpu_T[0]); 3973 tcg_gen_mov_tl(cpu_npc, cpu_T[0]);
3993 dc->npc = DYNAMIC_PC; 3974 dc->npc = DYNAMIC_PC;
3994 } 3975 }
@@ -3998,8 +3979,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -3998,8 +3979,8 @@ static void disas_sparc_insn(DisasContext * dc)
3998 { 3979 {
3999 if (!supervisor(dc)) 3980 if (!supervisor(dc))
4000 goto priv_insn; 3981 goto priv_insn;
4001 - gen_mov_pc_npc(dc);  
4002 - gen_op_check_align_T0_3(); 3982 + gen_mov_pc_npc(dc, cpu_T[2]);
  3983 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4003 tcg_gen_mov_tl(cpu_npc, cpu_T[0]); 3984 tcg_gen_mov_tl(cpu_npc, cpu_T[0]);
4004 dc->npc = DYNAMIC_PC; 3985 dc->npc = DYNAMIC_PC;
4005 tcg_gen_helper_0_0(helper_rett); 3986 tcg_gen_helper_0_0(helper_rett);
@@ -4010,12 +3991,12 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4010,12 +3991,12 @@ static void disas_sparc_insn(DisasContext * dc)
4010 tcg_gen_helper_0_1(helper_flush, cpu_T[0]); 3991 tcg_gen_helper_0_1(helper_flush, cpu_T[0]);
4011 break; 3992 break;
4012 case 0x3c: /* save */ 3993 case 0x3c: /* save */
4013 - save_state(dc); 3994 + save_state(dc, cpu_T[2]);
4014 tcg_gen_helper_0_0(helper_save); 3995 tcg_gen_helper_0_0(helper_save);
4015 gen_movl_TN_reg(rd, cpu_T[0]); 3996 gen_movl_TN_reg(rd, cpu_T[0]);
4016 break; 3997 break;
4017 case 0x3d: /* restore */ 3998 case 0x3d: /* restore */
4018 - save_state(dc); 3999 + save_state(dc, cpu_T[2]);
4019 tcg_gen_helper_0_0(helper_restore); 4000 tcg_gen_helper_0_0(helper_restore);
4020 gen_movl_TN_reg(rd, cpu_T[0]); 4001 gen_movl_TN_reg(rd, cpu_T[0]);
4021 break; 4002 break;
@@ -4054,7 +4035,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4054,7 +4035,7 @@ static void disas_sparc_insn(DisasContext * dc)
4054 { 4035 {
4055 unsigned int xop = GET_FIELD(insn, 7, 12); 4036 unsigned int xop = GET_FIELD(insn, 7, 12);
4056 rs1 = GET_FIELD(insn, 13, 17); 4037 rs1 = GET_FIELD(insn, 13, 17);
4057 - save_state(dc); 4038 + save_state(dc, cpu_T[2]);
4058 gen_movl_reg_TN(rs1, cpu_T[0]); 4039 gen_movl_reg_TN(rs1, cpu_T[0]);
4059 if (xop == 0x3c || xop == 0x3e) 4040 if (xop == 0x3c || xop == 0x3e)
4060 { 4041 {
@@ -4080,7 +4061,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4080,7 +4061,7 @@ static void disas_sparc_insn(DisasContext * dc)
4080 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) { 4061 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4081 switch (xop) { 4062 switch (xop) {
4082 case 0x0: /* load unsigned word */ 4063 case 0x0: /* load unsigned word */
4083 - gen_op_check_align_T0_3(); 4064 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4084 ABI32_MASK(cpu_T[0]); 4065 ABI32_MASK(cpu_T[0]);
4085 tcg_gen_qemu_ld32u(cpu_T[1], cpu_T[0], dc->mem_idx); 4066 tcg_gen_qemu_ld32u(cpu_T[1], cpu_T[0], dc->mem_idx);
4086 break; 4067 break;
@@ -4089,7 +4070,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4089,7 +4070,7 @@ static void disas_sparc_insn(DisasContext * dc)
4089 tcg_gen_qemu_ld8u(cpu_T[1], cpu_T[0], dc->mem_idx); 4070 tcg_gen_qemu_ld8u(cpu_T[1], cpu_T[0], dc->mem_idx);
4090 break; 4071 break;
4091 case 0x2: /* load unsigned halfword */ 4072 case 0x2: /* load unsigned halfword */
4092 - gen_op_check_align_T0_1(); 4073 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(1));
4093 ABI32_MASK(cpu_T[0]); 4074 ABI32_MASK(cpu_T[0]);
4094 tcg_gen_qemu_ld16u(cpu_T[1], cpu_T[0], dc->mem_idx); 4075 tcg_gen_qemu_ld16u(cpu_T[1], cpu_T[0], dc->mem_idx);
4095 break; 4076 break;
@@ -4097,7 +4078,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4097,7 +4078,7 @@ static void disas_sparc_insn(DisasContext * dc)
4097 if (rd & 1) 4078 if (rd & 1)
4098 goto illegal_insn; 4079 goto illegal_insn;
4099 else { 4080 else {
4100 - gen_op_check_align_T0_7(); 4081 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
4101 ABI32_MASK(cpu_T[0]); 4082 ABI32_MASK(cpu_T[0]);
4102 tcg_gen_qemu_ld64(cpu_tmp64, cpu_T[0], dc->mem_idx); 4083 tcg_gen_qemu_ld64(cpu_tmp64, cpu_T[0], dc->mem_idx);
4103 tcg_gen_trunc_i64_tl(cpu_T[0], cpu_tmp64); 4084 tcg_gen_trunc_i64_tl(cpu_T[0], cpu_tmp64);
@@ -4113,7 +4094,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4113,7 +4094,7 @@ static void disas_sparc_insn(DisasContext * dc)
4113 tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx); 4094 tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
4114 break; 4095 break;
4115 case 0xa: /* load signed halfword */ 4096 case 0xa: /* load signed halfword */
4116 - gen_op_check_align_T0_1(); 4097 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(1));
4117 ABI32_MASK(cpu_T[0]); 4098 ABI32_MASK(cpu_T[0]);
4118 tcg_gen_qemu_ld16s(cpu_T[1], cpu_T[0], dc->mem_idx); 4099 tcg_gen_qemu_ld16s(cpu_T[1], cpu_T[0], dc->mem_idx);
4119 break; 4100 break;
@@ -4123,7 +4104,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4123,7 +4104,7 @@ static void disas_sparc_insn(DisasContext * dc)
4123 tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_T[0], dc->mem_idx); 4104 tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_T[0], dc->mem_idx);
4124 break; 4105 break;
4125 case 0x0f: /* swap register with memory. Also atomically */ 4106 case 0x0f: /* swap register with memory. Also atomically */
4126 - gen_op_check_align_T0_3(); 4107 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4127 gen_movl_reg_TN(rd, cpu_T[1]); 4108 gen_movl_reg_TN(rd, cpu_T[1]);
4128 ABI32_MASK(cpu_T[0]); 4109 ABI32_MASK(cpu_T[0]);
4129 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx); 4110 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
@@ -4138,8 +4119,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4138,8 +4119,8 @@ static void disas_sparc_insn(DisasContext * dc)
4138 if (!supervisor(dc)) 4119 if (!supervisor(dc))
4139 goto priv_insn; 4120 goto priv_insn;
4140 #endif 4121 #endif
4141 - gen_op_check_align_T0_3();  
4142 - gen_ld_asi(insn, 4, 0); 4122 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
  4123 + gen_ld_asi(cpu_T[1], cpu_T[0], insn, 4, 0);
4143 break; 4124 break;
4144 case 0x11: /* load unsigned byte alternate */ 4125 case 0x11: /* load unsigned byte alternate */
4145 #ifndef TARGET_SPARC64 4126 #ifndef TARGET_SPARC64
@@ -4148,7 +4129,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4148,7 +4129,7 @@ static void disas_sparc_insn(DisasContext * dc)
4148 if (!supervisor(dc)) 4129 if (!supervisor(dc))
4149 goto priv_insn; 4130 goto priv_insn;
4150 #endif 4131 #endif
4151 - gen_ld_asi(insn, 1, 0); 4132 + gen_ld_asi(cpu_T[1], cpu_T[0], insn, 1, 0);
4152 break; 4133 break;
4153 case 0x12: /* load unsigned halfword alternate */ 4134 case 0x12: /* load unsigned halfword alternate */
4154 #ifndef TARGET_SPARC64 4135 #ifndef TARGET_SPARC64
@@ -4157,8 +4138,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4157,8 +4138,8 @@ static void disas_sparc_insn(DisasContext * dc)
4157 if (!supervisor(dc)) 4138 if (!supervisor(dc))
4158 goto priv_insn; 4139 goto priv_insn;
4159 #endif 4140 #endif
4160 - gen_op_check_align_T0_1();  
4161 - gen_ld_asi(insn, 2, 0); 4141 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(1));
  4142 + gen_ld_asi(cpu_T[1], cpu_T[0], insn, 2, 0);
4162 break; 4143 break;
4163 case 0x13: /* load double word alternate */ 4144 case 0x13: /* load double word alternate */
4164 #ifndef TARGET_SPARC64 4145 #ifndef TARGET_SPARC64
@@ -4169,8 +4150,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4169,8 +4150,8 @@ static void disas_sparc_insn(DisasContext * dc)
4169 #endif 4150 #endif
4170 if (rd & 1) 4151 if (rd & 1)
4171 goto illegal_insn; 4152 goto illegal_insn;
4172 - gen_op_check_align_T0_7();  
4173 - gen_ldda_asi(insn); 4153 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
  4154 + gen_ldda_asi(cpu_T[0], cpu_T[1], cpu_T[0], insn);
4174 gen_movl_TN_reg(rd + 1, cpu_T[0]); 4155 gen_movl_TN_reg(rd + 1, cpu_T[0]);
4175 break; 4156 break;
4176 case 0x19: /* load signed byte alternate */ 4157 case 0x19: /* load signed byte alternate */
@@ -4180,7 +4161,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4180,7 +4161,7 @@ static void disas_sparc_insn(DisasContext * dc)
4180 if (!supervisor(dc)) 4161 if (!supervisor(dc))
4181 goto priv_insn; 4162 goto priv_insn;
4182 #endif 4163 #endif
4183 - gen_ld_asi(insn, 1, 1); 4164 + gen_ld_asi(cpu_T[1], cpu_T[0], insn, 1, 1);
4184 break; 4165 break;
4185 case 0x1a: /* load signed halfword alternate */ 4166 case 0x1a: /* load signed halfword alternate */
4186 #ifndef TARGET_SPARC64 4167 #ifndef TARGET_SPARC64
@@ -4189,8 +4170,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4189,8 +4170,8 @@ static void disas_sparc_insn(DisasContext * dc)
4189 if (!supervisor(dc)) 4170 if (!supervisor(dc))
4190 goto priv_insn; 4171 goto priv_insn;
4191 #endif 4172 #endif
4192 - gen_op_check_align_T0_1();  
4193 - gen_ld_asi(insn, 2, 1); 4173 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(1));
  4174 + gen_ld_asi(cpu_T[1], cpu_T[0], insn, 2, 1);
4194 break; 4175 break;
4195 case 0x1d: /* ldstuba -- XXX: should be atomically */ 4176 case 0x1d: /* ldstuba -- XXX: should be atomically */
4196 #ifndef TARGET_SPARC64 4177 #ifndef TARGET_SPARC64
@@ -4199,7 +4180,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4199,7 +4180,7 @@ static void disas_sparc_insn(DisasContext * dc)
4199 if (!supervisor(dc)) 4180 if (!supervisor(dc))
4200 goto priv_insn; 4181 goto priv_insn;
4201 #endif 4182 #endif
4202 - gen_ldstub_asi(insn); 4183 + gen_ldstub_asi(cpu_T[1], cpu_T[0], insn);
4203 break; 4184 break;
4204 case 0x1f: /* swap reg with alt. memory. Also atomically */ 4185 case 0x1f: /* swap reg with alt. memory. Also atomically */
4205 #ifndef TARGET_SPARC64 4186 #ifndef TARGET_SPARC64
@@ -4208,9 +4189,9 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4208,9 +4189,9 @@ static void disas_sparc_insn(DisasContext * dc)
4208 if (!supervisor(dc)) 4189 if (!supervisor(dc))
4209 goto priv_insn; 4190 goto priv_insn;
4210 #endif 4191 #endif
4211 - gen_op_check_align_T0_3(); 4192 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4212 gen_movl_reg_TN(rd, cpu_T[1]); 4193 gen_movl_reg_TN(rd, cpu_T[1]);
4213 - gen_swap_asi(insn); 4194 + gen_swap_asi(cpu_T[1], cpu_T[0], insn);
4214 break; 4195 break;
4215 4196
4216 #ifndef TARGET_SPARC64 4197 #ifndef TARGET_SPARC64
@@ -4222,39 +4203,39 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4222,39 +4203,39 @@ static void disas_sparc_insn(DisasContext * dc)
4222 #endif 4203 #endif
4223 #ifdef TARGET_SPARC64 4204 #ifdef TARGET_SPARC64
4224 case 0x08: /* V9 ldsw */ 4205 case 0x08: /* V9 ldsw */
4225 - gen_op_check_align_T0_3(); 4206 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4226 ABI32_MASK(cpu_T[0]); 4207 ABI32_MASK(cpu_T[0]);
4227 tcg_gen_qemu_ld32s(cpu_T[1], cpu_T[0], dc->mem_idx); 4208 tcg_gen_qemu_ld32s(cpu_T[1], cpu_T[0], dc->mem_idx);
4228 break; 4209 break;
4229 case 0x0b: /* V9 ldx */ 4210 case 0x0b: /* V9 ldx */
4230 - gen_op_check_align_T0_7(); 4211 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
4231 ABI32_MASK(cpu_T[0]); 4212 ABI32_MASK(cpu_T[0]);
4232 tcg_gen_qemu_ld64(cpu_T[1], cpu_T[0], dc->mem_idx); 4213 tcg_gen_qemu_ld64(cpu_T[1], cpu_T[0], dc->mem_idx);
4233 break; 4214 break;
4234 case 0x18: /* V9 ldswa */ 4215 case 0x18: /* V9 ldswa */
4235 - gen_op_check_align_T0_3();  
4236 - gen_ld_asi(insn, 4, 1); 4216 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
  4217 + gen_ld_asi(cpu_T[1], cpu_T[0], insn, 4, 1);
4237 break; 4218 break;
4238 case 0x1b: /* V9 ldxa */ 4219 case 0x1b: /* V9 ldxa */
4239 - gen_op_check_align_T0_7();  
4240 - gen_ld_asi(insn, 8, 0); 4220 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
  4221 + gen_ld_asi(cpu_T[1], cpu_T[0], insn, 8, 0);
4241 break; 4222 break;
4242 case 0x2d: /* V9 prefetch, no effect */ 4223 case 0x2d: /* V9 prefetch, no effect */
4243 goto skip_move; 4224 goto skip_move;
4244 case 0x30: /* V9 ldfa */ 4225 case 0x30: /* V9 ldfa */
4245 - gen_op_check_align_T0_3();  
4246 - gen_ldf_asi(insn, 4, rd); 4226 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
  4227 + gen_ldf_asi(cpu_T[0], insn, 4, rd);
4247 goto skip_move; 4228 goto skip_move;
4248 case 0x33: /* V9 lddfa */ 4229 case 0x33: /* V9 lddfa */
4249 - gen_op_check_align_T0_3();  
4250 - gen_ldf_asi(insn, 8, DFPREG(rd)); 4230 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
  4231 + gen_ldf_asi(cpu_T[0], insn, 8, DFPREG(rd));
4251 goto skip_move; 4232 goto skip_move;
4252 case 0x3d: /* V9 prefetcha, no effect */ 4233 case 0x3d: /* V9 prefetcha, no effect */
4253 goto skip_move; 4234 goto skip_move;
4254 case 0x32: /* V9 ldqfa */ 4235 case 0x32: /* V9 ldqfa */
4255 #if defined(CONFIG_USER_ONLY) 4236 #if defined(CONFIG_USER_ONLY)
4256 - gen_op_check_align_T0_3();  
4257 - gen_ldf_asi(insn, 16, QFPREG(rd)); 4237 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
  4238 + gen_ldf_asi(cpu_T[0], insn, 16, QFPREG(rd));
4258 goto skip_move; 4239 goto skip_move;
4259 #else 4240 #else
4260 goto nfpu_insn; 4241 goto nfpu_insn;
@@ -4268,17 +4249,17 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4268,17 +4249,17 @@ static void disas_sparc_insn(DisasContext * dc)
4268 skip_move: ; 4249 skip_move: ;
4269 #endif 4250 #endif
4270 } else if (xop >= 0x20 && xop < 0x24) { 4251 } else if (xop >= 0x20 && xop < 0x24) {
4271 - if (gen_trap_ifnofpu(dc)) 4252 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
4272 goto jmp_insn; 4253 goto jmp_insn;
4273 switch (xop) { 4254 switch (xop) {
4274 case 0x20: /* load fpreg */ 4255 case 0x20: /* load fpreg */
4275 - gen_op_check_align_T0_3(); 4256 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4276 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx); 4257 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
4277 tcg_gen_st_i32(cpu_tmp32, cpu_env, 4258 tcg_gen_st_i32(cpu_tmp32, cpu_env,
4278 offsetof(CPUState, fpr[rd])); 4259 offsetof(CPUState, fpr[rd]));
4279 break; 4260 break;
4280 case 0x21: /* load fsr */ 4261 case 0x21: /* load fsr */
4281 - gen_op_check_align_T0_3(); 4262 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4282 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx); 4263 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
4283 tcg_gen_st_i32(cpu_tmp32, cpu_env, 4264 tcg_gen_st_i32(cpu_tmp32, cpu_env,
4284 offsetof(CPUState, ft0)); 4265 offsetof(CPUState, ft0));
@@ -4286,7 +4267,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4286,7 +4267,7 @@ static void disas_sparc_insn(DisasContext * dc)
4286 break; 4267 break;
4287 case 0x22: /* load quad fpreg */ 4268 case 0x22: /* load quad fpreg */
4288 #if defined(CONFIG_USER_ONLY) 4269 #if defined(CONFIG_USER_ONLY)
4289 - gen_op_check_align_T0_7(); 4270 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
4290 gen_op_ldst(ldqf); 4271 gen_op_ldst(ldqf);
4291 gen_op_store_QT0_fpr(QFPREG(rd)); 4272 gen_op_store_QT0_fpr(QFPREG(rd));
4292 break; 4273 break;
@@ -4294,7 +4275,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4294,7 +4275,7 @@ static void disas_sparc_insn(DisasContext * dc)
4294 goto nfpu_insn; 4275 goto nfpu_insn;
4295 #endif 4276 #endif
4296 case 0x23: /* load double fpreg */ 4277 case 0x23: /* load double fpreg */
4297 - gen_op_check_align_T0_7(); 4278 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
4298 gen_op_ldst(lddf); 4279 gen_op_ldst(lddf);
4299 gen_op_store_DT0_fpr(DFPREG(rd)); 4280 gen_op_store_DT0_fpr(DFPREG(rd));
4300 break; 4281 break;
@@ -4306,7 +4287,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4306,7 +4287,7 @@ static void disas_sparc_insn(DisasContext * dc)
4306 gen_movl_reg_TN(rd, cpu_T[1]); 4287 gen_movl_reg_TN(rd, cpu_T[1]);
4307 switch (xop) { 4288 switch (xop) {
4308 case 0x4: /* store word */ 4289 case 0x4: /* store word */
4309 - gen_op_check_align_T0_3(); 4290 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4310 ABI32_MASK(cpu_T[0]); 4291 ABI32_MASK(cpu_T[0]);
4311 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx); 4292 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
4312 break; 4293 break;
@@ -4315,7 +4296,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4315,7 +4296,7 @@ static void disas_sparc_insn(DisasContext * dc)
4315 tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], dc->mem_idx); 4296 tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], dc->mem_idx);
4316 break; 4297 break;
4317 case 0x6: /* store halfword */ 4298 case 0x6: /* store halfword */
4318 - gen_op_check_align_T0_1(); 4299 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(1));
4319 ABI32_MASK(cpu_T[0]); 4300 ABI32_MASK(cpu_T[0]);
4320 tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], dc->mem_idx); 4301 tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], dc->mem_idx);
4321 break; 4302 break;
@@ -4326,7 +4307,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4326,7 +4307,7 @@ static void disas_sparc_insn(DisasContext * dc)
4326 else { 4307 else {
4327 TCGv r_low; 4308 TCGv r_low;
4328 4309
4329 - gen_op_check_align_T0_7(); 4310 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
4330 r_low = tcg_temp_new(TCG_TYPE_I32); 4311 r_low = tcg_temp_new(TCG_TYPE_I32);
4331 gen_movl_reg_TN(rd + 1, r_low); 4312 gen_movl_reg_TN(rd + 1, r_low);
4332 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_T[1], 4313 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_T[1],
@@ -4334,8 +4315,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4334,8 +4315,8 @@ static void disas_sparc_insn(DisasContext * dc)
4334 tcg_gen_qemu_st64(cpu_tmp64, cpu_T[0], dc->mem_idx); 4315 tcg_gen_qemu_st64(cpu_tmp64, cpu_T[0], dc->mem_idx);
4335 } 4316 }
4336 #else /* __i386__ */ 4317 #else /* __i386__ */
4337 - gen_op_check_align_T0_7();  
4338 - flush_T2(dc); 4318 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
  4319 + flush_cond(dc, cpu_T[2]);
4339 gen_movl_reg_TN(rd + 1, cpu_T[2]); 4320 gen_movl_reg_TN(rd + 1, cpu_T[2]);
4340 gen_op_ldst(std); 4321 gen_op_ldst(std);
4341 #endif /* __i386__ */ 4322 #endif /* __i386__ */
@@ -4348,8 +4329,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4348,8 +4329,8 @@ static void disas_sparc_insn(DisasContext * dc)
4348 if (!supervisor(dc)) 4329 if (!supervisor(dc))
4349 goto priv_insn; 4330 goto priv_insn;
4350 #endif 4331 #endif
4351 - gen_op_check_align_T0_3();  
4352 - gen_st_asi(insn, 4); 4332 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
  4333 + gen_st_asi(cpu_T[1], cpu_T[0], insn, 4);
4353 break; 4334 break;
4354 case 0x15: /* store byte alternate */ 4335 case 0x15: /* store byte alternate */
4355 #ifndef TARGET_SPARC64 4336 #ifndef TARGET_SPARC64
@@ -4358,7 +4339,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4358,7 +4339,7 @@ static void disas_sparc_insn(DisasContext * dc)
4358 if (!supervisor(dc)) 4339 if (!supervisor(dc))
4359 goto priv_insn; 4340 goto priv_insn;
4360 #endif 4341 #endif
4361 - gen_st_asi(insn, 1); 4342 + gen_st_asi(cpu_T[1], cpu_T[0], insn, 1);
4362 break; 4343 break;
4363 case 0x16: /* store halfword alternate */ 4344 case 0x16: /* store halfword alternate */
4364 #ifndef TARGET_SPARC64 4345 #ifndef TARGET_SPARC64
@@ -4367,8 +4348,8 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4367,8 +4348,8 @@ static void disas_sparc_insn(DisasContext * dc)
4367 if (!supervisor(dc)) 4348 if (!supervisor(dc))
4368 goto priv_insn; 4349 goto priv_insn;
4369 #endif 4350 #endif
4370 - gen_op_check_align_T0_1();  
4371 - gen_st_asi(insn, 2); 4351 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(1));
  4352 + gen_st_asi(cpu_T[1], cpu_T[0], insn, 2);
4372 break; 4353 break;
4373 case 0x17: /* store double word alternate */ 4354 case 0x17: /* store double word alternate */
4374 #ifndef TARGET_SPARC64 4355 #ifndef TARGET_SPARC64
@@ -4380,38 +4361,38 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4380,38 +4361,38 @@ static void disas_sparc_insn(DisasContext * dc)
4380 if (rd & 1) 4361 if (rd & 1)
4381 goto illegal_insn; 4362 goto illegal_insn;
4382 else { 4363 else {
4383 - gen_op_check_align_T0_7();  
4384 - gen_stda_asi(insn, rd); 4364 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
  4365 + gen_stda_asi(cpu_T[1], cpu_T[0], insn, rd);
4385 } 4366 }
4386 break; 4367 break;
4387 #endif 4368 #endif
4388 #ifdef TARGET_SPARC64 4369 #ifdef TARGET_SPARC64
4389 case 0x0e: /* V9 stx */ 4370 case 0x0e: /* V9 stx */
4390 - gen_op_check_align_T0_7(); 4371 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
4391 ABI32_MASK(cpu_T[0]); 4372 ABI32_MASK(cpu_T[0]);
4392 tcg_gen_qemu_st64(cpu_T[1], cpu_T[0], dc->mem_idx); 4373 tcg_gen_qemu_st64(cpu_T[1], cpu_T[0], dc->mem_idx);
4393 break; 4374 break;
4394 case 0x1e: /* V9 stxa */ 4375 case 0x1e: /* V9 stxa */
4395 - gen_op_check_align_T0_7();  
4396 - gen_st_asi(insn, 8); 4376 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
  4377 + gen_st_asi(cpu_T[1], cpu_T[0], insn, 8);
4397 break; 4378 break;
4398 #endif 4379 #endif
4399 default: 4380 default:
4400 goto illegal_insn; 4381 goto illegal_insn;
4401 } 4382 }
4402 } else if (xop > 0x23 && xop < 0x28) { 4383 } else if (xop > 0x23 && xop < 0x28) {
4403 - if (gen_trap_ifnofpu(dc)) 4384 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
4404 goto jmp_insn; 4385 goto jmp_insn;
4405 switch (xop) { 4386 switch (xop) {
4406 case 0x24: /* store fpreg */ 4387 case 0x24: /* store fpreg */
4407 - gen_op_check_align_T0_3(); 4388 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4408 tcg_gen_ld_i32(cpu_tmp32, cpu_env, 4389 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4409 offsetof(CPUState, fpr[rd])); 4390 offsetof(CPUState, fpr[rd]));
4410 tcg_gen_qemu_st32(cpu_tmp32, cpu_T[0], dc->mem_idx); 4391 tcg_gen_qemu_st32(cpu_tmp32, cpu_T[0], dc->mem_idx);
4411 break; 4392 break;
4412 case 0x25: /* stfsr, V9 stxfsr */ 4393 case 0x25: /* stfsr, V9 stxfsr */
4413 #ifdef CONFIG_USER_ONLY 4394 #ifdef CONFIG_USER_ONLY
4414 - gen_op_check_align_T0_3(); 4395 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4415 #endif 4396 #endif
4416 tcg_gen_helper_0_0(helper_stfsr); 4397 tcg_gen_helper_0_0(helper_stfsr);
4417 tcg_gen_ld_i32(cpu_tmp32, cpu_env, 4398 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
@@ -4422,7 +4403,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4422,7 +4403,7 @@ static void disas_sparc_insn(DisasContext * dc)
4422 #ifdef TARGET_SPARC64 4403 #ifdef TARGET_SPARC64
4423 #if defined(CONFIG_USER_ONLY) 4404 #if defined(CONFIG_USER_ONLY)
4424 /* V9 stqf, store quad fpreg */ 4405 /* V9 stqf, store quad fpreg */
4425 - gen_op_check_align_T0_7(); 4406 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
4426 gen_op_load_fpr_QT0(QFPREG(rd)); 4407 gen_op_load_fpr_QT0(QFPREG(rd));
4427 gen_op_ldst(stqf); 4408 gen_op_ldst(stqf);
4428 break; 4409 break;
@@ -4436,13 +4417,13 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4436,13 +4417,13 @@ static void disas_sparc_insn(DisasContext * dc)
4436 #else 4417 #else
4437 if (!supervisor(dc)) 4418 if (!supervisor(dc))
4438 goto priv_insn; 4419 goto priv_insn;
4439 - if (gen_trap_ifnofpu(dc)) 4420 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
4440 goto jmp_insn; 4421 goto jmp_insn;
4441 goto nfq_insn; 4422 goto nfq_insn;
4442 #endif 4423 #endif
4443 #endif 4424 #endif
4444 case 0x27: 4425 case 0x27:
4445 - gen_op_check_align_T0_7(); 4426 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
4446 gen_op_load_fpr_DT0(DFPREG(rd)); 4427 gen_op_load_fpr_DT0(DFPREG(rd));
4447 gen_op_ldst(stdf); 4428 gen_op_ldst(stdf);
4448 break; 4429 break;
@@ -4453,32 +4434,32 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4453,32 +4434,32 @@ static void disas_sparc_insn(DisasContext * dc)
4453 switch (xop) { 4434 switch (xop) {
4454 #ifdef TARGET_SPARC64 4435 #ifdef TARGET_SPARC64
4455 case 0x34: /* V9 stfa */ 4436 case 0x34: /* V9 stfa */
4456 - gen_op_check_align_T0_3(); 4437 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4457 gen_op_load_fpr_FT0(rd); 4438 gen_op_load_fpr_FT0(rd);
4458 - gen_stf_asi(insn, 4, rd); 4439 + gen_stf_asi(cpu_T[0], insn, 4, rd);
4459 break; 4440 break;
4460 case 0x36: /* V9 stqfa */ 4441 case 0x36: /* V9 stqfa */
4461 #if defined(CONFIG_USER_ONLY) 4442 #if defined(CONFIG_USER_ONLY)
4462 - gen_op_check_align_T0_7(); 4443 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
4463 gen_op_load_fpr_QT0(QFPREG(rd)); 4444 gen_op_load_fpr_QT0(QFPREG(rd));
4464 - gen_stf_asi(insn, 16, QFPREG(rd)); 4445 + gen_stf_asi(cpu_T[0], insn, 16, QFPREG(rd));
4465 break; 4446 break;
4466 #else 4447 #else
4467 goto nfpu_insn; 4448 goto nfpu_insn;
4468 #endif 4449 #endif
4469 case 0x37: /* V9 stdfa */ 4450 case 0x37: /* V9 stdfa */
4470 - gen_op_check_align_T0_3(); 4451 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4471 gen_op_load_fpr_DT0(DFPREG(rd)); 4452 gen_op_load_fpr_DT0(DFPREG(rd));
4472 - gen_stf_asi(insn, 8, DFPREG(rd)); 4453 + gen_stf_asi(cpu_T[0], insn, 8, DFPREG(rd));
4473 break; 4454 break;
4474 case 0x3c: /* V9 casa */ 4455 case 0x3c: /* V9 casa */
4475 - gen_op_check_align_T0_3();  
4476 - gen_cas_asi(insn, rd); 4456 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
  4457 + gen_cas_asi(cpu_T[1], cpu_T[0], cpu_T[1], insn, rd);
4477 gen_movl_TN_reg(rd, cpu_T[1]); 4458 gen_movl_TN_reg(rd, cpu_T[1]);
4478 break; 4459 break;
4479 case 0x3e: /* V9 casxa */ 4460 case 0x3e: /* V9 casxa */
4480 - gen_op_check_align_T0_7();  
4481 - gen_casx_asi(insn, rd); 4461 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
  4462 + gen_casx_asi(cpu_T[1], cpu_T[0], cpu_T[1], insn, rd);
4482 gen_movl_TN_reg(rd, cpu_T[1]); 4463 gen_movl_TN_reg(rd, cpu_T[1]);
4483 break; 4464 break;
4484 #else 4465 #else
@@ -4512,24 +4493,24 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4512,24 +4493,24 @@ static void disas_sparc_insn(DisasContext * dc)
4512 jmp_insn: 4493 jmp_insn:
4513 return; 4494 return;
4514 illegal_insn: 4495 illegal_insn:
4515 - save_state(dc); 4496 + save_state(dc, cpu_T[2]);
4516 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_ILL_INSN)); 4497 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_ILL_INSN));
4517 dc->is_br = 1; 4498 dc->is_br = 1;
4518 return; 4499 return;
4519 #if !defined(CONFIG_USER_ONLY) 4500 #if !defined(CONFIG_USER_ONLY)
4520 priv_insn: 4501 priv_insn:
4521 - save_state(dc); 4502 + save_state(dc, cpu_T[2]);
4522 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_PRIV_INSN)); 4503 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_PRIV_INSN));
4523 dc->is_br = 1; 4504 dc->is_br = 1;
4524 return; 4505 return;
4525 nfpu_insn: 4506 nfpu_insn:
4526 - save_state(dc); 4507 + save_state(dc, cpu_T[2]);
4527 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP); 4508 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4528 dc->is_br = 1; 4509 dc->is_br = 1;
4529 return; 4510 return;
4530 #ifndef TARGET_SPARC64 4511 #ifndef TARGET_SPARC64
4531 nfq_insn: 4512 nfq_insn:
4532 - save_state(dc); 4513 + save_state(dc, cpu_T[2]);
4533 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR); 4514 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4534 dc->is_br = 1; 4515 dc->is_br = 1;
4535 return; 4516 return;
@@ -4537,7 +4518,7 @@ static void disas_sparc_insn(DisasContext * dc) @@ -4537,7 +4518,7 @@ static void disas_sparc_insn(DisasContext * dc)
4537 #endif 4518 #endif
4538 #ifndef TARGET_SPARC64 4519 #ifndef TARGET_SPARC64
4539 ncp_insn: 4520 ncp_insn:
4540 - save_state(dc); 4521 + save_state(dc, cpu_T[2]);
4541 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NCP_INSN)); 4522 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NCP_INSN));
4542 dc->is_br = 1; 4523 dc->is_br = 1;
4543 return; 4524 return;
@@ -4575,7 +4556,7 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb, @@ -4575,7 +4556,7 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4575 for(j = 0; j < env->nb_breakpoints; j++) { 4556 for(j = 0; j < env->nb_breakpoints; j++) {
4576 if (env->breakpoints[j] == dc->pc) { 4557 if (env->breakpoints[j] == dc->pc) {
4577 if (dc->pc != pc_start) 4558 if (dc->pc != pc_start)
4578 - save_state(dc); 4559 + save_state(dc, cpu_T[2]);
4579 tcg_gen_helper_0_0(helper_debug); 4560 tcg_gen_helper_0_0(helper_debug);
4580 tcg_gen_exit_tb(0); 4561 tcg_gen_exit_tb(0);
4581 dc->is_br = 1; 4562 dc->is_br = 1;
@@ -4627,7 +4608,7 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb, @@ -4627,7 +4608,7 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4627 } else { 4608 } else {
4628 if (dc->pc != DYNAMIC_PC) 4609 if (dc->pc != DYNAMIC_PC)
4629 tcg_gen_movi_tl(cpu_pc, dc->pc); 4610 tcg_gen_movi_tl(cpu_pc, dc->pc);
4630 - save_npc(dc); 4611 + save_npc(dc, cpu_T[2]);
4631 tcg_gen_exit_tb(0); 4612 tcg_gen_exit_tb(0);
4632 } 4613 }
4633 } 4614 }