gwj / at91sam9263 · Commits

Commit 4af984a76a7d1b021b91027d5c4219882ea6cbdf

Authored by blueswir1
1 parent ce5b3c3d

Concentrate cpu_T[012] use to one function 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4110 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 318 additions and 337 deletions
target-sparc/translate.c
  View file @4af984a
... ... @@ -471,75 +471,75 @@ static inline void gen_tag_tv(TCGv src1, TCGv src2)
471 471 gen_set_label(l1);
472 472 }
473 473  
474   -static inline void gen_op_add_T1_T0_cc(void)
  474 +static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
475 475 {
476   - tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
477   - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  476 + tcg_gen_mov_tl(cpu_cc_src, src1);
  477 + tcg_gen_add_tl(dst, src1, src2);
478 478 gen_cc_clear_icc();
479   - gen_cc_NZ_icc(cpu_T[0]);
480   - gen_cc_C_add_icc(cpu_T[0], cpu_cc_src);
481   - gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_T[1]);
  479 + gen_cc_NZ_icc(dst);
  480 + gen_cc_C_add_icc(dst, cpu_cc_src);
  481 + gen_cc_V_add_icc(dst, cpu_cc_src, src2);
482 482 #ifdef TARGET_SPARC64
483 483 gen_cc_clear_xcc();
484   - gen_cc_NZ_xcc(cpu_T[0]);
485   - gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src);
486   - gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]);
  484 + gen_cc_NZ_xcc(dst);
  485 + gen_cc_C_add_xcc(dst, cpu_cc_src);
  486 + gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
487 487 #endif
488 488 }
489 489  
490   -static inline void gen_op_addx_T1_T0_cc(void)
  490 +static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
491 491 {
492   - tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
  492 + tcg_gen_mov_tl(cpu_cc_src, src1);
493 493 gen_mov_reg_C(cpu_tmp0, cpu_psr);
494   - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
  494 + tcg_gen_add_tl(dst, src1, cpu_tmp0);
495 495 gen_cc_clear_icc();
496   - gen_cc_C_add_icc(cpu_T[0], cpu_cc_src);
  496 + gen_cc_C_add_icc(dst, cpu_cc_src);
497 497 #ifdef TARGET_SPARC64
498 498 gen_cc_clear_xcc();
499   - gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src);
  499 + gen_cc_C_add_xcc(dst, cpu_cc_src);
500 500 #endif
501   - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
502   - gen_cc_NZ_icc(cpu_T[0]);
503   - gen_cc_C_add_icc(cpu_T[0], cpu_cc_src);
504   - gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_T[1]);
  501 + tcg_gen_add_tl(dst, dst, src2);
  502 + gen_cc_NZ_icc(dst);
  503 + gen_cc_C_add_icc(dst, cpu_cc_src);
  504 + gen_cc_V_add_icc(dst, cpu_cc_src, src2);
505 505 #ifdef TARGET_SPARC64
506   - gen_cc_NZ_xcc(cpu_T[0]);
507   - gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src);
508   - gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]);
  506 + gen_cc_NZ_xcc(dst);
  507 + gen_cc_C_add_xcc(dst, cpu_cc_src);
  508 + gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
509 509 #endif
510 510 }
511 511  
512   -static inline void gen_op_tadd_T1_T0_cc(void)
  512 +static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
513 513 {
514   - tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
515   - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  514 + tcg_gen_mov_tl(cpu_cc_src, src1);
  515 + tcg_gen_add_tl(dst, src1, src2);
516 516 gen_cc_clear_icc();
517   - gen_cc_NZ_icc(cpu_T[0]);
518   - gen_cc_C_add_icc(cpu_T[0], cpu_cc_src);
519   - gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_T[1]);
520   - gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
  517 + gen_cc_NZ_icc(dst);
  518 + gen_cc_C_add_icc(dst, cpu_cc_src);
  519 + gen_cc_V_add_icc(dst, cpu_cc_src, src2);
  520 + gen_cc_V_tag(cpu_cc_src, src2);
521 521 #ifdef TARGET_SPARC64
522 522 gen_cc_clear_xcc();
523   - gen_cc_NZ_xcc(cpu_T[0]);
524   - gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src);
525   - gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]);
  523 + gen_cc_NZ_xcc(dst);
  524 + gen_cc_C_add_xcc(dst, cpu_cc_src);
  525 + gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
526 526 #endif
527 527 }
528 528  
529   -static inline void gen_op_tadd_T1_T0_ccTV(void)
  529 +static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
530 530 {
531   - gen_tag_tv(cpu_T[0], cpu_T[1]);
532   - tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
533   - tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
534   - gen_add_tv(cpu_T[0], cpu_cc_src, cpu_T[1]);
  531 + gen_tag_tv(src1, src2);
  532 + tcg_gen_mov_tl(cpu_cc_src, src1);
  533 + tcg_gen_add_tl(dst, src1, src2);
  534 + gen_add_tv(dst, cpu_cc_src, src2);
535 535 gen_cc_clear_icc();
536   - gen_cc_NZ_icc(cpu_T[0]);
537   - gen_cc_C_add_icc(cpu_T[0], cpu_cc_src);
  536 + gen_cc_NZ_icc(dst);
  537 + gen_cc_C_add_icc(dst, cpu_cc_src);
538 538 #ifdef TARGET_SPARC64
539 539 gen_cc_clear_xcc();
540   - gen_cc_NZ_xcc(cpu_T[0]);
541   - gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src);
542   - gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]);
  540 + gen_cc_NZ_xcc(dst);
  541 + gen_cc_C_add_xcc(dst, cpu_cc_src);
  542 + gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
543 543 #endif
544 544 }
545 545  
... ... @@ -632,79 +632,79 @@ static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
632 632 tcg_gen_discard_tl(r_temp);
633 633 }
634 634  
635   -static inline void gen_op_sub_T1_T0_cc(void)
  635 +static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
636 636 {
637   - tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
638   - tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  637 + tcg_gen_mov_tl(cpu_cc_src, src1);
  638 + tcg_gen_sub_tl(dst, src1, src2);
639 639 gen_cc_clear_icc();
640   - gen_cc_NZ_icc(cpu_T[0]);
641   - gen_cc_C_sub_icc(cpu_cc_src, cpu_T[1]);
642   - gen_cc_V_sub_icc(cpu_T[0], cpu_cc_src, cpu_T[1]);
  640 + gen_cc_NZ_icc(dst);
  641 + gen_cc_C_sub_icc(cpu_cc_src, src2);
  642 + gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
643 643 #ifdef TARGET_SPARC64
644 644 gen_cc_clear_xcc();
645   - gen_cc_NZ_xcc(cpu_T[0]);
646   - gen_cc_C_sub_xcc(cpu_cc_src, cpu_T[1]);
647   - gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]);
  645 + gen_cc_NZ_xcc(dst);
  646 + gen_cc_C_sub_xcc(cpu_cc_src, src2);
  647 + gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
648 648 #endif
649 649 }
650 650  
651   -static inline void gen_op_subx_T1_T0_cc(void)
  651 +static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
652 652 {
653   - tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
  653 + tcg_gen_mov_tl(cpu_cc_src, src1);
654 654 gen_mov_reg_C(cpu_tmp0, cpu_psr);
655   - tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
  655 + tcg_gen_sub_tl(dst, src1, cpu_tmp0);
656 656 gen_cc_clear_icc();
657   - gen_cc_C_sub_icc(cpu_T[0], cpu_cc_src);
  657 + gen_cc_C_sub_icc(dst, cpu_cc_src);
658 658 #ifdef TARGET_SPARC64
659 659 gen_cc_clear_xcc();
660   - gen_cc_C_sub_xcc(cpu_T[0], cpu_cc_src);
  660 + gen_cc_C_sub_xcc(dst, cpu_cc_src);
661 661 #endif
662   - tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
663   - gen_cc_NZ_icc(cpu_T[0]);
664   - gen_cc_C_sub_icc(cpu_T[0], cpu_cc_src);
665   - gen_cc_V_sub_icc(cpu_T[0], cpu_cc_src, cpu_T[1]);
  662 + tcg_gen_sub_tl(dst, dst, src2);
  663 + gen_cc_NZ_icc(dst);
  664 + gen_cc_C_sub_icc(dst, cpu_cc_src);
  665 + gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
666 666 #ifdef TARGET_SPARC64
667   - gen_cc_NZ_xcc(cpu_T[0]);
668   - gen_cc_C_sub_xcc(cpu_T[0], cpu_cc_src);
669   - gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]);
  667 + gen_cc_NZ_xcc(dst);
  668 + gen_cc_C_sub_xcc(dst, cpu_cc_src);
  669 + gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
670 670 #endif
671 671 }
672 672  
673   -static inline void gen_op_tsub_T1_T0_cc(void)
  673 +static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
674 674 {
675   - tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
676   - tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
  675 + tcg_gen_mov_tl(cpu_cc_src, src1);
  676 + tcg_gen_sub_tl(dst, src1, src2);
677 677 gen_cc_clear_icc();
678   - gen_cc_NZ_icc(cpu_T[0]);
679   - gen_cc_C_sub_icc(cpu_cc_src, cpu_T[1]);
680   - gen_cc_V_sub_icc(cpu_T[0], cpu_cc_src, cpu_T[1]);
681   - gen_cc_V_tag(cpu_cc_src, cpu_T[1]);
  678 + gen_cc_NZ_icc(dst);
  679 + gen_cc_C_sub_icc(cpu_cc_src, src2);
  680 + gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
  681 + gen_cc_V_tag(cpu_cc_src, src2);
682 682 #ifdef TARGET_SPARC64
683 683 gen_cc_clear_xcc();
684   - gen_cc_NZ_xcc(cpu_T[0]);
685   - gen_cc_C_sub_xcc(cpu_cc_src, cpu_T[1]);
686   - gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]);
  684 + gen_cc_NZ_xcc(dst);
  685 + gen_cc_C_sub_xcc(cpu_cc_src, src2);
  686 + gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
687 687 #endif
688 688 }
689 689  
690   -static inline void gen_op_tsub_T1_T0_ccTV(void)
  690 +static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
691 691 {
692   - gen_tag_tv(cpu_T[0], cpu_T[1]);
693   - tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
694   - tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
695   - gen_sub_tv(cpu_T[0], cpu_cc_src, cpu_T[1]);
  692 + gen_tag_tv(src1, src2);
  693 + tcg_gen_mov_tl(cpu_cc_src, src1);
  694 + tcg_gen_sub_tl(dst, src1, src2);
  695 + gen_sub_tv(dst, cpu_cc_src, src2);
696 696 gen_cc_clear_icc();
697   - gen_cc_NZ_icc(cpu_T[0]);
698   - gen_cc_C_sub_icc(cpu_cc_src, cpu_T[1]);
  697 + gen_cc_NZ_icc(dst);
  698 + gen_cc_C_sub_icc(cpu_cc_src, src2);
699 699 #ifdef TARGET_SPARC64
700 700 gen_cc_clear_xcc();
701   - gen_cc_NZ_xcc(cpu_T[0]);
702   - gen_cc_C_sub_xcc(cpu_cc_src, cpu_T[1]);
703   - gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]);
  701 + gen_cc_NZ_xcc(dst);
  702 + gen_cc_C_sub_xcc(cpu_cc_src, src2);
  703 + gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
704 704 #endif
705 705 }
706 706  
707   -static inline void gen_op_mulscc_T1_T0(void)
  707 +static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
708 708 {
709 709 TCGv r_temp, r_temp2;
710 710 int l1, l2;
... ... @@ -722,7 +722,7 @@ static inline void gen_op_mulscc_T1_T0(void)
722 722 tcg_gen_trunc_tl_i32(r_temp2, r_temp);
723 723 tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
724 724 tcg_gen_brcond_i32(TCG_COND_EQ, r_temp2, tcg_const_i32(0), l1);
725   - tcg_gen_mov_tl(cpu_cc_src2, cpu_T[1]);
  725 + tcg_gen_mov_tl(cpu_cc_src2, src2);
726 726 tcg_gen_br(l2);
727 727 gen_set_label(l1);
728 728 tcg_gen_movi_tl(cpu_cc_src2, 0);
... ... @@ -730,7 +730,7 @@ static inline void gen_op_mulscc_T1_T0(void)
730 730  
731 731 // b2 = T0 & 1;
732 732 // env->y = (b2 << 31) | (env->y >> 1);
733   - tcg_gen_trunc_tl_i32(r_temp2, cpu_T[0]);
  733 + tcg_gen_trunc_tl_i32(r_temp2, src1);
734 734 tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
735 735 tcg_gen_shli_i32(r_temp2, r_temp2, 31);
736 736 tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
... ... @@ -746,61 +746,61 @@ static inline void gen_op_mulscc_T1_T0(void)
746 746 // T0 = (b1 << 31) | (T0 >> 1);
747 747 // src1 = T0;
748 748 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
749   - tcg_gen_shri_tl(cpu_cc_src, cpu_T[0], 1);
  749 + tcg_gen_shri_tl(cpu_cc_src, src1, 1);
750 750 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
751 751  
752 752 /* do addition and update flags */
753   - tcg_gen_add_tl(cpu_T[0], cpu_cc_src, cpu_cc_src2);
  753 + tcg_gen_add_tl(dst, cpu_cc_src, cpu_cc_src2);
754 754 tcg_gen_discard_tl(r_temp);
755 755  
756 756 gen_cc_clear_icc();
757   - gen_cc_NZ_icc(cpu_T[0]);
758   - gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_cc_src2);
759   - gen_cc_C_add_icc(cpu_T[0], cpu_cc_src);
  757 + gen_cc_NZ_icc(dst);
  758 + gen_cc_V_add_icc(dst, cpu_cc_src, cpu_cc_src2);
  759 + gen_cc_C_add_icc(dst, cpu_cc_src);
760 760 }
761 761  
762   -static inline void gen_op_umul_T1_T0(void)
  762 +static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
763 763 {
764 764 TCGv r_temp, r_temp2;
765 765  
766 766 r_temp = tcg_temp_new(TCG_TYPE_I64);
767 767 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
768 768  
769   - tcg_gen_extu_tl_i64(r_temp, cpu_T[1]);
770   - tcg_gen_extu_tl_i64(r_temp2, cpu_T[0]);
  769 + tcg_gen_extu_tl_i64(r_temp, src2);
  770 + tcg_gen_extu_tl_i64(r_temp2, src1);
771 771 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
772 772  
773 773 tcg_gen_shri_i64(r_temp, r_temp2, 32);
774 774 tcg_gen_trunc_i64_i32(r_temp, r_temp);
775 775 tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
776 776 #ifdef TARGET_SPARC64
777   - tcg_gen_mov_i64(cpu_T[0], r_temp2);
  777 + tcg_gen_mov_i64(dst, r_temp2);
778 778 #else
779   - tcg_gen_trunc_i64_tl(cpu_T[0], r_temp2);
  779 + tcg_gen_trunc_i64_tl(dst, r_temp2);
780 780 #endif
781 781  
782 782 tcg_gen_discard_i64(r_temp);
783 783 tcg_gen_discard_i64(r_temp2);
784 784 }
785 785  
786   -static inline void gen_op_smul_T1_T0(void)
  786 +static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
787 787 {
788 788 TCGv r_temp, r_temp2;
789 789  
790 790 r_temp = tcg_temp_new(TCG_TYPE_I64);
791 791 r_temp2 = tcg_temp_new(TCG_TYPE_I64);
792 792  
793   - tcg_gen_ext_tl_i64(r_temp, cpu_T[1]);
794   - tcg_gen_ext_tl_i64(r_temp2, cpu_T[0]);
  793 + tcg_gen_ext_tl_i64(r_temp, src2);
  794 + tcg_gen_ext_tl_i64(r_temp2, src1);
795 795 tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
796 796  
797 797 tcg_gen_shri_i64(r_temp, r_temp2, 32);
798 798 tcg_gen_trunc_i64_i32(r_temp, r_temp);
799 799 tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
800 800 #ifdef TARGET_SPARC64
801   - tcg_gen_mov_i64(cpu_T[0], r_temp2);
  801 + tcg_gen_mov_i64(dst, r_temp2);
802 802 #else
803   - tcg_gen_trunc_i64_tl(cpu_T[0], r_temp2);
  803 + tcg_gen_trunc_i64_tl(dst, r_temp2);
804 804 #endif
805 805  
806 806 tcg_gen_discard_i64(r_temp);
... ... @@ -818,29 +818,29 @@ static inline void gen_trap_ifdivzero_tl(TCGv divisor)
818 818 gen_set_label(l1);
819 819 }
820 820  
821   -static inline void gen_op_sdivx_T1_T0(void)
  821 +static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
822 822 {
823 823 int l1, l2;
824 824  
825 825 l1 = gen_new_label();
826 826 l2 = gen_new_label();
827   - gen_trap_ifdivzero_tl(cpu_T[1]);
828   - tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[0], tcg_const_tl(INT64_MIN), l1);
829   - tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[1], tcg_const_tl(-1), l1);
830   - tcg_gen_movi_i64(cpu_T[0], INT64_MIN);
  827 + gen_trap_ifdivzero_tl(src2);
  828 + tcg_gen_brcond_tl(TCG_COND_NE, src1, tcg_const_tl(INT64_MIN), l1);
  829 + tcg_gen_brcond_tl(TCG_COND_NE, src2, tcg_const_tl(-1), l1);
  830 + tcg_gen_movi_i64(dst, INT64_MIN);
831 831 tcg_gen_br(l2);
832 832 gen_set_label(l1);
833   - tcg_gen_div_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
  833 + tcg_gen_div_i64(dst, src1, src2);
834 834 gen_set_label(l2);
835 835 }
836 836 #endif
837 837  
838   -static inline void gen_op_div_cc(void)
  838 +static inline void gen_op_div_cc(TCGv dst)
839 839 {
840 840 int l1;
841 841  
842 842 gen_cc_clear_icc();
843   - gen_cc_NZ_icc(cpu_T[0]);
  843 + gen_cc_NZ_icc(dst);
844 844 l1 = gen_new_label();
845 845 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2));
846 846 tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
... ... @@ -848,13 +848,13 @@ static inline void gen_op_div_cc(void)
848 848 gen_set_label(l1);
849 849 }
850 850  
851   -static inline void gen_op_logic_T0_cc(void)
  851 +static inline void gen_op_logic_cc(TCGv dst)
852 852 {
853 853 gen_cc_clear_icc();
854   - gen_cc_NZ_icc(cpu_T[0]);
  854 + gen_cc_NZ_icc(dst);
855 855 #ifdef TARGET_SPARC64
856 856 gen_cc_clear_xcc();
857   - gen_cc_NZ_xcc(cpu_T[0]);
  857 + gen_cc_NZ_xcc(dst);
858 858 #endif
859 859 }
860 860  
... ... @@ -1177,35 +1177,36 @@ static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1177 1177 gen_set_label(l2);
1178 1178 }
1179 1179  
1180   -/* call this function before using T2 as it may have been set for a jump */
1181   -static inline void flush_T2(DisasContext * dc)
  1180 +/* call this function before using the condition register as it may
  1181 + have been set for a jump */
  1182 +static inline void flush_cond(DisasContext *dc, TCGv cond)
1182 1183 {
1183 1184 if (dc->npc == JUMP_PC) {
1184   - gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
  1185 + gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1185 1186 dc->npc = DYNAMIC_PC;
1186 1187 }
1187 1188 }
1188 1189  
1189   -static inline void save_npc(DisasContext * dc)
  1190 +static inline void save_npc(DisasContext *dc, TCGv cond)
1190 1191 {
1191 1192 if (dc->npc == JUMP_PC) {
1192   - gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
  1193 + gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1193 1194 dc->npc = DYNAMIC_PC;
1194 1195 } else if (dc->npc != DYNAMIC_PC) {
1195 1196 tcg_gen_movi_tl(cpu_npc, dc->npc);
1196 1197 }
1197 1198 }
1198 1199  
1199   -static inline void save_state(DisasContext * dc)
  1200 +static inline void save_state(DisasContext *dc, TCGv cond)
1200 1201 {
1201 1202 tcg_gen_movi_tl(cpu_pc, dc->pc);
1202   - save_npc(dc);
  1203 + save_npc(dc, cond);
1203 1204 }
1204 1205  
1205   -static inline void gen_mov_pc_npc(DisasContext * dc)
  1206 +static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1206 1207 {
1207 1208 if (dc->npc == JUMP_PC) {
1208   - gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cpu_T[2]);
  1209 + gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1209 1210 tcg_gen_mov_tl(cpu_pc, cpu_npc);
1210 1211 dc->pc = DYNAMIC_PC;
1211 1212 } else if (dc->npc == DYNAMIC_PC) {
... ... @@ -1371,20 +1372,21 @@ static const int gen_tcg_cond_reg[8] = {
1371 1372 TCG_COND_LT,
1372 1373 };
1373 1374  
1374   -static inline void gen_cond_reg(TCGv r_dst, int cond)
  1375 +static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1375 1376 {
1376 1377 int l1;
1377 1378  
1378 1379 l1 = gen_new_label();
1379 1380 tcg_gen_movi_tl(r_dst, 0);
1380   - tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_T[0], tcg_const_tl(0), l1);
  1381 + tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], r_src, tcg_const_tl(0), l1);
1381 1382 tcg_gen_movi_tl(r_dst, 1);
1382 1383 gen_set_label(l1);
1383 1384 }
1384 1385 #endif
1385 1386  
1386 1387 /* XXX: potentially incorrect if dynamic npc */
1387   -static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
  1388 +static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
  1389 + TCGv r_cond)
1388 1390 {
1389 1391 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1390 1392 target_ulong target = dc->pc + offset;
... ... @@ -1408,10 +1410,10 @@ static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
1408 1410 dc->npc = target;
1409 1411 }
1410 1412 } else {
1411   - flush_T2(dc);
1412   - gen_cond(cpu_T[2], cc, cond);
  1413 + flush_cond(dc, r_cond);
  1414 + gen_cond(r_cond, cc, cond);
1413 1415 if (a) {
1414   - gen_branch_a(dc, target, dc->npc, cpu_T[2]);
  1416 + gen_branch_a(dc, target, dc->npc, r_cond);
1415 1417 dc->is_br = 1;
1416 1418 } else {
1417 1419 dc->pc = dc->npc;
... ... @@ -1423,7 +1425,8 @@ static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
1423 1425 }
1424 1426  
1425 1427 /* XXX: potentially incorrect if dynamic npc */
1426   -static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
  1428 +static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
  1429 + TCGv r_cond)
1427 1430 {
1428 1431 unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1429 1432 target_ulong target = dc->pc + offset;
... ... @@ -1447,10 +1450,10 @@ static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
1447 1450 dc->npc = target;
1448 1451 }
1449 1452 } else {
1450   - flush_T2(dc);
1451   - gen_fcond(cpu_T[2], cc, cond);
  1453 + flush_cond(dc, r_cond);
  1454 + gen_fcond(r_cond, cc, cond);
1452 1455 if (a) {
1453   - gen_branch_a(dc, target, dc->npc, cpu_T[2]);
  1456 + gen_branch_a(dc, target, dc->npc, r_cond);
1454 1457 dc->is_br = 1;
1455 1458 } else {
1456 1459 dc->pc = dc->npc;
... ... @@ -1463,15 +1466,16 @@ static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
1463 1466  
1464 1467 #ifdef TARGET_SPARC64
1465 1468 /* XXX: potentially incorrect if dynamic npc */
1466   -static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
  1469 +static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
  1470 + TCGv r_cond, TCGv r_reg)
1467 1471 {
1468 1472 unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1469 1473 target_ulong target = dc->pc + offset;
1470 1474  
1471   - flush_T2(dc);
1472   - gen_cond_reg(cpu_T[2], cond);
  1475 + flush_cond(dc, r_cond);
  1476 + gen_cond_reg(r_cond, cond, r_reg);
1473 1477 if (a) {
1474   - gen_branch_a(dc, target, dc->npc, cpu_T[2]);
  1478 + gen_branch_a(dc, target, dc->npc, r_cond);
1475 1479 dc->is_br = 1;
1476 1480 } else {
1477 1481 dc->pc = dc->npc;
... ... @@ -1606,11 +1610,11 @@ static inline void gen_op_fpexception_im(int fsr_flags)
1606 1610 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_FP_EXCP));
1607 1611 }
1608 1612  
1609   -static int gen_trap_ifnofpu(DisasContext * dc)
  1613 +static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1610 1614 {
1611 1615 #if !defined(CONFIG_USER_ONLY)
1612 1616 if (!dc->fpu_enabled) {
1613   - save_state(dc);
  1617 + save_state(dc, r_cond);
1614 1618 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NFPU_INSN));
1615 1619 dc->is_br = 1;
1616 1620 return 1;
... ... @@ -1629,26 +1633,6 @@ static inline void gen_clear_float_exceptions(void)
1629 1633 tcg_gen_helper_0_0(helper_clear_float_exceptions);
1630 1634 }
1631 1635  
1632   -static inline void gen_check_align(TCGv r_addr, int align)
1633   -{
1634   - tcg_gen_helper_0_2(helper_check_align, r_addr, tcg_const_i32(align));
1635   -}
1636   -
1637   -static inline void gen_op_check_align_T0_1(void)
1638   -{
1639   - gen_check_align(cpu_T[0], 1);
1640   -}
1641   -
1642   -static inline void gen_op_check_align_T0_3(void)
1643   -{
1644   - gen_check_align(cpu_T[0], 3);
1645   -}
1646   -
1647   -static inline void gen_op_check_align_T0_7(void)
1648   -{
1649   - gen_check_align(cpu_T[0], 7);
1650   -}
1651   -
1652 1636 /* asi moves */
1653 1637 #ifdef TARGET_SPARC64
1654 1638 static inline TCGv gen_get_asi(int insn, TCGv r_addr)
... ... @@ -1668,37 +1652,36 @@ static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1668 1652 return r_asi;
1669 1653 }
1670 1654  
1671   -static inline void gen_ld_asi(int insn, int size, int sign)
  1655 +static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
1672 1656 {
1673 1657 TCGv r_asi;
1674 1658  
1675   - r_asi = gen_get_asi(insn, cpu_T[0]);
1676   - tcg_gen_helper_1_4(helper_ld_asi, cpu_T[1], cpu_T[0], r_asi,
  1659 + r_asi = gen_get_asi(insn, addr);
  1660 + tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi,
1677 1661 tcg_const_i32(size), tcg_const_i32(sign));
1678 1662 tcg_gen_discard_i32(r_asi);
1679 1663 }
1680 1664  
1681   -static inline void gen_st_asi(int insn, int size)
  1665 +static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1682 1666 {
1683 1667 TCGv r_asi;
1684 1668  
1685   - r_asi = gen_get_asi(insn, cpu_T[0]);
1686   - tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], r_asi,
1687   - tcg_const_i32(size));
  1669 + r_asi = gen_get_asi(insn, addr);
  1670 + tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, tcg_const_i32(size));
1688 1671 tcg_gen_discard_i32(r_asi);
1689 1672 }
1690 1673  
1691   -static inline void gen_ldf_asi(int insn, int size, int rd)
  1674 +static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1692 1675 {
1693 1676 TCGv r_asi;
1694 1677  
1695   - r_asi = gen_get_asi(insn, cpu_T[0]);
1696   - tcg_gen_helper_0_4(helper_ldf_asi, cpu_T[0], r_asi, tcg_const_i32(size),
  1678 + r_asi = gen_get_asi(insn, addr);
  1679 + tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, tcg_const_i32(size),
1697 1680 tcg_const_i32(rd));
1698 1681 tcg_gen_discard_i32(r_asi);
1699 1682 }
1700 1683  
1701   -static inline void gen_stf_asi(int insn, int size, int rd)
  1684 +static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1702 1685 {
1703 1686 TCGv r_asi;
1704 1687  
... ... @@ -1708,145 +1691,143 @@ static inline void gen_stf_asi(int insn, int size, int rd)
1708 1691 tcg_gen_discard_i32(r_asi);
1709 1692 }
1710 1693  
1711   -static inline void gen_swap_asi(int insn)
  1694 +static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1712 1695 {
1713 1696 TCGv r_temp, r_asi;
1714 1697  
1715 1698 r_temp = tcg_temp_new(TCG_TYPE_I32);
1716   - r_asi = gen_get_asi(insn, cpu_T[0]);
1717   - tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], r_asi,
  1699 + r_asi = gen_get_asi(insn, addr);
  1700 + tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, r_asi,
1718 1701 tcg_const_i32(4), tcg_const_i32(0));
1719   - tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], r_temp, r_asi,
  1702 + tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi,
1720 1703 tcg_const_i32(4));
1721   - tcg_gen_extu_i32_tl(cpu_T[1], r_temp);
  1704 + tcg_gen_extu_i32_tl(dst, r_temp);
1722 1705 tcg_gen_discard_i32(r_asi);
1723 1706 tcg_gen_discard_i32(r_temp);
1724 1707 }
1725 1708  
1726   -static inline void gen_ldda_asi(int insn)
  1709 +static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1727 1710 {
1728 1711 TCGv r_asi;
1729 1712  
1730   - r_asi = gen_get_asi(insn, cpu_T[0]);
1731   - tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, cpu_T[0], r_asi,
  1713 + r_asi = gen_get_asi(insn, addr);
  1714 + tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi,
1732 1715 tcg_const_i32(8), tcg_const_i32(0));
1733   - tcg_gen_andi_i64(cpu_T[0], cpu_tmp64, 0xffffffffULL);
  1716 + tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL);
1734 1717 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1735   - tcg_gen_andi_i64(cpu_T[1], cpu_tmp64, 0xffffffffULL);
  1718 + tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL);
1736 1719 tcg_gen_discard_i32(r_asi);
1737 1720 }
1738 1721  
1739   -static inline void gen_stda_asi(int insn, int rd)
  1722 +static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1740 1723 {
1741 1724 TCGv r_temp, r_asi;
1742 1725  
1743 1726 r_temp = tcg_temp_new(TCG_TYPE_I32);
1744 1727 gen_movl_reg_TN(rd + 1, r_temp);
1745   - tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_T[1],
  1728 + tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1746 1729 r_temp);
1747   - r_asi = gen_get_asi(insn, cpu_T[0]);
1748   - tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_tmp64, r_asi,
  1730 + r_asi = gen_get_asi(insn, addr);
  1731 + tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi,
1749 1732 tcg_const_i32(8));
1750 1733 tcg_gen_discard_i32(r_asi);
1751 1734 tcg_gen_discard_i32(r_temp);
1752 1735 }
1753 1736  
1754   -static inline void gen_cas_asi(int insn, int rd)
  1737 +static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
1755 1738 {
1756 1739 TCGv r_val1, r_asi;
1757 1740  
1758 1741 r_val1 = tcg_temp_new(TCG_TYPE_I32);
1759 1742 gen_movl_reg_TN(rd, r_val1);
1760   - r_asi = gen_get_asi(insn, cpu_T[0]);
1761   - tcg_gen_helper_1_4(helper_cas_asi, cpu_T[1], cpu_T[0], r_val1, cpu_T[1],
1762   - r_asi);
  1743 + r_asi = gen_get_asi(insn, addr);
  1744 + tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1763 1745 tcg_gen_discard_i32(r_asi);
1764 1746 tcg_gen_discard_i32(r_val1);
1765 1747 }
1766 1748  
1767   -static inline void gen_casx_asi(int insn, int rd)
  1749 +static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
1768 1750 {
1769 1751 TCGv r_asi;
1770 1752  
1771 1753 gen_movl_reg_TN(rd, cpu_tmp64);
1772   - r_asi = gen_get_asi(insn, cpu_T[0]);
1773   - tcg_gen_helper_1_4(helper_casx_asi, cpu_T[1], cpu_T[0], cpu_tmp64, cpu_T[1],
1774   - r_asi);
  1754 + r_asi = gen_get_asi(insn, addr);
  1755 + tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1775 1756 tcg_gen_discard_i32(r_asi);
1776 1757 }
1777 1758  
1778 1759 #elif !defined(CONFIG_USER_ONLY)
1779 1760  
1780   -static inline void gen_ld_asi(int insn, int size, int sign)
  1761 +static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
1781 1762 {
1782 1763 int asi;
1783 1764  
1784 1765 asi = GET_FIELD(insn, 19, 26);
1785   - tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, cpu_T[0], tcg_const_i32(asi),
  1766 + tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
1786 1767 tcg_const_i32(size), tcg_const_i32(sign));
1787   - tcg_gen_trunc_i64_tl(cpu_T[1], cpu_tmp64);
  1768 + tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1788 1769 }
1789 1770  
1790   -static inline void gen_st_asi(int insn, int size)
  1771 +static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1791 1772 {
1792 1773 int asi;
1793 1774  
1794   - tcg_gen_extu_tl_i64(cpu_tmp64, cpu_T[1]);
  1775 + tcg_gen_extu_tl_i64(cpu_tmp64, src);
1795 1776 asi = GET_FIELD(insn, 19, 26);
1796   - tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_tmp64, tcg_const_i32(asi),
  1777 + tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
1797 1778 tcg_const_i32(size));
1798 1779 }
1799 1780  
1800   -static inline void gen_swap_asi(int insn)
  1781 +static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1801 1782 {
1802 1783 int asi;
1803 1784 TCGv r_temp;
1804 1785  
1805 1786 r_temp = tcg_temp_new(TCG_TYPE_I32);
1806 1787 asi = GET_FIELD(insn, 19, 26);
1807   - tcg_gen_helper_1_4(helper_ld_asi, r_temp, cpu_T[0], tcg_const_i32(asi),
  1788 + tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, tcg_const_i32(asi),
1808 1789 tcg_const_i32(4), tcg_const_i32(0));
1809   - tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_T[1], tcg_const_i32(asi),
  1790 + tcg_gen_helper_0_4(helper_st_asi, addr, dst, tcg_const_i32(asi),
1810 1791 tcg_const_i32(4));
1811   - tcg_gen_extu_i32_tl(cpu_T[1], r_temp);
  1792 + tcg_gen_extu_i32_tl(dst, r_temp);
1812 1793 tcg_gen_discard_i32(r_temp);
1813 1794 }
1814 1795  
1815   -static inline void gen_ldda_asi(int insn)
  1796 +static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1816 1797 {
1817 1798 int asi;
1818 1799  
1819 1800 asi = GET_FIELD(insn, 19, 26);
1820   - tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, cpu_T[0], tcg_const_i32(asi),
  1801 + tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
1821 1802 tcg_const_i32(8), tcg_const_i32(0));
1822   - tcg_gen_trunc_i64_tl(cpu_T[0], cpu_tmp64);
  1803 + tcg_gen_trunc_i64_tl(lo, cpu_tmp64);
1823 1804 tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1824   - tcg_gen_trunc_i64_tl(cpu_T[1], cpu_tmp64);
  1805 + tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1825 1806 }
1826 1807  
1827   -static inline void gen_stda_asi(int insn, int rd)
  1808 +static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1828 1809 {
1829 1810 int asi;
1830 1811 TCGv r_temp;
1831 1812  
1832 1813 r_temp = tcg_temp_new(TCG_TYPE_I32);
1833 1814 gen_movl_reg_TN(rd + 1, r_temp);
1834   - tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_T[1], r_temp);
  1815 + tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1835 1816 asi = GET_FIELD(insn, 19, 26);
1836   - tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], cpu_tmp64, tcg_const_i32(asi),
  1817 + tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
1837 1818 tcg_const_i32(8));
1838 1819 }
1839 1820 #endif
1840 1821  
1841 1822 #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1842   -static inline void gen_ldstub_asi(int insn)
  1823 +static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1843 1824 {
1844 1825 int asi;
1845 1826  
1846   - gen_ld_asi(insn, 1, 0);
  1827 + gen_ld_asi(dst, addr, insn, 1, 0);
1847 1828  
1848 1829 asi = GET_FIELD(insn, 19, 26);
1849   - tcg_gen_helper_0_4(helper_st_asi, cpu_T[0], tcg_const_i64(0xffULL),
  1830 + tcg_gen_helper_0_4(helper_st_asi, addr, tcg_const_i64(0xffULL),
1850 1831 tcg_const_i32(asi), tcg_const_i32(1));
1851 1832 }
1852 1833 #endif
... ... @@ -1876,9 +1857,9 @@ static void disas_sparc_insn(DisasContext * dc)
1876 1857 target <<= 2;
1877 1858 cc = GET_FIELD_SP(insn, 20, 21);
1878 1859 if (cc == 0)
1879   - do_branch(dc, target, insn, 0);
  1860 + do_branch(dc, target, insn, 0, cpu_T[2]);
1880 1861 else if (cc == 2)
1881   - do_branch(dc, target, insn, 1);
  1862 + do_branch(dc, target, insn, 1, cpu_T[2]);
1882 1863 else
1883 1864 goto illegal_insn;
1884 1865 goto jmp_insn;
... ... @@ -1891,18 +1872,18 @@ static void disas_sparc_insn(DisasContext * dc)
1891 1872 target <<= 2;
1892 1873 rs1 = GET_FIELD(insn, 13, 17);
1893 1874 gen_movl_reg_TN(rs1, cpu_T[0]);
1894   - do_branch_reg(dc, target, insn);
  1875 + do_branch_reg(dc, target, insn, cpu_T[2], cpu_T[0]);
1895 1876 goto jmp_insn;
1896 1877 }
1897 1878 case 0x5: /* V9 FBPcc */
1898 1879 {
1899 1880 int cc = GET_FIELD_SP(insn, 20, 21);
1900   - if (gen_trap_ifnofpu(dc))
  1881 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
1901 1882 goto jmp_insn;
1902 1883 target = GET_FIELD_SP(insn, 0, 18);
1903 1884 target = sign_extend(target, 19);
1904 1885 target <<= 2;
1905   - do_fbranch(dc, target, insn, cc);
  1886 + do_fbranch(dc, target, insn, cc, cpu_T[2]);
1906 1887 goto jmp_insn;
1907 1888 }
1908 1889 #else
... ... @@ -1916,17 +1897,17 @@ static void disas_sparc_insn(DisasContext * dc)
1916 1897 target = GET_FIELD(insn, 10, 31);
1917 1898 target = sign_extend(target, 22);
1918 1899 target <<= 2;
1919   - do_branch(dc, target, insn, 0);
  1900 + do_branch(dc, target, insn, 0, cpu_T[2]);
1920 1901 goto jmp_insn;
1921 1902 }
1922 1903 case 0x6: /* FBN+x */
1923 1904 {
1924   - if (gen_trap_ifnofpu(dc))
  1905 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
1925 1906 goto jmp_insn;
1926 1907 target = GET_FIELD(insn, 10, 31);
1927 1908 target = sign_extend(target, 22);
1928 1909 target <<= 2;
1929   - do_fbranch(dc, target, insn, 0);
  1910 + do_fbranch(dc, target, insn, 0, cpu_T[2]);
1930 1911 goto jmp_insn;
1931 1912 }
1932 1913 case 0x4: /* SETHI */
... ... @@ -1954,7 +1935,7 @@ static void disas_sparc_insn(DisasContext * dc)
1954 1935  
1955 1936 gen_movl_TN_reg(15, tcg_const_tl(dc->pc));
1956 1937 target += dc->pc;
1957   - gen_mov_pc_npc(dc);
  1938 + gen_mov_pc_npc(dc, cpu_T[2]);
1958 1939 dc->npc = target;
1959 1940 }
1960 1941 goto jmp_insn;
... ... @@ -1982,7 +1963,7 @@ static void disas_sparc_insn(DisasContext * dc)
1982 1963 }
1983 1964 cond = GET_FIELD(insn, 3, 6);
1984 1965 if (cond == 0x8) {
1985   - save_state(dc);
  1966 + save_state(dc, cpu_T[2]);
1986 1967 tcg_gen_helper_0_1(helper_trap, cpu_T[0]);
1987 1968 } else if (cond != 0) {
1988 1969 TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
... ... @@ -1990,7 +1971,7 @@ static void disas_sparc_insn(DisasContext * dc)
1990 1971 /* V9 icc/xcc */
1991 1972 int cc = GET_FIELD_SP(insn, 11, 12);
1992 1973  
1993   - save_state(dc);
  1974 + save_state(dc, cpu_T[2]);
1994 1975 if (cc == 0)
1995 1976 gen_cond(r_cond, 0, cond);
1996 1977 else if (cc == 2)
... ... @@ -1998,7 +1979,7 @@ static void disas_sparc_insn(DisasContext * dc)
1998 1979 else
1999 1980 goto illegal_insn;
2000 1981 #else
2001   - save_state(dc);
  1982 + save_state(dc, cpu_T[2]);
2002 1983 gen_cond(r_cond, 0, cond);
2003 1984 #endif
2004 1985 tcg_gen_helper_0_2(helper_trapcc, cpu_T[0], r_cond);
... ... @@ -2060,7 +2041,7 @@ static void disas_sparc_insn(DisasContext * dc)
2060 2041 case 0xf: /* V9 membar */
2061 2042 break; /* no effect */
2062 2043 case 0x13: /* Graphics Status */
2063   - if (gen_trap_ifnofpu(dc))
  2044 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
2064 2045 goto jmp_insn;
2065 2046 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, gsr));
2066 2047 gen_movl_TN_reg(rd, cpu_T[0]);
... ... @@ -2275,7 +2256,7 @@ static void disas_sparc_insn(DisasContext * dc)
2275 2256 break;
2276 2257 #endif
2277 2258 } else if (xop == 0x34) { /* FPU Operations */
2278   - if (gen_trap_ifnofpu(dc))
  2259 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
2279 2260 goto jmp_insn;
2280 2261 gen_op_clear_ieee_excp_and_FTT();
2281 2262 rs1 = GET_FIELD(insn, 13, 17);
... ... @@ -2650,7 +2631,7 @@ static void disas_sparc_insn(DisasContext * dc)
2650 2631 #ifdef TARGET_SPARC64
2651 2632 int cond;
2652 2633 #endif
2653   - if (gen_trap_ifnofpu(dc))
  2634 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
2654 2635 goto jmp_insn;
2655 2636 gen_op_clear_ieee_excp_and_FTT();
2656 2637 rs1 = GET_FIELD(insn, 13, 17);
... ... @@ -2977,28 +2958,28 @@ static void disas_sparc_insn(DisasContext * dc)
2977 2958 switch (xop & ~0x10) {
2978 2959 case 0x0:
2979 2960 if (xop & 0x10)
2980   - gen_op_add_T1_T0_cc();
  2961 + gen_op_add_cc(cpu_T[0], cpu_T[0], cpu_T[1]);
2981 2962 else
2982 2963 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2983 2964 break;
2984 2965 case 0x1:
2985 2966 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2986 2967 if (xop & 0x10)
2987   - gen_op_logic_T0_cc();
  2968 + gen_op_logic_cc(cpu_T[0]);
2988 2969 break;
2989 2970 case 0x2:
2990 2971 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2991 2972 if (xop & 0x10)
2992   - gen_op_logic_T0_cc();
  2973 + gen_op_logic_cc(cpu_T[0]);
2993 2974 break;
2994 2975 case 0x3:
2995 2976 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
2996 2977 if (xop & 0x10)
2997   - gen_op_logic_T0_cc();
  2978 + gen_op_logic_cc(cpu_T[0]);
2998 2979 break;
2999 2980 case 0x4:
3000 2981 if (xop & 0x10)
3001   - gen_op_sub_T1_T0_cc();
  2982 + gen_op_sub_cc(cpu_T[0], cpu_T[0], cpu_T[1]);
3002 2983 else
3003 2984 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3004 2985 break;
... ... @@ -3006,23 +2987,23 @@ static void disas_sparc_insn(DisasContext * dc)
3006 2987 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
3007 2988 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3008 2989 if (xop & 0x10)
3009   - gen_op_logic_T0_cc();
  2990 + gen_op_logic_cc(cpu_T[0]);
3010 2991 break;
3011 2992 case 0x6:
3012 2993 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
3013 2994 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3014 2995 if (xop & 0x10)
3015   - gen_op_logic_T0_cc();
  2996 + gen_op_logic_cc(cpu_T[0]);
3016 2997 break;
3017 2998 case 0x7:
3018 2999 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
3019 3000 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3020 3001 if (xop & 0x10)
3021   - gen_op_logic_T0_cc();
  3002 + gen_op_logic_cc(cpu_T[0]);
3022 3003 break;
3023 3004 case 0x8:
3024 3005 if (xop & 0x10)
3025   - gen_op_addx_T1_T0_cc();
  3006 + gen_op_addx_cc(cpu_T[0], cpu_T[0], cpu_T[1]);
3026 3007 else {
3027 3008 gen_mov_reg_C(cpu_tmp0, cpu_psr);
3028 3009 tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
... ... @@ -3035,18 +3016,18 @@ static void disas_sparc_insn(DisasContext * dc)
3035 3016 break;
3036 3017 #endif
3037 3018 case 0xa:
3038   - gen_op_umul_T1_T0();
  3019 + gen_op_umul(cpu_T[0], cpu_T[0], cpu_T[1]);
3039 3020 if (xop & 0x10)
3040   - gen_op_logic_T0_cc();
  3021 + gen_op_logic_cc(cpu_T[0]);
3041 3022 break;
3042 3023 case 0xb:
3043   - gen_op_smul_T1_T0();
  3024 + gen_op_smul(cpu_T[0], cpu_T[0], cpu_T[1]);
3044 3025 if (xop & 0x10)
3045   - gen_op_logic_T0_cc();
  3026 + gen_op_logic_cc(cpu_T[0]);
3046 3027 break;
3047 3028 case 0xc:
3048 3029 if (xop & 0x10)
3049   - gen_op_subx_T1_T0_cc();
  3030 + gen_op_subx_cc(cpu_T[0], cpu_T[0], cpu_T[1]);
3050 3031 else {
3051 3032 gen_mov_reg_C(cpu_tmp0, cpu_psr);
3052 3033 tcg_gen_add_tl(cpu_T[1], cpu_T[1], cpu_tmp0);
... ... @@ -3062,12 +3043,12 @@ static void disas_sparc_insn(DisasContext * dc)
3062 3043 case 0xe:
3063 3044 tcg_gen_helper_1_2(helper_udiv, cpu_T[0], cpu_T[0], cpu_T[1]);
3064 3045 if (xop & 0x10)
3065   - gen_op_div_cc();
  3046 + gen_op_div_cc(cpu_T[0]);
3066 3047 break;
3067 3048 case 0xf:
3068 3049 tcg_gen_helper_1_2(helper_sdiv, cpu_T[0], cpu_T[0], cpu_T[1]);
3069 3050 if (xop & 0x10)
3070   - gen_op_div_cc();
  3051 + gen_op_div_cc(cpu_T[0]);
3071 3052 break;
3072 3053 default:
3073 3054 goto illegal_insn;
... ... @@ -3076,25 +3057,25 @@ static void disas_sparc_insn(DisasContext * dc)
3076 3057 } else {
3077 3058 switch (xop) {
3078 3059 case 0x20: /* taddcc */
3079   - gen_op_tadd_T1_T0_cc();
  3060 + gen_op_tadd_cc(cpu_T[0], cpu_T[0], cpu_T[1]);
3080 3061 gen_movl_TN_reg(rd, cpu_T[0]);
3081 3062 break;
3082 3063 case 0x21: /* tsubcc */
3083   - gen_op_tsub_T1_T0_cc();
  3064 + gen_op_tsub_cc(cpu_T[0], cpu_T[0], cpu_T[1]);
3084 3065 gen_movl_TN_reg(rd, cpu_T[0]);
3085 3066 break;
3086 3067 case 0x22: /* taddcctv */
3087   - save_state(dc);
3088   - gen_op_tadd_T1_T0_ccTV();
  3068 + save_state(dc, cpu_T[2]);
  3069 + gen_op_tadd_ccTV(cpu_T[0], cpu_T[0], cpu_T[1]);
3089 3070 gen_movl_TN_reg(rd, cpu_T[0]);
3090 3071 break;
3091 3072 case 0x23: /* tsubcctv */
3092   - save_state(dc);
3093   - gen_op_tsub_T1_T0_ccTV();
  3073 + save_state(dc, cpu_T[2]);
  3074 + gen_op_tsub_ccTV(cpu_T[0], cpu_T[0], cpu_T[1]);
3094 3075 gen_movl_TN_reg(rd, cpu_T[0]);
3095 3076 break;
3096 3077 case 0x24: /* mulscc */
3097   - gen_op_mulscc_T1_T0();
  3078 + gen_op_mulscc(cpu_T[0], cpu_T[0], cpu_T[1]);
3098 3079 gen_movl_TN_reg(rd, cpu_T[0]);
3099 3080 break;
3100 3081 #ifndef TARGET_SPARC64
... ... @@ -3145,7 +3126,7 @@ static void disas_sparc_insn(DisasContext * dc)
3145 3126 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3146 3127 tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_T[0]);
3147 3128 tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
3148   - save_state(dc);
  3129 + save_state(dc, cpu_T[2]);
3149 3130 gen_op_next_insn();
3150 3131 tcg_gen_exit_tb(0);
3151 3132 dc->is_br = 1;
... ... @@ -3157,7 +3138,7 @@ static void disas_sparc_insn(DisasContext * dc)
3157 3138 #endif
3158 3139 break;
3159 3140 case 0x13: /* Graphics Status */
3160   - if (gen_trap_ifnofpu(dc))
  3141 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
3161 3142 goto jmp_insn;
3162 3143 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3163 3144 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, gsr));
... ... @@ -3257,7 +3238,7 @@ static void disas_sparc_insn(DisasContext * dc)
3257 3238 #else
3258 3239 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3259 3240 tcg_gen_helper_0_1(helper_wrpsr, cpu_T[0]);
3260   - save_state(dc);
  3241 + save_state(dc, cpu_T[2]);
3261 3242 gen_op_next_insn();
3262 3243 tcg_gen_exit_tb(0);
3263 3244 dc->is_br = 1;
... ... @@ -3335,7 +3316,7 @@ static void disas_sparc_insn(DisasContext * dc)
3335 3316 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUSPARCState, tbr));
3336 3317 break;
3337 3318 case 6: // pstate
3338   - save_state(dc);
  3319 + save_state(dc, cpu_T[2]);
3339 3320 tcg_gen_helper_0_1(helper_wrpstate, cpu_T[0]);
3340 3321 gen_op_next_insn();
3341 3322 tcg_gen_exit_tb(0);
... ... @@ -3406,7 +3387,7 @@ static void disas_sparc_insn(DisasContext * dc)
3406 3387 switch (rd) {
3407 3388 case 0: // hpstate
3408 3389 // XXX gen_op_wrhpstate();
3409   - save_state(dc);
  3390 + save_state(dc, cpu_T[2]);
3410 3391 gen_op_next_insn();
3411 3392 tcg_gen_exit_tb(0);
3412 3393 dc->is_br = 1;
... ... @@ -3481,7 +3462,7 @@ static void disas_sparc_insn(DisasContext * dc)
3481 3462 break;
3482 3463 }
3483 3464 case 0x2d: /* V9 sdivx */
3484   - gen_op_sdivx_T1_T0();
  3465 + gen_op_sdivx(cpu_T[0], cpu_T[0], cpu_T[1]);
3485 3466 gen_movl_TN_reg(rd, cpu_T[0]);
3486 3467 break;
3487 3468 case 0x2e: /* V9 popc */
... ... @@ -3532,7 +3513,7 @@ static void disas_sparc_insn(DisasContext * dc)
3532 3513 int opf = GET_FIELD_SP(insn, 5, 13);
3533 3514 rs1 = GET_FIELD(insn, 13, 17);
3534 3515 rs2 = GET_FIELD(insn, 27, 31);
3535   - if (gen_trap_ifnofpu(dc))
  3516 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
3536 3517 goto jmp_insn;
3537 3518  
3538 3519 switch (opf) {
... ... @@ -3940,7 +3921,7 @@ static void disas_sparc_insn(DisasContext * dc)
3940 3921 #ifdef TARGET_SPARC64
3941 3922 } else if (xop == 0x39) { /* V9 return */
3942 3923 rs1 = GET_FIELD(insn, 13, 17);
3943   - save_state(dc);
  3924 + save_state(dc, cpu_T[2]);
3944 3925 gen_movl_reg_TN(rs1, cpu_T[0]);
3945 3926 if (IS_IMM) { /* immediate */
3946 3927 rs2 = GET_FIELDs(insn, 19, 31);
... ... @@ -3957,8 +3938,8 @@ static void disas_sparc_insn(DisasContext * dc)
3957 3938 #endif
3958 3939 }
3959 3940 tcg_gen_helper_0_0(helper_restore);
3960   - gen_mov_pc_npc(dc);
3961   - gen_op_check_align_T0_3();
  3941 + gen_mov_pc_npc(dc, cpu_T[2]);
  3942 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
3962 3943 tcg_gen_mov_tl(cpu_npc, cpu_T[0]);
3963 3944 dc->npc = DYNAMIC_PC;
3964 3945 goto jmp_insn;
... ... @@ -3987,8 +3968,8 @@ static void disas_sparc_insn(DisasContext * dc)
3987 3968 tcg_gen_movi_tl(cpu_T[1], dc->pc);
3988 3969 gen_movl_TN_reg(rd, cpu_T[1]);
3989 3970 }
3990   - gen_mov_pc_npc(dc);
3991   - gen_op_check_align_T0_3();
  3971 + gen_mov_pc_npc(dc, cpu_T[2]);
  3972 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
3992 3973 tcg_gen_mov_tl(cpu_npc, cpu_T[0]);
3993 3974 dc->npc = DYNAMIC_PC;
3994 3975 }
... ... @@ -3998,8 +3979,8 @@ static void disas_sparc_insn(DisasContext * dc)
3998 3979 {
3999 3980 if (!supervisor(dc))
4000 3981 goto priv_insn;
4001   - gen_mov_pc_npc(dc);
4002   - gen_op_check_align_T0_3();
  3982 + gen_mov_pc_npc(dc, cpu_T[2]);
  3983 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4003 3984 tcg_gen_mov_tl(cpu_npc, cpu_T[0]);
4004 3985 dc->npc = DYNAMIC_PC;
4005 3986 tcg_gen_helper_0_0(helper_rett);
... ... @@ -4010,12 +3991,12 @@ static void disas_sparc_insn(DisasContext * dc)
4010 3991 tcg_gen_helper_0_1(helper_flush, cpu_T[0]);
4011 3992 break;
4012 3993 case 0x3c: /* save */
4013   - save_state(dc);
  3994 + save_state(dc, cpu_T[2]);
4014 3995 tcg_gen_helper_0_0(helper_save);
4015 3996 gen_movl_TN_reg(rd, cpu_T[0]);
4016 3997 break;
4017 3998 case 0x3d: /* restore */
4018   - save_state(dc);
  3999 + save_state(dc, cpu_T[2]);
4019 4000 tcg_gen_helper_0_0(helper_restore);
4020 4001 gen_movl_TN_reg(rd, cpu_T[0]);
4021 4002 break;
... ... @@ -4054,7 +4035,7 @@ static void disas_sparc_insn(DisasContext * dc)
4054 4035 {
4055 4036 unsigned int xop = GET_FIELD(insn, 7, 12);
4056 4037 rs1 = GET_FIELD(insn, 13, 17);
4057   - save_state(dc);
  4038 + save_state(dc, cpu_T[2]);
4058 4039 gen_movl_reg_TN(rs1, cpu_T[0]);
4059 4040 if (xop == 0x3c || xop == 0x3e)
4060 4041 {
... ... @@ -4080,7 +4061,7 @@ static void disas_sparc_insn(DisasContext * dc)
4080 4061 (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4081 4062 switch (xop) {
4082 4063 case 0x0: /* load unsigned word */
4083   - gen_op_check_align_T0_3();
  4064 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4084 4065 ABI32_MASK(cpu_T[0]);
4085 4066 tcg_gen_qemu_ld32u(cpu_T[1], cpu_T[0], dc->mem_idx);
4086 4067 break;
... ... @@ -4089,7 +4070,7 @@ static void disas_sparc_insn(DisasContext * dc)
4089 4070 tcg_gen_qemu_ld8u(cpu_T[1], cpu_T[0], dc->mem_idx);
4090 4071 break;
4091 4072 case 0x2: /* load unsigned halfword */
4092   - gen_op_check_align_T0_1();
  4073 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(1));
4093 4074 ABI32_MASK(cpu_T[0]);
4094 4075 tcg_gen_qemu_ld16u(cpu_T[1], cpu_T[0], dc->mem_idx);
4095 4076 break;
... ... @@ -4097,7 +4078,7 @@ static void disas_sparc_insn(DisasContext * dc)
4097 4078 if (rd & 1)
4098 4079 goto illegal_insn;
4099 4080 else {
4100   - gen_op_check_align_T0_7();
  4081 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
4101 4082 ABI32_MASK(cpu_T[0]);
4102 4083 tcg_gen_qemu_ld64(cpu_tmp64, cpu_T[0], dc->mem_idx);
4103 4084 tcg_gen_trunc_i64_tl(cpu_T[0], cpu_tmp64);
... ... @@ -4113,7 +4094,7 @@ static void disas_sparc_insn(DisasContext * dc)
4113 4094 tcg_gen_qemu_ld8s(cpu_T[1], cpu_T[0], dc->mem_idx);
4114 4095 break;
4115 4096 case 0xa: /* load signed halfword */
4116   - gen_op_check_align_T0_1();
  4097 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(1));
4117 4098 ABI32_MASK(cpu_T[0]);
4118 4099 tcg_gen_qemu_ld16s(cpu_T[1], cpu_T[0], dc->mem_idx);
4119 4100 break;
... ... @@ -4123,7 +4104,7 @@ static void disas_sparc_insn(DisasContext * dc)
4123 4104 tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_T[0], dc->mem_idx);
4124 4105 break;
4125 4106 case 0x0f: /* swap register with memory. Also atomically */
4126   - gen_op_check_align_T0_3();
  4107 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4127 4108 gen_movl_reg_TN(rd, cpu_T[1]);
4128 4109 ABI32_MASK(cpu_T[0]);
4129 4110 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
... ... @@ -4138,8 +4119,8 @@ static void disas_sparc_insn(DisasContext * dc)
4138 4119 if (!supervisor(dc))
4139 4120 goto priv_insn;
4140 4121 #endif
4141   - gen_op_check_align_T0_3();
4142   - gen_ld_asi(insn, 4, 0);
  4122 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
  4123 + gen_ld_asi(cpu_T[1], cpu_T[0], insn, 4, 0);
4143 4124 break;
4144 4125 case 0x11: /* load unsigned byte alternate */
4145 4126 #ifndef TARGET_SPARC64
... ... @@ -4148,7 +4129,7 @@ static void disas_sparc_insn(DisasContext * dc)
4148 4129 if (!supervisor(dc))
4149 4130 goto priv_insn;
4150 4131 #endif
4151   - gen_ld_asi(insn, 1, 0);
  4132 + gen_ld_asi(cpu_T[1], cpu_T[0], insn, 1, 0);
4152 4133 break;
4153 4134 case 0x12: /* load unsigned halfword alternate */
4154 4135 #ifndef TARGET_SPARC64
... ... @@ -4157,8 +4138,8 @@ static void disas_sparc_insn(DisasContext * dc)
4157 4138 if (!supervisor(dc))
4158 4139 goto priv_insn;
4159 4140 #endif
4160   - gen_op_check_align_T0_1();
4161   - gen_ld_asi(insn, 2, 0);
  4141 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(1));
  4142 + gen_ld_asi(cpu_T[1], cpu_T[0], insn, 2, 0);
4162 4143 break;
4163 4144 case 0x13: /* load double word alternate */
4164 4145 #ifndef TARGET_SPARC64
... ... @@ -4169,8 +4150,8 @@ static void disas_sparc_insn(DisasContext * dc)
4169 4150 #endif
4170 4151 if (rd & 1)
4171 4152 goto illegal_insn;
4172   - gen_op_check_align_T0_7();
4173   - gen_ldda_asi(insn);
  4153 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
  4154 + gen_ldda_asi(cpu_T[0], cpu_T[1], cpu_T[0], insn);
4174 4155 gen_movl_TN_reg(rd + 1, cpu_T[0]);
4175 4156 break;
4176 4157 case 0x19: /* load signed byte alternate */
... ... @@ -4180,7 +4161,7 @@ static void disas_sparc_insn(DisasContext * dc)
4180 4161 if (!supervisor(dc))
4181 4162 goto priv_insn;
4182 4163 #endif
4183   - gen_ld_asi(insn, 1, 1);
  4164 + gen_ld_asi(cpu_T[1], cpu_T[0], insn, 1, 1);
4184 4165 break;
4185 4166 case 0x1a: /* load signed halfword alternate */
4186 4167 #ifndef TARGET_SPARC64
... ... @@ -4189,8 +4170,8 @@ static void disas_sparc_insn(DisasContext * dc)
4189 4170 if (!supervisor(dc))
4190 4171 goto priv_insn;
4191 4172 #endif
4192   - gen_op_check_align_T0_1();
4193   - gen_ld_asi(insn, 2, 1);
  4173 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(1));
  4174 + gen_ld_asi(cpu_T[1], cpu_T[0], insn, 2, 1);
4194 4175 break;
4195 4176 case 0x1d: /* ldstuba -- XXX: should be atomically */
4196 4177 #ifndef TARGET_SPARC64
... ... @@ -4199,7 +4180,7 @@ static void disas_sparc_insn(DisasContext * dc)
4199 4180 if (!supervisor(dc))
4200 4181 goto priv_insn;
4201 4182 #endif
4202   - gen_ldstub_asi(insn);
  4183 + gen_ldstub_asi(cpu_T[1], cpu_T[0], insn);
4203 4184 break;
4204 4185 case 0x1f: /* swap reg with alt. memory. Also atomically */
4205 4186 #ifndef TARGET_SPARC64
... ... @@ -4208,9 +4189,9 @@ static void disas_sparc_insn(DisasContext * dc)
4208 4189 if (!supervisor(dc))
4209 4190 goto priv_insn;
4210 4191 #endif
4211   - gen_op_check_align_T0_3();
  4192 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4212 4193 gen_movl_reg_TN(rd, cpu_T[1]);
4213   - gen_swap_asi(insn);
  4194 + gen_swap_asi(cpu_T[1], cpu_T[0], insn);
4214 4195 break;
4215 4196  
4216 4197 #ifndef TARGET_SPARC64
... ... @@ -4222,39 +4203,39 @@ static void disas_sparc_insn(DisasContext * dc)
4222 4203 #endif
4223 4204 #ifdef TARGET_SPARC64
4224 4205 case 0x08: /* V9 ldsw */
4225   - gen_op_check_align_T0_3();
  4206 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4226 4207 ABI32_MASK(cpu_T[0]);
4227 4208 tcg_gen_qemu_ld32s(cpu_T[1], cpu_T[0], dc->mem_idx);
4228 4209 break;
4229 4210 case 0x0b: /* V9 ldx */
4230   - gen_op_check_align_T0_7();
  4211 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
4231 4212 ABI32_MASK(cpu_T[0]);
4232 4213 tcg_gen_qemu_ld64(cpu_T[1], cpu_T[0], dc->mem_idx);
4233 4214 break;
4234 4215 case 0x18: /* V9 ldswa */
4235   - gen_op_check_align_T0_3();
4236   - gen_ld_asi(insn, 4, 1);
  4216 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
  4217 + gen_ld_asi(cpu_T[1], cpu_T[0], insn, 4, 1);
4237 4218 break;
4238 4219 case 0x1b: /* V9 ldxa */
4239   - gen_op_check_align_T0_7();
4240   - gen_ld_asi(insn, 8, 0);
  4220 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
  4221 + gen_ld_asi(cpu_T[1], cpu_T[0], insn, 8, 0);
4241 4222 break;
4242 4223 case 0x2d: /* V9 prefetch, no effect */
4243 4224 goto skip_move;
4244 4225 case 0x30: /* V9 ldfa */
4245   - gen_op_check_align_T0_3();
4246   - gen_ldf_asi(insn, 4, rd);
  4226 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
  4227 + gen_ldf_asi(cpu_T[0], insn, 4, rd);
4247 4228 goto skip_move;
4248 4229 case 0x33: /* V9 lddfa */
4249   - gen_op_check_align_T0_3();
4250   - gen_ldf_asi(insn, 8, DFPREG(rd));
  4230 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
  4231 + gen_ldf_asi(cpu_T[0], insn, 8, DFPREG(rd));
4251 4232 goto skip_move;
4252 4233 case 0x3d: /* V9 prefetcha, no effect */
4253 4234 goto skip_move;
4254 4235 case 0x32: /* V9 ldqfa */
4255 4236 #if defined(CONFIG_USER_ONLY)
4256   - gen_op_check_align_T0_3();
4257   - gen_ldf_asi(insn, 16, QFPREG(rd));
  4237 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
  4238 + gen_ldf_asi(cpu_T[0], insn, 16, QFPREG(rd));
4258 4239 goto skip_move;
4259 4240 #else
4260 4241 goto nfpu_insn;
... ... @@ -4268,17 +4249,17 @@ static void disas_sparc_insn(DisasContext * dc)
4268 4249 skip_move: ;
4269 4250 #endif
4270 4251 } else if (xop >= 0x20 && xop < 0x24) {
4271   - if (gen_trap_ifnofpu(dc))
  4252 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
4272 4253 goto jmp_insn;
4273 4254 switch (xop) {
4274 4255 case 0x20: /* load fpreg */
4275   - gen_op_check_align_T0_3();
  4256 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4276 4257 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
4277 4258 tcg_gen_st_i32(cpu_tmp32, cpu_env,
4278 4259 offsetof(CPUState, fpr[rd]));
4279 4260 break;
4280 4261 case 0x21: /* load fsr */
4281   - gen_op_check_align_T0_3();
  4262 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4282 4263 tcg_gen_qemu_ld32u(cpu_tmp32, cpu_T[0], dc->mem_idx);
4283 4264 tcg_gen_st_i32(cpu_tmp32, cpu_env,
4284 4265 offsetof(CPUState, ft0));
... ... @@ -4286,7 +4267,7 @@ static void disas_sparc_insn(DisasContext * dc)
4286 4267 break;
4287 4268 case 0x22: /* load quad fpreg */
4288 4269 #if defined(CONFIG_USER_ONLY)
4289   - gen_op_check_align_T0_7();
  4270 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
4290 4271 gen_op_ldst(ldqf);
4291 4272 gen_op_store_QT0_fpr(QFPREG(rd));
4292 4273 break;
... ... @@ -4294,7 +4275,7 @@ static void disas_sparc_insn(DisasContext * dc)
4294 4275 goto nfpu_insn;
4295 4276 #endif
4296 4277 case 0x23: /* load double fpreg */
4297   - gen_op_check_align_T0_7();
  4278 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
4298 4279 gen_op_ldst(lddf);
4299 4280 gen_op_store_DT0_fpr(DFPREG(rd));
4300 4281 break;
... ... @@ -4306,7 +4287,7 @@ static void disas_sparc_insn(DisasContext * dc)
4306 4287 gen_movl_reg_TN(rd, cpu_T[1]);
4307 4288 switch (xop) {
4308 4289 case 0x4: /* store word */
4309   - gen_op_check_align_T0_3();
  4290 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4310 4291 ABI32_MASK(cpu_T[0]);
4311 4292 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], dc->mem_idx);
4312 4293 break;
... ... @@ -4315,7 +4296,7 @@ static void disas_sparc_insn(DisasContext * dc)
4315 4296 tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], dc->mem_idx);
4316 4297 break;
4317 4298 case 0x6: /* store halfword */
4318   - gen_op_check_align_T0_1();
  4299 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(1));
4319 4300 ABI32_MASK(cpu_T[0]);
4320 4301 tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], dc->mem_idx);
4321 4302 break;
... ... @@ -4326,7 +4307,7 @@ static void disas_sparc_insn(DisasContext * dc)
4326 4307 else {
4327 4308 TCGv r_low;
4328 4309  
4329   - gen_op_check_align_T0_7();
  4310 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
4330 4311 r_low = tcg_temp_new(TCG_TYPE_I32);
4331 4312 gen_movl_reg_TN(rd + 1, r_low);
4332 4313 tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_T[1],
... ... @@ -4334,8 +4315,8 @@ static void disas_sparc_insn(DisasContext * dc)
4334 4315 tcg_gen_qemu_st64(cpu_tmp64, cpu_T[0], dc->mem_idx);
4335 4316 }
4336 4317 #else /* __i386__ */
4337   - gen_op_check_align_T0_7();
4338   - flush_T2(dc);
  4318 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
  4319 + flush_cond(dc, cpu_T[2]);
4339 4320 gen_movl_reg_TN(rd + 1, cpu_T[2]);
4340 4321 gen_op_ldst(std);
4341 4322 #endif /* __i386__ */
... ... @@ -4348,8 +4329,8 @@ static void disas_sparc_insn(DisasContext * dc)
4348 4329 if (!supervisor(dc))
4349 4330 goto priv_insn;
4350 4331 #endif
4351   - gen_op_check_align_T0_3();
4352   - gen_st_asi(insn, 4);
  4332 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
  4333 + gen_st_asi(cpu_T[1], cpu_T[0], insn, 4);
4353 4334 break;
4354 4335 case 0x15: /* store byte alternate */
4355 4336 #ifndef TARGET_SPARC64
... ... @@ -4358,7 +4339,7 @@ static void disas_sparc_insn(DisasContext * dc)
4358 4339 if (!supervisor(dc))
4359 4340 goto priv_insn;
4360 4341 #endif
4361   - gen_st_asi(insn, 1);
  4342 + gen_st_asi(cpu_T[1], cpu_T[0], insn, 1);
4362 4343 break;
4363 4344 case 0x16: /* store halfword alternate */
4364 4345 #ifndef TARGET_SPARC64
... ... @@ -4367,8 +4348,8 @@ static void disas_sparc_insn(DisasContext * dc)
4367 4348 if (!supervisor(dc))
4368 4349 goto priv_insn;
4369 4350 #endif
4370   - gen_op_check_align_T0_1();
4371   - gen_st_asi(insn, 2);
  4351 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(1));
  4352 + gen_st_asi(cpu_T[1], cpu_T[0], insn, 2);
4372 4353 break;
4373 4354 case 0x17: /* store double word alternate */
4374 4355 #ifndef TARGET_SPARC64
... ... @@ -4380,38 +4361,38 @@ static void disas_sparc_insn(DisasContext * dc)
4380 4361 if (rd & 1)
4381 4362 goto illegal_insn;
4382 4363 else {
4383   - gen_op_check_align_T0_7();
4384   - gen_stda_asi(insn, rd);
  4364 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
  4365 + gen_stda_asi(cpu_T[1], cpu_T[0], insn, rd);
4385 4366 }
4386 4367 break;
4387 4368 #endif
4388 4369 #ifdef TARGET_SPARC64
4389 4370 case 0x0e: /* V9 stx */
4390   - gen_op_check_align_T0_7();
  4371 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
4391 4372 ABI32_MASK(cpu_T[0]);
4392 4373 tcg_gen_qemu_st64(cpu_T[1], cpu_T[0], dc->mem_idx);
4393 4374 break;
4394 4375 case 0x1e: /* V9 stxa */
4395   - gen_op_check_align_T0_7();
4396   - gen_st_asi(insn, 8);
  4376 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
  4377 + gen_st_asi(cpu_T[1], cpu_T[0], insn, 8);
4397 4378 break;
4398 4379 #endif
4399 4380 default:
4400 4381 goto illegal_insn;
4401 4382 }
4402 4383 } else if (xop > 0x23 && xop < 0x28) {
4403   - if (gen_trap_ifnofpu(dc))
  4384 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
4404 4385 goto jmp_insn;
4405 4386 switch (xop) {
4406 4387 case 0x24: /* store fpreg */
4407   - gen_op_check_align_T0_3();
  4388 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4408 4389 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4409 4390 offsetof(CPUState, fpr[rd]));
4410 4391 tcg_gen_qemu_st32(cpu_tmp32, cpu_T[0], dc->mem_idx);
4411 4392 break;
4412 4393 case 0x25: /* stfsr, V9 stxfsr */
4413 4394 #ifdef CONFIG_USER_ONLY
4414   - gen_op_check_align_T0_3();
  4395 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4415 4396 #endif
4416 4397 tcg_gen_helper_0_0(helper_stfsr);
4417 4398 tcg_gen_ld_i32(cpu_tmp32, cpu_env,
... ... @@ -4422,7 +4403,7 @@ static void disas_sparc_insn(DisasContext * dc)
4422 4403 #ifdef TARGET_SPARC64
4423 4404 #if defined(CONFIG_USER_ONLY)
4424 4405 /* V9 stqf, store quad fpreg */
4425   - gen_op_check_align_T0_7();
  4406 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
4426 4407 gen_op_load_fpr_QT0(QFPREG(rd));
4427 4408 gen_op_ldst(stqf);
4428 4409 break;
... ... @@ -4436,13 +4417,13 @@ static void disas_sparc_insn(DisasContext * dc)
4436 4417 #else
4437 4418 if (!supervisor(dc))
4438 4419 goto priv_insn;
4439   - if (gen_trap_ifnofpu(dc))
  4420 + if (gen_trap_ifnofpu(dc, cpu_T[2]))
4440 4421 goto jmp_insn;
4441 4422 goto nfq_insn;
4442 4423 #endif
4443 4424 #endif
4444 4425 case 0x27:
4445   - gen_op_check_align_T0_7();
  4426 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
4446 4427 gen_op_load_fpr_DT0(DFPREG(rd));
4447 4428 gen_op_ldst(stdf);
4448 4429 break;
... ... @@ -4453,32 +4434,32 @@ static void disas_sparc_insn(DisasContext * dc)
4453 4434 switch (xop) {
4454 4435 #ifdef TARGET_SPARC64
4455 4436 case 0x34: /* V9 stfa */
4456   - gen_op_check_align_T0_3();
  4437 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4457 4438 gen_op_load_fpr_FT0(rd);
4458   - gen_stf_asi(insn, 4, rd);
  4439 + gen_stf_asi(cpu_T[0], insn, 4, rd);
4459 4440 break;
4460 4441 case 0x36: /* V9 stqfa */
4461 4442 #if defined(CONFIG_USER_ONLY)
4462   - gen_op_check_align_T0_7();
  4443 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
4463 4444 gen_op_load_fpr_QT0(QFPREG(rd));
4464   - gen_stf_asi(insn, 16, QFPREG(rd));
  4445 + gen_stf_asi(cpu_T[0], insn, 16, QFPREG(rd));
4465 4446 break;
4466 4447 #else
4467 4448 goto nfpu_insn;
4468 4449 #endif
4469 4450 case 0x37: /* V9 stdfa */
4470   - gen_op_check_align_T0_3();
  4451 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
4471 4452 gen_op_load_fpr_DT0(DFPREG(rd));
4472   - gen_stf_asi(insn, 8, DFPREG(rd));
  4453 + gen_stf_asi(cpu_T[0], insn, 8, DFPREG(rd));
4473 4454 break;
4474 4455 case 0x3c: /* V9 casa */
4475   - gen_op_check_align_T0_3();
4476   - gen_cas_asi(insn, rd);
  4456 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(3));
  4457 + gen_cas_asi(cpu_T[1], cpu_T[0], cpu_T[1], insn, rd);
4477 4458 gen_movl_TN_reg(rd, cpu_T[1]);
4478 4459 break;
4479 4460 case 0x3e: /* V9 casxa */
4480   - gen_op_check_align_T0_7();
4481   - gen_casx_asi(insn, rd);
  4461 + tcg_gen_helper_0_2(helper_check_align, cpu_T[0], tcg_const_i32(7));
  4462 + gen_casx_asi(cpu_T[1], cpu_T[0], cpu_T[1], insn, rd);
4482 4463 gen_movl_TN_reg(rd, cpu_T[1]);
4483 4464 break;
4484 4465 #else
... ... @@ -4512,24 +4493,24 @@ static void disas_sparc_insn(DisasContext * dc)
4512 4493 jmp_insn:
4513 4494 return;
4514 4495 illegal_insn:
4515   - save_state(dc);
  4496 + save_state(dc, cpu_T[2]);
4516 4497 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_ILL_INSN));
4517 4498 dc->is_br = 1;
4518 4499 return;
4519 4500 #if !defined(CONFIG_USER_ONLY)
4520 4501 priv_insn:
4521   - save_state(dc);
  4502 + save_state(dc, cpu_T[2]);
4522 4503 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_PRIV_INSN));
4523 4504 dc->is_br = 1;
4524 4505 return;
4525 4506 nfpu_insn:
4526   - save_state(dc);
  4507 + save_state(dc, cpu_T[2]);
4527 4508 gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4528 4509 dc->is_br = 1;
4529 4510 return;
4530 4511 #ifndef TARGET_SPARC64
4531 4512 nfq_insn:
4532   - save_state(dc);
  4513 + save_state(dc, cpu_T[2]);
4533 4514 gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4534 4515 dc->is_br = 1;
4535 4516 return;
... ... @@ -4537,7 +4518,7 @@ static void disas_sparc_insn(DisasContext * dc)
4537 4518 #endif
4538 4519 #ifndef TARGET_SPARC64
4539 4520 ncp_insn:
4540   - save_state(dc);
  4521 + save_state(dc, cpu_T[2]);
4541 4522 tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NCP_INSN));
4542 4523 dc->is_br = 1;
4543 4524 return;
... ... @@ -4575,7 +4556,7 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4575 4556 for(j = 0; j < env->nb_breakpoints; j++) {
4576 4557 if (env->breakpoints[j] == dc->pc) {
4577 4558 if (dc->pc != pc_start)
4578   - save_state(dc);
  4559 + save_state(dc, cpu_T[2]);
4579 4560 tcg_gen_helper_0_0(helper_debug);
4580 4561 tcg_gen_exit_tb(0);
4581 4562 dc->is_br = 1;
... ... @@ -4627,7 +4608,7 @@ static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4627 4608 } else {
4628 4609 if (dc->pc != DYNAMIC_PC)
4629 4610 tcg_gen_movi_tl(cpu_pc, dc->pc);
4630   - save_npc(dc);
  4611 + save_npc(dc, cpu_T[2]);
4631 4612 tcg_gen_exit_tb(0);
4632 4613 }
4633 4614 }
... ...