Commit ce5b3c3d461b35c23efa038c9c9897ca8e91d023
1 parent
2f5680ee
Split icc and xcc flag calculations
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4109 c046a42c-6fe2-441c-8c8c-71466251a162
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181 additions
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135 deletions
target-sparc/translate.c
... | ... | @@ -306,13 +306,17 @@ static inline void gen_mov_reg_C(TCGv reg, TCGv src) |
306 | 306 | tcg_gen_andi_tl(reg, reg, 0x1); |
307 | 307 | } |
308 | 308 | |
309 | -static inline void gen_cc_clear(void) | |
309 | +static inline void gen_cc_clear_icc(void) | |
310 | 310 | { |
311 | 311 | tcg_gen_movi_i32(cpu_psr, 0); |
312 | +} | |
313 | + | |
312 | 314 | #ifdef TARGET_SPARC64 |
315 | +static inline void gen_cc_clear_xcc(void) | |
316 | +{ | |
313 | 317 | tcg_gen_movi_i32(cpu_xcc, 0); |
314 | -#endif | |
315 | 318 | } |
319 | +#endif | |
316 | 320 | |
317 | 321 | /* old op: |
318 | 322 | if (!T0) |
... | ... | @@ -320,7 +324,7 @@ static inline void gen_cc_clear(void) |
320 | 324 | if ((int32_t) T0 < 0) |
321 | 325 | env->psr |= PSR_NEG; |
322 | 326 | */ |
323 | -static inline void gen_cc_NZ(TCGv dst) | |
327 | +static inline void gen_cc_NZ_icc(TCGv dst) | |
324 | 328 | { |
325 | 329 | TCGv r_temp; |
326 | 330 | int l1, l2; |
... | ... | @@ -336,27 +340,29 @@ static inline void gen_cc_NZ(TCGv dst) |
336 | 340 | tcg_gen_brcond_tl(TCG_COND_GE, r_temp, tcg_const_tl(0), l2); |
337 | 341 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG); |
338 | 342 | gen_set_label(l2); |
343 | +} | |
344 | + | |
339 | 345 | #ifdef TARGET_SPARC64 |
340 | - { | |
341 | - int l3, l4; | |
342 | - | |
343 | - l3 = gen_new_label(); | |
344 | - l4 = gen_new_label(); | |
345 | - tcg_gen_brcond_tl(TCG_COND_NE, dst, tcg_const_tl(0), l3); | |
346 | - tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO); | |
347 | - gen_set_label(l3); | |
348 | - tcg_gen_brcond_tl(TCG_COND_GE, dst, tcg_const_tl(0), l4); | |
349 | - tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG); | |
350 | - gen_set_label(l4); | |
351 | - } | |
352 | -#endif | |
346 | +static inline void gen_cc_NZ_xcc(TCGv dst) | |
347 | +{ | |
348 | + int l1, l2; | |
349 | + | |
350 | + l1 = gen_new_label(); | |
351 | + l2 = gen_new_label(); | |
352 | + tcg_gen_brcond_tl(TCG_COND_NE, dst, tcg_const_tl(0), l1); | |
353 | + tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO); | |
354 | + gen_set_label(l1); | |
355 | + tcg_gen_brcond_tl(TCG_COND_GE, dst, tcg_const_tl(0), l2); | |
356 | + tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG); | |
357 | + gen_set_label(l2); | |
353 | 358 | } |
359 | +#endif | |
354 | 360 | |
355 | 361 | /* old op: |
356 | 362 | if (T0 < src1) |
357 | 363 | env->psr |= PSR_CARRY; |
358 | 364 | */ |
359 | -static inline void gen_cc_C_add(TCGv dst, TCGv src1) | |
365 | +static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1) | |
360 | 366 | { |
361 | 367 | TCGv r_temp; |
362 | 368 | int l1; |
... | ... | @@ -367,23 +373,25 @@ static inline void gen_cc_C_add(TCGv dst, TCGv src1) |
367 | 373 | tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1); |
368 | 374 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
369 | 375 | gen_set_label(l1); |
376 | +} | |
377 | + | |
370 | 378 | #ifdef TARGET_SPARC64 |
371 | - { | |
372 | - int l2; | |
379 | +static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1) | |
380 | +{ | |
381 | + int l1; | |
373 | 382 | |
374 | - l2 = gen_new_label(); | |
375 | - tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l2); | |
376 | - tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); | |
377 | - gen_set_label(l2); | |
378 | - } | |
379 | -#endif | |
383 | + l1 = gen_new_label(); | |
384 | + tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1); | |
385 | + tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); | |
386 | + gen_set_label(l1); | |
380 | 387 | } |
388 | +#endif | |
381 | 389 | |
382 | 390 | /* old op: |
383 | 391 | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) |
384 | 392 | env->psr |= PSR_OVF; |
385 | 393 | */ |
386 | -static inline void gen_cc_V_add(TCGv dst, TCGv src1, TCGv src2) | |
394 | +static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2) | |
387 | 395 | { |
388 | 396 | TCGv r_temp; |
389 | 397 | int l1; |
... | ... | @@ -399,23 +407,27 @@ static inline void gen_cc_V_add(TCGv dst, TCGv src1, TCGv src2) |
399 | 407 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); |
400 | 408 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
401 | 409 | gen_set_label(l1); |
410 | +} | |
411 | + | |
402 | 412 | #ifdef TARGET_SPARC64 |
403 | - { | |
404 | - int l2; | |
405 | - | |
406 | - l2 = gen_new_label(); | |
407 | - tcg_gen_xor_tl(r_temp, src1, src2); | |
408 | - tcg_gen_xori_tl(r_temp, r_temp, -1); | |
409 | - tcg_gen_xor_tl(cpu_tmp0, src1, dst); | |
410 | - tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
411 | - tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | |
412 | - tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2); | |
413 | - tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF); | |
414 | - gen_set_label(l2); | |
415 | - } | |
416 | -#endif | |
417 | - tcg_gen_discard_tl(r_temp); | |
413 | +static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2) | |
414 | +{ | |
415 | + TCGv r_temp; | |
416 | + int l1; | |
417 | + | |
418 | + l1 = gen_new_label(); | |
419 | + | |
420 | + r_temp = tcg_temp_new(TCG_TYPE_TL); | |
421 | + tcg_gen_xor_tl(r_temp, src1, src2); | |
422 | + tcg_gen_xori_tl(r_temp, r_temp, -1); | |
423 | + tcg_gen_xor_tl(cpu_tmp0, src1, dst); | |
424 | + tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
425 | + tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | |
426 | + tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); | |
427 | + tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF); | |
428 | + gen_set_label(l1); | |
418 | 429 | } |
430 | +#endif | |
419 | 431 | |
420 | 432 | static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) |
421 | 433 | { |
... | ... | @@ -433,22 +445,6 @@ static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) |
433 | 445 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); |
434 | 446 | tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF)); |
435 | 447 | gen_set_label(l1); |
436 | -#ifdef TARGET_SPARC64 | |
437 | - { | |
438 | - int l2; | |
439 | - | |
440 | - l2 = gen_new_label(); | |
441 | - tcg_gen_xor_tl(r_temp, src1, src2); | |
442 | - tcg_gen_xori_tl(r_temp, r_temp, -1); | |
443 | - tcg_gen_xor_tl(cpu_tmp0, src1, dst); | |
444 | - tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
445 | - tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | |
446 | - tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2); | |
447 | - tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF)); | |
448 | - gen_set_label(l2); | |
449 | - } | |
450 | -#endif | |
451 | - tcg_gen_discard_tl(r_temp); | |
452 | 448 | } |
453 | 449 | |
454 | 450 | static inline void gen_cc_V_tag(TCGv src1, TCGv src2) |
... | ... | @@ -479,10 +475,16 @@ static inline void gen_op_add_T1_T0_cc(void) |
479 | 475 | { |
480 | 476 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
481 | 477 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
482 | - gen_cc_clear(); | |
483 | - gen_cc_NZ(cpu_T[0]); | |
484 | - gen_cc_C_add(cpu_T[0], cpu_cc_src); | |
485 | - gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
478 | + gen_cc_clear_icc(); | |
479 | + gen_cc_NZ_icc(cpu_T[0]); | |
480 | + gen_cc_C_add_icc(cpu_T[0], cpu_cc_src); | |
481 | + gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
482 | +#ifdef TARGET_SPARC64 | |
483 | + gen_cc_clear_xcc(); | |
484 | + gen_cc_NZ_xcc(cpu_T[0]); | |
485 | + gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src); | |
486 | + gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
487 | +#endif | |
486 | 488 | } |
487 | 489 | |
488 | 490 | static inline void gen_op_addx_T1_T0_cc(void) |
... | ... | @@ -490,23 +492,38 @@ static inline void gen_op_addx_T1_T0_cc(void) |
490 | 492 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
491 | 493 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
492 | 494 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
493 | - gen_cc_clear(); | |
494 | - gen_cc_C_add(cpu_T[0], cpu_cc_src); | |
495 | + gen_cc_clear_icc(); | |
496 | + gen_cc_C_add_icc(cpu_T[0], cpu_cc_src); | |
497 | +#ifdef TARGET_SPARC64 | |
498 | + gen_cc_clear_xcc(); | |
499 | + gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src); | |
500 | +#endif | |
495 | 501 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
496 | - gen_cc_C_add(cpu_T[0], cpu_cc_src); | |
497 | - gen_cc_NZ(cpu_T[0]); | |
498 | - gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
502 | + gen_cc_NZ_icc(cpu_T[0]); | |
503 | + gen_cc_C_add_icc(cpu_T[0], cpu_cc_src); | |
504 | + gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
505 | +#ifdef TARGET_SPARC64 | |
506 | + gen_cc_NZ_xcc(cpu_T[0]); | |
507 | + gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src); | |
508 | + gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
509 | +#endif | |
499 | 510 | } |
500 | 511 | |
501 | 512 | static inline void gen_op_tadd_T1_T0_cc(void) |
502 | 513 | { |
503 | 514 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
504 | 515 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
505 | - gen_cc_clear(); | |
506 | - gen_cc_NZ(cpu_T[0]); | |
507 | - gen_cc_C_add(cpu_T[0], cpu_cc_src); | |
508 | - gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
516 | + gen_cc_clear_icc(); | |
517 | + gen_cc_NZ_icc(cpu_T[0]); | |
518 | + gen_cc_C_add_icc(cpu_T[0], cpu_cc_src); | |
519 | + gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
509 | 520 | gen_cc_V_tag(cpu_cc_src, cpu_T[1]); |
521 | +#ifdef TARGET_SPARC64 | |
522 | + gen_cc_clear_xcc(); | |
523 | + gen_cc_NZ_xcc(cpu_T[0]); | |
524 | + gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src); | |
525 | + gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
526 | +#endif | |
510 | 527 | } |
511 | 528 | |
512 | 529 | static inline void gen_op_tadd_T1_T0_ccTV(void) |
... | ... | @@ -515,16 +532,22 @@ static inline void gen_op_tadd_T1_T0_ccTV(void) |
515 | 532 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
516 | 533 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
517 | 534 | gen_add_tv(cpu_T[0], cpu_cc_src, cpu_T[1]); |
518 | - gen_cc_clear(); | |
519 | - gen_cc_NZ(cpu_T[0]); | |
520 | - gen_cc_C_add(cpu_T[0], cpu_cc_src); | |
535 | + gen_cc_clear_icc(); | |
536 | + gen_cc_NZ_icc(cpu_T[0]); | |
537 | + gen_cc_C_add_icc(cpu_T[0], cpu_cc_src); | |
538 | +#ifdef TARGET_SPARC64 | |
539 | + gen_cc_clear_xcc(); | |
540 | + gen_cc_NZ_xcc(cpu_T[0]); | |
541 | + gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src); | |
542 | + gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
543 | +#endif | |
521 | 544 | } |
522 | 545 | |
523 | 546 | /* old op: |
524 | 547 | if (src1 < T1) |
525 | 548 | env->psr |= PSR_CARRY; |
526 | 549 | */ |
527 | -static inline void gen_cc_C_sub(TCGv src1, TCGv src2) | |
550 | +static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2) | |
528 | 551 | { |
529 | 552 | TCGv r_temp1, r_temp2; |
530 | 553 | int l1; |
... | ... | @@ -537,23 +560,25 @@ static inline void gen_cc_C_sub(TCGv src1, TCGv src2) |
537 | 560 | tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); |
538 | 561 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
539 | 562 | gen_set_label(l1); |
563 | +} | |
564 | + | |
540 | 565 | #ifdef TARGET_SPARC64 |
541 | - { | |
542 | - int l2; | |
566 | +static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2) | |
567 | +{ | |
568 | + int l1; | |
543 | 569 | |
544 | - l2 = gen_new_label(); | |
545 | - tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l2); | |
546 | - tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); | |
547 | - gen_set_label(l2); | |
548 | - } | |
549 | -#endif | |
570 | + l1 = gen_new_label(); | |
571 | + tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1); | |
572 | + tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); | |
573 | + gen_set_label(l1); | |
550 | 574 | } |
575 | +#endif | |
551 | 576 | |
552 | 577 | /* old op: |
553 | 578 | if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31)) |
554 | 579 | env->psr |= PSR_OVF; |
555 | 580 | */ |
556 | -static inline void gen_cc_V_sub(TCGv dst, TCGv src1, TCGv src2) | |
581 | +static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2) | |
557 | 582 | { |
558 | 583 | TCGv r_temp; |
559 | 584 | int l1; |
... | ... | @@ -568,22 +593,26 @@ static inline void gen_cc_V_sub(TCGv dst, TCGv src1, TCGv src2) |
568 | 593 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); |
569 | 594 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
570 | 595 | gen_set_label(l1); |
596 | +} | |
597 | + | |
571 | 598 | #ifdef TARGET_SPARC64 |
572 | - { | |
573 | - int l2; | |
574 | - | |
575 | - l2 = gen_new_label(); | |
576 | - tcg_gen_xor_tl(r_temp, src1, src2); | |
577 | - tcg_gen_xor_tl(cpu_tmp0, src1, dst); | |
578 | - tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
579 | - tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | |
580 | - tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2); | |
581 | - tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF); | |
582 | - gen_set_label(l2); | |
583 | - } | |
584 | -#endif | |
585 | - tcg_gen_discard_tl(r_temp); | |
599 | +static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2) | |
600 | +{ | |
601 | + TCGv r_temp; | |
602 | + int l1; | |
603 | + | |
604 | + l1 = gen_new_label(); | |
605 | + | |
606 | + r_temp = tcg_temp_new(TCG_TYPE_TL); | |
607 | + tcg_gen_xor_tl(r_temp, src1, src2); | |
608 | + tcg_gen_xor_tl(cpu_tmp0, src1, dst); | |
609 | + tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
610 | + tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | |
611 | + tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); | |
612 | + tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF); | |
613 | + gen_set_label(l1); | |
586 | 614 | } |
615 | +#endif | |
587 | 616 | |
588 | 617 | static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) |
589 | 618 | { |
... | ... | @@ -600,20 +629,6 @@ static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) |
600 | 629 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); |
601 | 630 | tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF)); |
602 | 631 | gen_set_label(l1); |
603 | -#ifdef TARGET_SPARC64 | |
604 | - { | |
605 | - int l2; | |
606 | - | |
607 | - l2 = gen_new_label(); | |
608 | - tcg_gen_xor_tl(r_temp, src1, src2); | |
609 | - tcg_gen_xor_tl(cpu_tmp0, src1, dst); | |
610 | - tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | |
611 | - tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | |
612 | - tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2); | |
613 | - tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF)); | |
614 | - gen_set_label(l2); | |
615 | - } | |
616 | -#endif | |
617 | 632 | tcg_gen_discard_tl(r_temp); |
618 | 633 | } |
619 | 634 | |
... | ... | @@ -621,10 +636,16 @@ static inline void gen_op_sub_T1_T0_cc(void) |
621 | 636 | { |
622 | 637 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
623 | 638 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
624 | - gen_cc_clear(); | |
625 | - gen_cc_NZ(cpu_T[0]); | |
626 | - gen_cc_C_sub(cpu_cc_src, cpu_T[1]); | |
627 | - gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
639 | + gen_cc_clear_icc(); | |
640 | + gen_cc_NZ_icc(cpu_T[0]); | |
641 | + gen_cc_C_sub_icc(cpu_cc_src, cpu_T[1]); | |
642 | + gen_cc_V_sub_icc(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
643 | +#ifdef TARGET_SPARC64 | |
644 | + gen_cc_clear_xcc(); | |
645 | + gen_cc_NZ_xcc(cpu_T[0]); | |
646 | + gen_cc_C_sub_xcc(cpu_cc_src, cpu_T[1]); | |
647 | + gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
648 | +#endif | |
628 | 649 | } |
629 | 650 | |
630 | 651 | static inline void gen_op_subx_T1_T0_cc(void) |
... | ... | @@ -632,23 +653,38 @@ static inline void gen_op_subx_T1_T0_cc(void) |
632 | 653 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
633 | 654 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
634 | 655 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
635 | - gen_cc_clear(); | |
636 | - gen_cc_C_sub(cpu_T[0], cpu_cc_src); | |
656 | + gen_cc_clear_icc(); | |
657 | + gen_cc_C_sub_icc(cpu_T[0], cpu_cc_src); | |
658 | +#ifdef TARGET_SPARC64 | |
659 | + gen_cc_clear_xcc(); | |
660 | + gen_cc_C_sub_xcc(cpu_T[0], cpu_cc_src); | |
661 | +#endif | |
637 | 662 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
638 | - gen_cc_C_sub(cpu_T[0], cpu_cc_src); | |
639 | - gen_cc_NZ(cpu_T[0]); | |
640 | - gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
663 | + gen_cc_NZ_icc(cpu_T[0]); | |
664 | + gen_cc_C_sub_icc(cpu_T[0], cpu_cc_src); | |
665 | + gen_cc_V_sub_icc(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
666 | +#ifdef TARGET_SPARC64 | |
667 | + gen_cc_NZ_xcc(cpu_T[0]); | |
668 | + gen_cc_C_sub_xcc(cpu_T[0], cpu_cc_src); | |
669 | + gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
670 | +#endif | |
641 | 671 | } |
642 | 672 | |
643 | 673 | static inline void gen_op_tsub_T1_T0_cc(void) |
644 | 674 | { |
645 | 675 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
646 | 676 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
647 | - gen_cc_clear(); | |
648 | - gen_cc_NZ(cpu_T[0]); | |
649 | - gen_cc_C_sub(cpu_cc_src, cpu_T[1]); | |
650 | - gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
677 | + gen_cc_clear_icc(); | |
678 | + gen_cc_NZ_icc(cpu_T[0]); | |
679 | + gen_cc_C_sub_icc(cpu_cc_src, cpu_T[1]); | |
680 | + gen_cc_V_sub_icc(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
651 | 681 | gen_cc_V_tag(cpu_cc_src, cpu_T[1]); |
682 | +#ifdef TARGET_SPARC64 | |
683 | + gen_cc_clear_xcc(); | |
684 | + gen_cc_NZ_xcc(cpu_T[0]); | |
685 | + gen_cc_C_sub_xcc(cpu_cc_src, cpu_T[1]); | |
686 | + gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
687 | +#endif | |
652 | 688 | } |
653 | 689 | |
654 | 690 | static inline void gen_op_tsub_T1_T0_ccTV(void) |
... | ... | @@ -657,9 +693,15 @@ static inline void gen_op_tsub_T1_T0_ccTV(void) |
657 | 693 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
658 | 694 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
659 | 695 | gen_sub_tv(cpu_T[0], cpu_cc_src, cpu_T[1]); |
660 | - gen_cc_clear(); | |
661 | - gen_cc_NZ(cpu_T[0]); | |
662 | - gen_cc_C_sub(cpu_cc_src, cpu_T[1]); | |
696 | + gen_cc_clear_icc(); | |
697 | + gen_cc_NZ_icc(cpu_T[0]); | |
698 | + gen_cc_C_sub_icc(cpu_cc_src, cpu_T[1]); | |
699 | +#ifdef TARGET_SPARC64 | |
700 | + gen_cc_clear_xcc(); | |
701 | + gen_cc_NZ_xcc(cpu_T[0]); | |
702 | + gen_cc_C_sub_xcc(cpu_cc_src, cpu_T[1]); | |
703 | + gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); | |
704 | +#endif | |
663 | 705 | } |
664 | 706 | |
665 | 707 | static inline void gen_op_mulscc_T1_T0(void) |
... | ... | @@ -711,10 +753,10 @@ static inline void gen_op_mulscc_T1_T0(void) |
711 | 753 | tcg_gen_add_tl(cpu_T[0], cpu_cc_src, cpu_cc_src2); |
712 | 754 | tcg_gen_discard_tl(r_temp); |
713 | 755 | |
714 | - gen_cc_clear(); | |
715 | - gen_cc_NZ(cpu_T[0]); | |
716 | - gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_cc_src2); | |
717 | - gen_cc_C_add(cpu_T[0], cpu_cc_src); | |
756 | + gen_cc_clear_icc(); | |
757 | + gen_cc_NZ_icc(cpu_T[0]); | |
758 | + gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_cc_src2); | |
759 | + gen_cc_C_add_icc(cpu_T[0], cpu_cc_src); | |
718 | 760 | } |
719 | 761 | |
720 | 762 | static inline void gen_op_umul_T1_T0(void) |
... | ... | @@ -797,8 +839,8 @@ static inline void gen_op_div_cc(void) |
797 | 839 | { |
798 | 840 | int l1; |
799 | 841 | |
800 | - gen_cc_clear(); | |
801 | - gen_cc_NZ(cpu_T[0]); | |
842 | + gen_cc_clear_icc(); | |
843 | + gen_cc_NZ_icc(cpu_T[0]); | |
802 | 844 | l1 = gen_new_label(); |
803 | 845 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2)); |
804 | 846 | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1); |
... | ... | @@ -808,8 +850,12 @@ static inline void gen_op_div_cc(void) |
808 | 850 | |
809 | 851 | static inline void gen_op_logic_T0_cc(void) |
810 | 852 | { |
811 | - gen_cc_clear(); | |
812 | - gen_cc_NZ(cpu_T[0]); | |
853 | + gen_cc_clear_icc(); | |
854 | + gen_cc_NZ_icc(cpu_T[0]); | |
855 | +#ifdef TARGET_SPARC64 | |
856 | + gen_cc_clear_xcc(); | |
857 | + gen_cc_NZ_xcc(cpu_T[0]); | |
858 | +#endif | |
813 | 859 | } |
814 | 860 | |
815 | 861 | // 1 | ... | ... |