Commit ce5b3c3d461b35c23efa038c9c9897ca8e91d023
1 parent
2f5680ee
Split icc and xcc flag calculations
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4109 c046a42c-6fe2-441c-8c8c-71466251a162
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1 changed file
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181 additions
and
135 deletions
target-sparc/translate.c
| @@ -306,13 +306,17 @@ static inline void gen_mov_reg_C(TCGv reg, TCGv src) | @@ -306,13 +306,17 @@ static inline void gen_mov_reg_C(TCGv reg, TCGv src) | ||
| 306 | tcg_gen_andi_tl(reg, reg, 0x1); | 306 | tcg_gen_andi_tl(reg, reg, 0x1); |
| 307 | } | 307 | } |
| 308 | 308 | ||
| 309 | -static inline void gen_cc_clear(void) | 309 | +static inline void gen_cc_clear_icc(void) |
| 310 | { | 310 | { |
| 311 | tcg_gen_movi_i32(cpu_psr, 0); | 311 | tcg_gen_movi_i32(cpu_psr, 0); |
| 312 | +} | ||
| 313 | + | ||
| 312 | #ifdef TARGET_SPARC64 | 314 | #ifdef TARGET_SPARC64 |
| 315 | +static inline void gen_cc_clear_xcc(void) | ||
| 316 | +{ | ||
| 313 | tcg_gen_movi_i32(cpu_xcc, 0); | 317 | tcg_gen_movi_i32(cpu_xcc, 0); |
| 314 | -#endif | ||
| 315 | } | 318 | } |
| 319 | +#endif | ||
| 316 | 320 | ||
| 317 | /* old op: | 321 | /* old op: |
| 318 | if (!T0) | 322 | if (!T0) |
| @@ -320,7 +324,7 @@ static inline void gen_cc_clear(void) | @@ -320,7 +324,7 @@ static inline void gen_cc_clear(void) | ||
| 320 | if ((int32_t) T0 < 0) | 324 | if ((int32_t) T0 < 0) |
| 321 | env->psr |= PSR_NEG; | 325 | env->psr |= PSR_NEG; |
| 322 | */ | 326 | */ |
| 323 | -static inline void gen_cc_NZ(TCGv dst) | 327 | +static inline void gen_cc_NZ_icc(TCGv dst) |
| 324 | { | 328 | { |
| 325 | TCGv r_temp; | 329 | TCGv r_temp; |
| 326 | int l1, l2; | 330 | int l1, l2; |
| @@ -336,27 +340,29 @@ static inline void gen_cc_NZ(TCGv dst) | @@ -336,27 +340,29 @@ static inline void gen_cc_NZ(TCGv dst) | ||
| 336 | tcg_gen_brcond_tl(TCG_COND_GE, r_temp, tcg_const_tl(0), l2); | 340 | tcg_gen_brcond_tl(TCG_COND_GE, r_temp, tcg_const_tl(0), l2); |
| 337 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG); | 341 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG); |
| 338 | gen_set_label(l2); | 342 | gen_set_label(l2); |
| 343 | +} | ||
| 344 | + | ||
| 339 | #ifdef TARGET_SPARC64 | 345 | #ifdef TARGET_SPARC64 |
| 340 | - { | ||
| 341 | - int l3, l4; | ||
| 342 | - | ||
| 343 | - l3 = gen_new_label(); | ||
| 344 | - l4 = gen_new_label(); | ||
| 345 | - tcg_gen_brcond_tl(TCG_COND_NE, dst, tcg_const_tl(0), l3); | ||
| 346 | - tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO); | ||
| 347 | - gen_set_label(l3); | ||
| 348 | - tcg_gen_brcond_tl(TCG_COND_GE, dst, tcg_const_tl(0), l4); | ||
| 349 | - tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG); | ||
| 350 | - gen_set_label(l4); | ||
| 351 | - } | ||
| 352 | -#endif | 346 | +static inline void gen_cc_NZ_xcc(TCGv dst) |
| 347 | +{ | ||
| 348 | + int l1, l2; | ||
| 349 | + | ||
| 350 | + l1 = gen_new_label(); | ||
| 351 | + l2 = gen_new_label(); | ||
| 352 | + tcg_gen_brcond_tl(TCG_COND_NE, dst, tcg_const_tl(0), l1); | ||
| 353 | + tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO); | ||
| 354 | + gen_set_label(l1); | ||
| 355 | + tcg_gen_brcond_tl(TCG_COND_GE, dst, tcg_const_tl(0), l2); | ||
| 356 | + tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG); | ||
| 357 | + gen_set_label(l2); | ||
| 353 | } | 358 | } |
| 359 | +#endif | ||
| 354 | 360 | ||
| 355 | /* old op: | 361 | /* old op: |
| 356 | if (T0 < src1) | 362 | if (T0 < src1) |
| 357 | env->psr |= PSR_CARRY; | 363 | env->psr |= PSR_CARRY; |
| 358 | */ | 364 | */ |
| 359 | -static inline void gen_cc_C_add(TCGv dst, TCGv src1) | 365 | +static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1) |
| 360 | { | 366 | { |
| 361 | TCGv r_temp; | 367 | TCGv r_temp; |
| 362 | int l1; | 368 | int l1; |
| @@ -367,23 +373,25 @@ static inline void gen_cc_C_add(TCGv dst, TCGv src1) | @@ -367,23 +373,25 @@ static inline void gen_cc_C_add(TCGv dst, TCGv src1) | ||
| 367 | tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1); | 373 | tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1); |
| 368 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); | 374 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
| 369 | gen_set_label(l1); | 375 | gen_set_label(l1); |
| 376 | +} | ||
| 377 | + | ||
| 370 | #ifdef TARGET_SPARC64 | 378 | #ifdef TARGET_SPARC64 |
| 371 | - { | ||
| 372 | - int l2; | 379 | +static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1) |
| 380 | +{ | ||
| 381 | + int l1; | ||
| 373 | 382 | ||
| 374 | - l2 = gen_new_label(); | ||
| 375 | - tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l2); | ||
| 376 | - tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); | ||
| 377 | - gen_set_label(l2); | ||
| 378 | - } | ||
| 379 | -#endif | 383 | + l1 = gen_new_label(); |
| 384 | + tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1); | ||
| 385 | + tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); | ||
| 386 | + gen_set_label(l1); | ||
| 380 | } | 387 | } |
| 388 | +#endif | ||
| 381 | 389 | ||
| 382 | /* old op: | 390 | /* old op: |
| 383 | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) | 391 | if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31)) |
| 384 | env->psr |= PSR_OVF; | 392 | env->psr |= PSR_OVF; |
| 385 | */ | 393 | */ |
| 386 | -static inline void gen_cc_V_add(TCGv dst, TCGv src1, TCGv src2) | 394 | +static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2) |
| 387 | { | 395 | { |
| 388 | TCGv r_temp; | 396 | TCGv r_temp; |
| 389 | int l1; | 397 | int l1; |
| @@ -399,23 +407,27 @@ static inline void gen_cc_V_add(TCGv dst, TCGv src1, TCGv src2) | @@ -399,23 +407,27 @@ static inline void gen_cc_V_add(TCGv dst, TCGv src1, TCGv src2) | ||
| 399 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); | 407 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); |
| 400 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); | 408 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
| 401 | gen_set_label(l1); | 409 | gen_set_label(l1); |
| 410 | +} | ||
| 411 | + | ||
| 402 | #ifdef TARGET_SPARC64 | 412 | #ifdef TARGET_SPARC64 |
| 403 | - { | ||
| 404 | - int l2; | ||
| 405 | - | ||
| 406 | - l2 = gen_new_label(); | ||
| 407 | - tcg_gen_xor_tl(r_temp, src1, src2); | ||
| 408 | - tcg_gen_xori_tl(r_temp, r_temp, -1); | ||
| 409 | - tcg_gen_xor_tl(cpu_tmp0, src1, dst); | ||
| 410 | - tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | ||
| 411 | - tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | ||
| 412 | - tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2); | ||
| 413 | - tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF); | ||
| 414 | - gen_set_label(l2); | ||
| 415 | - } | ||
| 416 | -#endif | ||
| 417 | - tcg_gen_discard_tl(r_temp); | 413 | +static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2) |
| 414 | +{ | ||
| 415 | + TCGv r_temp; | ||
| 416 | + int l1; | ||
| 417 | + | ||
| 418 | + l1 = gen_new_label(); | ||
| 419 | + | ||
| 420 | + r_temp = tcg_temp_new(TCG_TYPE_TL); | ||
| 421 | + tcg_gen_xor_tl(r_temp, src1, src2); | ||
| 422 | + tcg_gen_xori_tl(r_temp, r_temp, -1); | ||
| 423 | + tcg_gen_xor_tl(cpu_tmp0, src1, dst); | ||
| 424 | + tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | ||
| 425 | + tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | ||
| 426 | + tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); | ||
| 427 | + tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF); | ||
| 428 | + gen_set_label(l1); | ||
| 418 | } | 429 | } |
| 430 | +#endif | ||
| 419 | 431 | ||
| 420 | static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) | 432 | static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) |
| 421 | { | 433 | { |
| @@ -433,22 +445,6 @@ static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) | @@ -433,22 +445,6 @@ static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) | ||
| 433 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); | 445 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); |
| 434 | tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF)); | 446 | tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF)); |
| 435 | gen_set_label(l1); | 447 | gen_set_label(l1); |
| 436 | -#ifdef TARGET_SPARC64 | ||
| 437 | - { | ||
| 438 | - int l2; | ||
| 439 | - | ||
| 440 | - l2 = gen_new_label(); | ||
| 441 | - tcg_gen_xor_tl(r_temp, src1, src2); | ||
| 442 | - tcg_gen_xori_tl(r_temp, r_temp, -1); | ||
| 443 | - tcg_gen_xor_tl(cpu_tmp0, src1, dst); | ||
| 444 | - tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | ||
| 445 | - tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | ||
| 446 | - tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2); | ||
| 447 | - tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF)); | ||
| 448 | - gen_set_label(l2); | ||
| 449 | - } | ||
| 450 | -#endif | ||
| 451 | - tcg_gen_discard_tl(r_temp); | ||
| 452 | } | 448 | } |
| 453 | 449 | ||
| 454 | static inline void gen_cc_V_tag(TCGv src1, TCGv src2) | 450 | static inline void gen_cc_V_tag(TCGv src1, TCGv src2) |
| @@ -479,10 +475,16 @@ static inline void gen_op_add_T1_T0_cc(void) | @@ -479,10 +475,16 @@ static inline void gen_op_add_T1_T0_cc(void) | ||
| 479 | { | 475 | { |
| 480 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | 476 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
| 481 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | 477 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
| 482 | - gen_cc_clear(); | ||
| 483 | - gen_cc_NZ(cpu_T[0]); | ||
| 484 | - gen_cc_C_add(cpu_T[0], cpu_cc_src); | ||
| 485 | - gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]); | 478 | + gen_cc_clear_icc(); |
| 479 | + gen_cc_NZ_icc(cpu_T[0]); | ||
| 480 | + gen_cc_C_add_icc(cpu_T[0], cpu_cc_src); | ||
| 481 | + gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_T[1]); | ||
| 482 | +#ifdef TARGET_SPARC64 | ||
| 483 | + gen_cc_clear_xcc(); | ||
| 484 | + gen_cc_NZ_xcc(cpu_T[0]); | ||
| 485 | + gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src); | ||
| 486 | + gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); | ||
| 487 | +#endif | ||
| 486 | } | 488 | } |
| 487 | 489 | ||
| 488 | static inline void gen_op_addx_T1_T0_cc(void) | 490 | static inline void gen_op_addx_T1_T0_cc(void) |
| @@ -490,23 +492,38 @@ static inline void gen_op_addx_T1_T0_cc(void) | @@ -490,23 +492,38 @@ static inline void gen_op_addx_T1_T0_cc(void) | ||
| 490 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | 492 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
| 491 | gen_mov_reg_C(cpu_tmp0, cpu_psr); | 493 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
| 492 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | 494 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
| 493 | - gen_cc_clear(); | ||
| 494 | - gen_cc_C_add(cpu_T[0], cpu_cc_src); | 495 | + gen_cc_clear_icc(); |
| 496 | + gen_cc_C_add_icc(cpu_T[0], cpu_cc_src); | ||
| 497 | +#ifdef TARGET_SPARC64 | ||
| 498 | + gen_cc_clear_xcc(); | ||
| 499 | + gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src); | ||
| 500 | +#endif | ||
| 495 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | 501 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
| 496 | - gen_cc_C_add(cpu_T[0], cpu_cc_src); | ||
| 497 | - gen_cc_NZ(cpu_T[0]); | ||
| 498 | - gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]); | 502 | + gen_cc_NZ_icc(cpu_T[0]); |
| 503 | + gen_cc_C_add_icc(cpu_T[0], cpu_cc_src); | ||
| 504 | + gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_T[1]); | ||
| 505 | +#ifdef TARGET_SPARC64 | ||
| 506 | + gen_cc_NZ_xcc(cpu_T[0]); | ||
| 507 | + gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src); | ||
| 508 | + gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); | ||
| 509 | +#endif | ||
| 499 | } | 510 | } |
| 500 | 511 | ||
| 501 | static inline void gen_op_tadd_T1_T0_cc(void) | 512 | static inline void gen_op_tadd_T1_T0_cc(void) |
| 502 | { | 513 | { |
| 503 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | 514 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
| 504 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | 515 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
| 505 | - gen_cc_clear(); | ||
| 506 | - gen_cc_NZ(cpu_T[0]); | ||
| 507 | - gen_cc_C_add(cpu_T[0], cpu_cc_src); | ||
| 508 | - gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_T[1]); | 516 | + gen_cc_clear_icc(); |
| 517 | + gen_cc_NZ_icc(cpu_T[0]); | ||
| 518 | + gen_cc_C_add_icc(cpu_T[0], cpu_cc_src); | ||
| 519 | + gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_T[1]); | ||
| 509 | gen_cc_V_tag(cpu_cc_src, cpu_T[1]); | 520 | gen_cc_V_tag(cpu_cc_src, cpu_T[1]); |
| 521 | +#ifdef TARGET_SPARC64 | ||
| 522 | + gen_cc_clear_xcc(); | ||
| 523 | + gen_cc_NZ_xcc(cpu_T[0]); | ||
| 524 | + gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src); | ||
| 525 | + gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); | ||
| 526 | +#endif | ||
| 510 | } | 527 | } |
| 511 | 528 | ||
| 512 | static inline void gen_op_tadd_T1_T0_ccTV(void) | 529 | static inline void gen_op_tadd_T1_T0_ccTV(void) |
| @@ -515,16 +532,22 @@ static inline void gen_op_tadd_T1_T0_ccTV(void) | @@ -515,16 +532,22 @@ static inline void gen_op_tadd_T1_T0_ccTV(void) | ||
| 515 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | 532 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
| 516 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | 533 | tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
| 517 | gen_add_tv(cpu_T[0], cpu_cc_src, cpu_T[1]); | 534 | gen_add_tv(cpu_T[0], cpu_cc_src, cpu_T[1]); |
| 518 | - gen_cc_clear(); | ||
| 519 | - gen_cc_NZ(cpu_T[0]); | ||
| 520 | - gen_cc_C_add(cpu_T[0], cpu_cc_src); | 535 | + gen_cc_clear_icc(); |
| 536 | + gen_cc_NZ_icc(cpu_T[0]); | ||
| 537 | + gen_cc_C_add_icc(cpu_T[0], cpu_cc_src); | ||
| 538 | +#ifdef TARGET_SPARC64 | ||
| 539 | + gen_cc_clear_xcc(); | ||
| 540 | + gen_cc_NZ_xcc(cpu_T[0]); | ||
| 541 | + gen_cc_C_add_xcc(cpu_T[0], cpu_cc_src); | ||
| 542 | + gen_cc_V_add_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); | ||
| 543 | +#endif | ||
| 521 | } | 544 | } |
| 522 | 545 | ||
| 523 | /* old op: | 546 | /* old op: |
| 524 | if (src1 < T1) | 547 | if (src1 < T1) |
| 525 | env->psr |= PSR_CARRY; | 548 | env->psr |= PSR_CARRY; |
| 526 | */ | 549 | */ |
| 527 | -static inline void gen_cc_C_sub(TCGv src1, TCGv src2) | 550 | +static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2) |
| 528 | { | 551 | { |
| 529 | TCGv r_temp1, r_temp2; | 552 | TCGv r_temp1, r_temp2; |
| 530 | int l1; | 553 | int l1; |
| @@ -537,23 +560,25 @@ static inline void gen_cc_C_sub(TCGv src1, TCGv src2) | @@ -537,23 +560,25 @@ static inline void gen_cc_C_sub(TCGv src1, TCGv src2) | ||
| 537 | tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); | 560 | tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); |
| 538 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); | 561 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY); |
| 539 | gen_set_label(l1); | 562 | gen_set_label(l1); |
| 563 | +} | ||
| 564 | + | ||
| 540 | #ifdef TARGET_SPARC64 | 565 | #ifdef TARGET_SPARC64 |
| 541 | - { | ||
| 542 | - int l2; | 566 | +static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2) |
| 567 | +{ | ||
| 568 | + int l1; | ||
| 543 | 569 | ||
| 544 | - l2 = gen_new_label(); | ||
| 545 | - tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l2); | ||
| 546 | - tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); | ||
| 547 | - gen_set_label(l2); | ||
| 548 | - } | ||
| 549 | -#endif | 570 | + l1 = gen_new_label(); |
| 571 | + tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1); | ||
| 572 | + tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY); | ||
| 573 | + gen_set_label(l1); | ||
| 550 | } | 574 | } |
| 575 | +#endif | ||
| 551 | 576 | ||
| 552 | /* old op: | 577 | /* old op: |
| 553 | if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31)) | 578 | if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31)) |
| 554 | env->psr |= PSR_OVF; | 579 | env->psr |= PSR_OVF; |
| 555 | */ | 580 | */ |
| 556 | -static inline void gen_cc_V_sub(TCGv dst, TCGv src1, TCGv src2) | 581 | +static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2) |
| 557 | { | 582 | { |
| 558 | TCGv r_temp; | 583 | TCGv r_temp; |
| 559 | int l1; | 584 | int l1; |
| @@ -568,22 +593,26 @@ static inline void gen_cc_V_sub(TCGv dst, TCGv src1, TCGv src2) | @@ -568,22 +593,26 @@ static inline void gen_cc_V_sub(TCGv dst, TCGv src1, TCGv src2) | ||
| 568 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); | 593 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); |
| 569 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); | 594 | tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF); |
| 570 | gen_set_label(l1); | 595 | gen_set_label(l1); |
| 596 | +} | ||
| 597 | + | ||
| 571 | #ifdef TARGET_SPARC64 | 598 | #ifdef TARGET_SPARC64 |
| 572 | - { | ||
| 573 | - int l2; | ||
| 574 | - | ||
| 575 | - l2 = gen_new_label(); | ||
| 576 | - tcg_gen_xor_tl(r_temp, src1, src2); | ||
| 577 | - tcg_gen_xor_tl(cpu_tmp0, src1, dst); | ||
| 578 | - tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | ||
| 579 | - tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | ||
| 580 | - tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2); | ||
| 581 | - tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF); | ||
| 582 | - gen_set_label(l2); | ||
| 583 | - } | ||
| 584 | -#endif | ||
| 585 | - tcg_gen_discard_tl(r_temp); | 599 | +static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2) |
| 600 | +{ | ||
| 601 | + TCGv r_temp; | ||
| 602 | + int l1; | ||
| 603 | + | ||
| 604 | + l1 = gen_new_label(); | ||
| 605 | + | ||
| 606 | + r_temp = tcg_temp_new(TCG_TYPE_TL); | ||
| 607 | + tcg_gen_xor_tl(r_temp, src1, src2); | ||
| 608 | + tcg_gen_xor_tl(cpu_tmp0, src1, dst); | ||
| 609 | + tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | ||
| 610 | + tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | ||
| 611 | + tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); | ||
| 612 | + tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF); | ||
| 613 | + gen_set_label(l1); | ||
| 586 | } | 614 | } |
| 615 | +#endif | ||
| 587 | 616 | ||
| 588 | static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) | 617 | static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) |
| 589 | { | 618 | { |
| @@ -600,20 +629,6 @@ static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) | @@ -600,20 +629,6 @@ static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) | ||
| 600 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); | 629 | tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1); |
| 601 | tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF)); | 630 | tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF)); |
| 602 | gen_set_label(l1); | 631 | gen_set_label(l1); |
| 603 | -#ifdef TARGET_SPARC64 | ||
| 604 | - { | ||
| 605 | - int l2; | ||
| 606 | - | ||
| 607 | - l2 = gen_new_label(); | ||
| 608 | - tcg_gen_xor_tl(r_temp, src1, src2); | ||
| 609 | - tcg_gen_xor_tl(cpu_tmp0, src1, dst); | ||
| 610 | - tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); | ||
| 611 | - tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63)); | ||
| 612 | - tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l2); | ||
| 613 | - tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF)); | ||
| 614 | - gen_set_label(l2); | ||
| 615 | - } | ||
| 616 | -#endif | ||
| 617 | tcg_gen_discard_tl(r_temp); | 632 | tcg_gen_discard_tl(r_temp); |
| 618 | } | 633 | } |
| 619 | 634 | ||
| @@ -621,10 +636,16 @@ static inline void gen_op_sub_T1_T0_cc(void) | @@ -621,10 +636,16 @@ static inline void gen_op_sub_T1_T0_cc(void) | ||
| 621 | { | 636 | { |
| 622 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | 637 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
| 623 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | 638 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
| 624 | - gen_cc_clear(); | ||
| 625 | - gen_cc_NZ(cpu_T[0]); | ||
| 626 | - gen_cc_C_sub(cpu_cc_src, cpu_T[1]); | ||
| 627 | - gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]); | 639 | + gen_cc_clear_icc(); |
| 640 | + gen_cc_NZ_icc(cpu_T[0]); | ||
| 641 | + gen_cc_C_sub_icc(cpu_cc_src, cpu_T[1]); | ||
| 642 | + gen_cc_V_sub_icc(cpu_T[0], cpu_cc_src, cpu_T[1]); | ||
| 643 | +#ifdef TARGET_SPARC64 | ||
| 644 | + gen_cc_clear_xcc(); | ||
| 645 | + gen_cc_NZ_xcc(cpu_T[0]); | ||
| 646 | + gen_cc_C_sub_xcc(cpu_cc_src, cpu_T[1]); | ||
| 647 | + gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); | ||
| 648 | +#endif | ||
| 628 | } | 649 | } |
| 629 | 650 | ||
| 630 | static inline void gen_op_subx_T1_T0_cc(void) | 651 | static inline void gen_op_subx_T1_T0_cc(void) |
| @@ -632,23 +653,38 @@ static inline void gen_op_subx_T1_T0_cc(void) | @@ -632,23 +653,38 @@ static inline void gen_op_subx_T1_T0_cc(void) | ||
| 632 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | 653 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
| 633 | gen_mov_reg_C(cpu_tmp0, cpu_psr); | 654 | gen_mov_reg_C(cpu_tmp0, cpu_psr); |
| 634 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp0); | 655 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp0); |
| 635 | - gen_cc_clear(); | ||
| 636 | - gen_cc_C_sub(cpu_T[0], cpu_cc_src); | 656 | + gen_cc_clear_icc(); |
| 657 | + gen_cc_C_sub_icc(cpu_T[0], cpu_cc_src); | ||
| 658 | +#ifdef TARGET_SPARC64 | ||
| 659 | + gen_cc_clear_xcc(); | ||
| 660 | + gen_cc_C_sub_xcc(cpu_T[0], cpu_cc_src); | ||
| 661 | +#endif | ||
| 637 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | 662 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
| 638 | - gen_cc_C_sub(cpu_T[0], cpu_cc_src); | ||
| 639 | - gen_cc_NZ(cpu_T[0]); | ||
| 640 | - gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]); | 663 | + gen_cc_NZ_icc(cpu_T[0]); |
| 664 | + gen_cc_C_sub_icc(cpu_T[0], cpu_cc_src); | ||
| 665 | + gen_cc_V_sub_icc(cpu_T[0], cpu_cc_src, cpu_T[1]); | ||
| 666 | +#ifdef TARGET_SPARC64 | ||
| 667 | + gen_cc_NZ_xcc(cpu_T[0]); | ||
| 668 | + gen_cc_C_sub_xcc(cpu_T[0], cpu_cc_src); | ||
| 669 | + gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); | ||
| 670 | +#endif | ||
| 641 | } | 671 | } |
| 642 | 672 | ||
| 643 | static inline void gen_op_tsub_T1_T0_cc(void) | 673 | static inline void gen_op_tsub_T1_T0_cc(void) |
| 644 | { | 674 | { |
| 645 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | 675 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
| 646 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | 676 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
| 647 | - gen_cc_clear(); | ||
| 648 | - gen_cc_NZ(cpu_T[0]); | ||
| 649 | - gen_cc_C_sub(cpu_cc_src, cpu_T[1]); | ||
| 650 | - gen_cc_V_sub(cpu_T[0], cpu_cc_src, cpu_T[1]); | 677 | + gen_cc_clear_icc(); |
| 678 | + gen_cc_NZ_icc(cpu_T[0]); | ||
| 679 | + gen_cc_C_sub_icc(cpu_cc_src, cpu_T[1]); | ||
| 680 | + gen_cc_V_sub_icc(cpu_T[0], cpu_cc_src, cpu_T[1]); | ||
| 651 | gen_cc_V_tag(cpu_cc_src, cpu_T[1]); | 681 | gen_cc_V_tag(cpu_cc_src, cpu_T[1]); |
| 682 | +#ifdef TARGET_SPARC64 | ||
| 683 | + gen_cc_clear_xcc(); | ||
| 684 | + gen_cc_NZ_xcc(cpu_T[0]); | ||
| 685 | + gen_cc_C_sub_xcc(cpu_cc_src, cpu_T[1]); | ||
| 686 | + gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); | ||
| 687 | +#endif | ||
| 652 | } | 688 | } |
| 653 | 689 | ||
| 654 | static inline void gen_op_tsub_T1_T0_ccTV(void) | 690 | static inline void gen_op_tsub_T1_T0_ccTV(void) |
| @@ -657,9 +693,15 @@ static inline void gen_op_tsub_T1_T0_ccTV(void) | @@ -657,9 +693,15 @@ static inline void gen_op_tsub_T1_T0_ccTV(void) | ||
| 657 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); | 693 | tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]); |
| 658 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); | 694 | tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]); |
| 659 | gen_sub_tv(cpu_T[0], cpu_cc_src, cpu_T[1]); | 695 | gen_sub_tv(cpu_T[0], cpu_cc_src, cpu_T[1]); |
| 660 | - gen_cc_clear(); | ||
| 661 | - gen_cc_NZ(cpu_T[0]); | ||
| 662 | - gen_cc_C_sub(cpu_cc_src, cpu_T[1]); | 696 | + gen_cc_clear_icc(); |
| 697 | + gen_cc_NZ_icc(cpu_T[0]); | ||
| 698 | + gen_cc_C_sub_icc(cpu_cc_src, cpu_T[1]); | ||
| 699 | +#ifdef TARGET_SPARC64 | ||
| 700 | + gen_cc_clear_xcc(); | ||
| 701 | + gen_cc_NZ_xcc(cpu_T[0]); | ||
| 702 | + gen_cc_C_sub_xcc(cpu_cc_src, cpu_T[1]); | ||
| 703 | + gen_cc_V_sub_xcc(cpu_T[0], cpu_cc_src, cpu_T[1]); | ||
| 704 | +#endif | ||
| 663 | } | 705 | } |
| 664 | 706 | ||
| 665 | static inline void gen_op_mulscc_T1_T0(void) | 707 | static inline void gen_op_mulscc_T1_T0(void) |
| @@ -711,10 +753,10 @@ static inline void gen_op_mulscc_T1_T0(void) | @@ -711,10 +753,10 @@ static inline void gen_op_mulscc_T1_T0(void) | ||
| 711 | tcg_gen_add_tl(cpu_T[0], cpu_cc_src, cpu_cc_src2); | 753 | tcg_gen_add_tl(cpu_T[0], cpu_cc_src, cpu_cc_src2); |
| 712 | tcg_gen_discard_tl(r_temp); | 754 | tcg_gen_discard_tl(r_temp); |
| 713 | 755 | ||
| 714 | - gen_cc_clear(); | ||
| 715 | - gen_cc_NZ(cpu_T[0]); | ||
| 716 | - gen_cc_V_add(cpu_T[0], cpu_cc_src, cpu_cc_src2); | ||
| 717 | - gen_cc_C_add(cpu_T[0], cpu_cc_src); | 756 | + gen_cc_clear_icc(); |
| 757 | + gen_cc_NZ_icc(cpu_T[0]); | ||
| 758 | + gen_cc_V_add_icc(cpu_T[0], cpu_cc_src, cpu_cc_src2); | ||
| 759 | + gen_cc_C_add_icc(cpu_T[0], cpu_cc_src); | ||
| 718 | } | 760 | } |
| 719 | 761 | ||
| 720 | static inline void gen_op_umul_T1_T0(void) | 762 | static inline void gen_op_umul_T1_T0(void) |
| @@ -797,8 +839,8 @@ static inline void gen_op_div_cc(void) | @@ -797,8 +839,8 @@ static inline void gen_op_div_cc(void) | ||
| 797 | { | 839 | { |
| 798 | int l1; | 840 | int l1; |
| 799 | 841 | ||
| 800 | - gen_cc_clear(); | ||
| 801 | - gen_cc_NZ(cpu_T[0]); | 842 | + gen_cc_clear_icc(); |
| 843 | + gen_cc_NZ_icc(cpu_T[0]); | ||
| 802 | l1 = gen_new_label(); | 844 | l1 = gen_new_label(); |
| 803 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2)); | 845 | tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2)); |
| 804 | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1); | 846 | tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1); |
| @@ -808,8 +850,12 @@ static inline void gen_op_div_cc(void) | @@ -808,8 +850,12 @@ static inline void gen_op_div_cc(void) | ||
| 808 | 850 | ||
| 809 | static inline void gen_op_logic_T0_cc(void) | 851 | static inline void gen_op_logic_T0_cc(void) |
| 810 | { | 852 | { |
| 811 | - gen_cc_clear(); | ||
| 812 | - gen_cc_NZ(cpu_T[0]); | 853 | + gen_cc_clear_icc(); |
| 854 | + gen_cc_NZ_icc(cpu_T[0]); | ||
| 855 | +#ifdef TARGET_SPARC64 | ||
| 856 | + gen_cc_clear_xcc(); | ||
| 857 | + gen_cc_NZ_xcc(cpu_T[0]); | ||
| 858 | +#endif | ||
| 813 | } | 859 | } |
| 814 | 860 | ||
| 815 | // 1 | 861 | // 1 |