Commit 3a8a44c4a8b31cc4e84a277e4e08faafa022de5e

Authored by aurel32
1 parent 829337a6

SH4: convert a few control or system register functions to TCG

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5107 c046a42c-6fe2-441c-8c8c-71466251a162
target-sh4/op.c
@@ -107,42 +107,12 @@ void OPPROTO op_rts(void) @@ -107,42 +107,12 @@ void OPPROTO op_rts(void)
107 RETURN(); 107 RETURN();
108 } 108 }
109 109
110 -void OPPROTO op_clrmac(void)  
111 -{  
112 - env->mach = env->macl = 0;  
113 - RETURN();  
114 -}  
115 -  
116 -void OPPROTO op_clrs(void)  
117 -{  
118 - env->sr &= ~SR_S;  
119 - RETURN();  
120 -}  
121 -  
122 -void OPPROTO op_clrt(void)  
123 -{  
124 - env->sr &= ~SR_T;  
125 - RETURN();  
126 -}  
127 -  
128 void OPPROTO op_ldtlb(void) 110 void OPPROTO op_ldtlb(void)
129 { 111 {
130 helper_ldtlb(); 112 helper_ldtlb();
131 RETURN(); 113 RETURN();
132 } 114 }
133 115
134 -void OPPROTO op_sets(void)  
135 -{  
136 - env->sr |= SR_S;  
137 - RETURN();  
138 -}  
139 -  
140 -void OPPROTO op_sett(void)  
141 -{  
142 - env->sr |= SR_T;  
143 - RETURN();  
144 -}  
145 -  
146 void OPPROTO op_frchg(void) 116 void OPPROTO op_frchg(void)
147 { 117 {
148 env->fpscr ^= FPSCR_FR; 118 env->fpscr ^= FPSCR_FR;
@@ -233,12 +203,6 @@ void OPPROTO op_div0s_T0_T1(void) @@ -233,12 +203,6 @@ void OPPROTO op_div0s_T0_T1(void)
233 RETURN(); 203 RETURN();
234 } 204 }
235 205
236 -void OPPROTO op_div0u(void)  
237 -{  
238 - env->sr &= ~(SR_M | SR_Q | SR_T);  
239 - RETURN();  
240 -}  
241 -  
242 void OPPROTO op_div1_T0_T1(void) 206 void OPPROTO op_div1_T0_T1(void)
243 { 207 {
244 helper_div1_T0_T1(); 208 helper_div1_T0_T1();
@@ -406,12 +370,6 @@ void OPPROTO op_sts_fpscr_T0(void) @@ -406,12 +370,6 @@ void OPPROTO op_sts_fpscr_T0(void)
406 RETURN(); 370 RETURN();
407 } 371 }
408 372
409 -void OPPROTO op_movt_rN(void)  
410 -{  
411 - env->gregs[PARAM1] = env->sr & SR_T;  
412 - RETURN();  
413 -}  
414 -  
415 void OPPROTO op_rotcl_Rn(void) 373 void OPPROTO op_rotcl_Rn(void)
416 { 374 {
417 helper_rotcl(&env->gregs[PARAM1]); 375 helper_rotcl(&env->gregs[PARAM1]);
@@ -676,12 +634,6 @@ void OPPROTO op_movl_FT0_fpul(void) @@ -676,12 +634,6 @@ void OPPROTO op_movl_FT0_fpul(void)
676 RETURN(); 634 RETURN();
677 } 635 }
678 636
679 -void OPPROTO op_movl_imm_PC(void)  
680 -{  
681 - env->pc = PARAM1;  
682 - RETURN();  
683 -}  
684 -  
685 void OPPROTO op_jT(void) 637 void OPPROTO op_jT(void)
686 { 638 {
687 if (env->sr & SR_T) 639 if (env->sr & SR_T)
@@ -704,12 +656,6 @@ void OPPROTO op_movl_delayed_pc_PC(void) @@ -704,12 +656,6 @@ void OPPROTO op_movl_delayed_pc_PC(void)
704 RETURN(); 656 RETURN();
705 } 657 }
706 658
707 -void OPPROTO op_addl_GBR_T0(void)  
708 -{  
709 - T0 += env->gbr;  
710 - RETURN();  
711 -}  
712 -  
713 void OPPROTO op_tst_imm_T0(void) 659 void OPPROTO op_tst_imm_T0(void)
714 { 660 {
715 cond_t((T0 & PARAM1) == 0); 661 cond_t((T0 & PARAM1) == 0);
target-sh4/translate.c
@@ -60,6 +60,9 @@ enum { @@ -60,6 +60,9 @@ enum {
60 /* global register indexes */ 60 /* global register indexes */
61 static TCGv cpu_env; 61 static TCGv cpu_env;
62 static TCGv cpu_gregs[24]; 62 static TCGv cpu_gregs[24];
  63 +static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
  64 +static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
  65 +static TCGv cpu_pr, cpu_fpscr, cpu_fpul;
63 66
64 /* dyngen register indexes */ 67 /* dyngen register indexes */
65 static TCGv cpu_T[2]; 68 static TCGv cpu_T[2];
@@ -90,6 +93,33 @@ static void sh4_translate_init(void) @@ -90,6 +93,33 @@ static void sh4_translate_init(void)
90 offsetof(CPUState, gregs[i]), 93 offsetof(CPUState, gregs[i]),
91 gregnames[i]); 94 gregnames[i]);
92 95
  96 + cpu_pc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  97 + offsetof(CPUState, pc), "PC");
  98 + cpu_sr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  99 + offsetof(CPUState, sr), "SR");
  100 + cpu_ssr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  101 + offsetof(CPUState, ssr), "SSR");
  102 + cpu_spc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  103 + offsetof(CPUState, spc), "SPC");
  104 + cpu_gbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  105 + offsetof(CPUState, gbr), "GBR");
  106 + cpu_vbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  107 + offsetof(CPUState, vbr), "VBR");
  108 + cpu_sgr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  109 + offsetof(CPUState, sgr), "SGR");
  110 + cpu_dbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  111 + offsetof(CPUState, dbr), "DBR");
  112 + cpu_mach = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  113 + offsetof(CPUState, mach), "MACH");
  114 + cpu_macl = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  115 + offsetof(CPUState, macl), "MACL");
  116 + cpu_pr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  117 + offsetof(CPUState, pr), "PR");
  118 + cpu_fpscr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  119 + offsetof(CPUState, fpscr), "FPSCR");
  120 + cpu_fpul = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  121 + offsetof(CPUState, fpul), "FPUL");
  122 +
93 /* register helpers */ 123 /* register helpers */
94 #undef DEF_HELPER 124 #undef DEF_HELPER
95 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); 125 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
@@ -204,10 +234,10 @@ static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest) @@ -204,10 +234,10 @@ static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest)
204 !ctx->singlestep_enabled) { 234 !ctx->singlestep_enabled) {
205 /* Use a direct jump if in same page and singlestep not enabled */ 235 /* Use a direct jump if in same page and singlestep not enabled */
206 tcg_gen_goto_tb(n); 236 tcg_gen_goto_tb(n);
207 - gen_op_movl_imm_PC(dest); 237 + tcg_gen_movi_i32(cpu_pc, dest);
208 tcg_gen_exit_tb((long) tb + n); 238 tcg_gen_exit_tb((long) tb + n);
209 } else { 239 } else {
210 - gen_op_movl_imm_PC(dest); 240 + tcg_gen_movi_i32(cpu_pc, dest);
211 if (ctx->singlestep_enabled) 241 if (ctx->singlestep_enabled)
212 gen_op_debug(); 242 gen_op_debug();
213 tcg_gen_exit_tb(0); 243 tcg_gen_exit_tb(0);
@@ -286,7 +316,7 @@ void _decode_opc(DisasContext * ctx) @@ -286,7 +316,7 @@ void _decode_opc(DisasContext * ctx)
286 #endif 316 #endif
287 switch (ctx->opcode) { 317 switch (ctx->opcode) {
288 case 0x0019: /* div0u */ 318 case 0x0019: /* div0u */
289 - gen_op_div0u(); 319 + tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T));
290 return; 320 return;
291 case 0x000b: /* rts */ 321 case 0x000b: /* rts */
292 CHECK_NOT_DELAY_SLOT gen_op_rts(); 322 CHECK_NOT_DELAY_SLOT gen_op_rts();
@@ -294,13 +324,14 @@ void _decode_opc(DisasContext * ctx) @@ -294,13 +324,14 @@ void _decode_opc(DisasContext * ctx)
294 ctx->delayed_pc = (uint32_t) - 1; 324 ctx->delayed_pc = (uint32_t) - 1;
295 return; 325 return;
296 case 0x0028: /* clrmac */ 326 case 0x0028: /* clrmac */
297 - gen_op_clrmac(); 327 + tcg_gen_movi_i32(cpu_mach, 0);
  328 + tcg_gen_movi_i32(cpu_macl, 0);
298 return; 329 return;
299 case 0x0048: /* clrs */ 330 case 0x0048: /* clrs */
300 - gen_op_clrs(); 331 + tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S);
301 return; 332 return;
302 case 0x0008: /* clrt */ 333 case 0x0008: /* clrt */
303 - gen_op_clrt(); 334 + tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
304 return; 335 return;
305 case 0x0038: /* ldtlb */ 336 case 0x0038: /* ldtlb */
306 #if defined(CONFIG_USER_ONLY) 337 #if defined(CONFIG_USER_ONLY)
@@ -315,10 +346,10 @@ void _decode_opc(DisasContext * ctx) @@ -315,10 +346,10 @@ void _decode_opc(DisasContext * ctx)
315 ctx->delayed_pc = (uint32_t) - 1; 346 ctx->delayed_pc = (uint32_t) - 1;
316 return; 347 return;
317 case 0x0058: /* sets */ 348 case 0x0058: /* sets */
318 - gen_op_sets(); 349 + tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S);
319 return; 350 return;
320 case 0x0018: /* sett */ 351 case 0x0018: /* sett */
321 - gen_op_sett(); 352 + tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
322 return; 353 return;
323 case 0xfbfd: /* frchg */ 354 case 0xfbfd: /* frchg */
324 gen_op_frchg(); 355 gen_op_frchg();
@@ -850,7 +881,7 @@ void _decode_opc(DisasContext * ctx) @@ -850,7 +881,7 @@ void _decode_opc(DisasContext * ctx)
850 return; 881 return;
851 case 0xcd00: /* and.b #imm,@(R0,GBR) */ 882 case 0xcd00: /* and.b #imm,@(R0,GBR) */
852 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); 883 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
853 - gen_op_addl_GBR_T0(); 884 + tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr);
854 tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); 885 tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
855 gen_op_ldub_T0_T0(ctx); 886 gen_op_ldub_T0_T0(ctx);
856 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], B7_0); 887 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], B7_0);
@@ -954,14 +985,14 @@ void _decode_opc(DisasContext * ctx) @@ -954,14 +985,14 @@ void _decode_opc(DisasContext * ctx)
954 return; 985 return;
955 case 0xcf00: /* or.b #imm,@(R0,GBR) */ 986 case 0xcf00: /* or.b #imm,@(R0,GBR) */
956 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); 987 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
957 - gen_op_addl_GBR_T0(); 988 + tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr);
958 tcg_gen_mov_i32(cpu_T[0], cpu_T[1]); 989 tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
959 gen_op_ldub_T0_T0(ctx); 990 gen_op_ldub_T0_T0(ctx);
960 tcg_gen_ori_i32(cpu_T[0], cpu_T[0], B7_0); 991 tcg_gen_ori_i32(cpu_T[0], cpu_T[0], B7_0);
961 gen_op_stb_T0_T1(ctx); 992 gen_op_stb_T0_T1(ctx);
962 return; 993 return;
963 case 0xc300: /* trapa #imm */ 994 case 0xc300: /* trapa #imm */
964 - CHECK_NOT_DELAY_SLOT gen_op_movl_imm_PC(ctx->pc); 995 + CHECK_NOT_DELAY_SLOT tcg_gen_movi_i32(cpu_pc, ctx->pc);
965 gen_op_trapa(B7_0); 996 gen_op_trapa(B7_0);
966 ctx->bstate = BS_BRANCH; 997 ctx->bstate = BS_BRANCH;
967 return; 998 return;
@@ -970,7 +1001,7 @@ void _decode_opc(DisasContext * ctx) @@ -970,7 +1001,7 @@ void _decode_opc(DisasContext * ctx)
970 return; 1001 return;
971 case 0xcc00: /* tst.b #imm,@(R0,GBR) */ 1002 case 0xcc00: /* tst.b #imm,@(R0,GBR) */
972 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); 1003 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
973 - gen_op_addl_GBR_T0(); 1004 + tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr);
974 gen_op_ldub_T0_T0(ctx); 1005 gen_op_ldub_T0_T0(ctx);
975 gen_op_tst_imm_T0(B7_0); 1006 gen_op_tst_imm_T0(B7_0);
976 return; 1007 return;
@@ -979,7 +1010,7 @@ void _decode_opc(DisasContext * ctx) @@ -979,7 +1010,7 @@ void _decode_opc(DisasContext * ctx)
979 return; 1010 return;
980 case 0xce00: /* xor.b #imm,@(R0,GBR) */ 1011 case 0xce00: /* xor.b #imm,@(R0,GBR) */
981 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]); 1012 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
982 - gen_op_addl_GBR_T0(); 1013 + tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr);
983 tcg_gen_mov_i32(cpu_T[1], cpu_T[0]); 1014 tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
984 gen_op_ldub_T0_T0(ctx); 1015 gen_op_ldub_T0_T0(ctx);
985 tcg_gen_xori_i32(cpu_T[0], cpu_T[0], B7_0); 1016 tcg_gen_xori_i32(cpu_T[0], cpu_T[0], B7_0);
@@ -1096,7 +1127,7 @@ void _decode_opc(DisasContext * ctx) @@ -1096,7 +1127,7 @@ void _decode_opc(DisasContext * ctx)
1096 gen_op_stl_T0_T1(ctx); 1127 gen_op_stl_T0_T1(ctx);
1097 return; 1128 return;
1098 case 0x0029: /* movt Rn */ 1129 case 0x0029: /* movt Rn */
1099 - gen_op_movt_rN(REG(B11_8)); 1130 + tcg_gen_andi_i32(cpu_gregs[REG(B11_8)], cpu_sr, SR_T);
1100 return; 1131 return;
1101 case 0x0093: /* ocbi @Rn */ 1132 case 0x0093: /* ocbi @Rn */
1102 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]); 1133 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
@@ -1329,7 +1360,7 @@ gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, @@ -1329,7 +1360,7 @@ gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
1329 for (i = 0; i < env->nb_breakpoints; i++) { 1360 for (i = 0; i < env->nb_breakpoints; i++) {
1330 if (ctx.pc == env->breakpoints[i]) { 1361 if (ctx.pc == env->breakpoints[i]) {
1331 /* We have hit a breakpoint - make sure PC is up-to-date */ 1362 /* We have hit a breakpoint - make sure PC is up-to-date */
1332 - gen_op_movl_imm_PC(ctx.pc); 1363 + tcg_gen_movi_i32(cpu_pc, ctx.pc);
1333 gen_op_debug(); 1364 gen_op_debug();
1334 ctx.bstate = BS_EXCP; 1365 ctx.bstate = BS_EXCP;
1335 break; 1366 break;