gwj / at91sam9263 · Commits

Commit 829337a6878affa8aef099061f52321ff82e316e

Authored by aurel32
1 parent 5aa3b1ea

SH4: Fix bugs introduce in r5099 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5106 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 8 additions and 8 deletions
target-sh4/translate.c
  View file @829337a
... ... @@ -624,7 +624,7 @@ void _decode_opc(DisasContext * ctx)
624 624 case 0x000f: /* mac.l @Rm+,@Rn+ */
625 625 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
626 626 gen_op_ldl_T0_T0(ctx);
627   - tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
  627 + tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
628 628 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
629 629 gen_op_ldl_T0_T0(ctx);
630 630 gen_op_macl_T0_T1();
... ... @@ -634,7 +634,7 @@ void _decode_opc(DisasContext * ctx)
634 634 case 0x400f: /* mac.w @Rm+,@Rn+ */
635 635 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
636 636 gen_op_ldl_T0_T0(ctx);
637   - tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
  637 + tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
638 638 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B7_4)]);
639 639 gen_op_ldl_T0_T0(ctx);
640 640 gen_op_macw_T0_T1();
... ... @@ -851,7 +851,7 @@ void _decode_opc(DisasContext * ctx)
851 851 case 0xcd00: /* and.b #imm,@(R0,GBR) */
852 852 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
853 853 gen_op_addl_GBR_T0();
854   - tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
  854 + tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
855 855 gen_op_ldub_T0_T0(ctx);
856 856 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], B7_0);
857 857 gen_op_stb_T0_T1(ctx);
... ... @@ -903,21 +903,21 @@ void _decode_opc(DisasContext * ctx)
903 903 case 0xc000: /* mov.b R0,@(disp,GBR) */
904 904 gen_op_stc_gbr_T0();
905 905 tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0);
906   - tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
  906 + tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
907 907 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
908 908 gen_op_stb_T0_T1(ctx);
909 909 return;
910 910 case 0xc100: /* mov.w R0,@(disp,GBR) */
911 911 gen_op_stc_gbr_T0();
912 912 tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0 * 2);
913   - tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
  913 + tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
914 914 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
915 915 gen_op_stw_T0_T1(ctx);
916 916 return;
917 917 case 0xc200: /* mov.l R0,@(disp,GBR) */
918 918 gen_op_stc_gbr_T0();
919 919 tcg_gen_addi_i32(cpu_T[0], cpu_T[0], B7_0 * 4);
920   - tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
  920 + tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
921 921 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
922 922 gen_op_stl_T0_T1(ctx);
923 923 return;
... ... @@ -980,7 +980,7 @@ void _decode_opc(DisasContext * ctx)
980 980 case 0xce00: /* xor.b #imm,@(R0,GBR) */
981 981 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
982 982 gen_op_addl_GBR_T0();
983   - tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
  983 + tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
984 984 gen_op_ldub_T0_T0(ctx);
985 985 tcg_gen_xori_i32(cpu_T[0], cpu_T[0], B7_0);
986 986 gen_op_stb_T0_T1(ctx);
... ... @@ -1154,7 +1154,7 @@ void _decode_opc(DisasContext * ctx)
1154 1154 return;
1155 1155 case 0x401b: /* tas.b @Rn */
1156 1156 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
1157   - tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
  1157 + tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
1158 1158 gen_op_ldub_T0_T0(ctx);
1159 1159 gen_op_cmp_eq_imm_T0(0);
1160 1160 tcg_gen_ori_i32(cpu_T[0], cpu_T[0], 0x80);
... ...