gwj / at91sam9263 · Commits

Commit 3a8a44c4a8b31cc4e84a277e4e08faafa022de5e

Authored by aurel32
1 parent 829337a6

SH4: convert a few control or system register functions to TCG 

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5107 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 2 changed files with 46 additions and 69 deletions
target-sh4/op.c
  View file @3a8a44c
... ... @@ -107,42 +107,12 @@ void OPPROTO op_rts(void)
107 107 RETURN();
108 108 }
109 109  
110   -void OPPROTO op_clrmac(void)
111   -{
112   - env->mach = env->macl = 0;
113   - RETURN();
114   -}
115   -
116   -void OPPROTO op_clrs(void)
117   -{
118   - env->sr &= ~SR_S;
119   - RETURN();
120   -}
121   -
122   -void OPPROTO op_clrt(void)
123   -{
124   - env->sr &= ~SR_T;
125   - RETURN();
126   -}
127   -
128 110 void OPPROTO op_ldtlb(void)
129 111 {
130 112 helper_ldtlb();
131 113 RETURN();
132 114 }
133 115  
134   -void OPPROTO op_sets(void)
135   -{
136   - env->sr |= SR_S;
137   - RETURN();
138   -}
139   -
140   -void OPPROTO op_sett(void)
141   -{
142   - env->sr |= SR_T;
143   - RETURN();
144   -}
145   -
146 116 void OPPROTO op_frchg(void)
147 117 {
148 118 env->fpscr ^= FPSCR_FR;
... ... @@ -233,12 +203,6 @@ void OPPROTO op_div0s_T0_T1(void)
233 203 RETURN();
234 204 }
235 205  
236   -void OPPROTO op_div0u(void)
237   -{
238   - env->sr &= ~(SR_M | SR_Q | SR_T);
239   - RETURN();
240   -}
241   -
242 206 void OPPROTO op_div1_T0_T1(void)
243 207 {
244 208 helper_div1_T0_T1();
... ... @@ -406,12 +370,6 @@ void OPPROTO op_sts_fpscr_T0(void)
406 370 RETURN();
407 371 }
408 372  
409   -void OPPROTO op_movt_rN(void)
410   -{
411   - env->gregs[PARAM1] = env->sr & SR_T;
412   - RETURN();
413   -}
414   -
415 373 void OPPROTO op_rotcl_Rn(void)
416 374 {
417 375 helper_rotcl(&env->gregs[PARAM1]);
... ... @@ -676,12 +634,6 @@ void OPPROTO op_movl_FT0_fpul(void)
676 634 RETURN();
677 635 }
678 636  
679   -void OPPROTO op_movl_imm_PC(void)
680   -{
681   - env->pc = PARAM1;
682   - RETURN();
683   -}
684   -
685 637 void OPPROTO op_jT(void)
686 638 {
687 639 if (env->sr & SR_T)
... ... @@ -704,12 +656,6 @@ void OPPROTO op_movl_delayed_pc_PC(void)
704 656 RETURN();
705 657 }
706 658  
707   -void OPPROTO op_addl_GBR_T0(void)
708   -{
709   - T0 += env->gbr;
710   - RETURN();
711   -}
712   -
713 659 void OPPROTO op_tst_imm_T0(void)
714 660 {
715 661 cond_t((T0 & PARAM1) == 0);
... ...
target-sh4/translate.c
  View file @3a8a44c
... ... @@ -60,6 +60,9 @@ enum {
60 60 /* global register indexes */
61 61 static TCGv cpu_env;
62 62 static TCGv cpu_gregs[24];
  63 +static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
  64 +static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
  65 +static TCGv cpu_pr, cpu_fpscr, cpu_fpul;
63 66  
64 67 /* dyngen register indexes */
65 68 static TCGv cpu_T[2];
... ... @@ -90,6 +93,33 @@ static void sh4_translate_init(void)
90 93 offsetof(CPUState, gregs[i]),
91 94 gregnames[i]);
92 95  
  96 + cpu_pc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  97 + offsetof(CPUState, pc), "PC");
  98 + cpu_sr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  99 + offsetof(CPUState, sr), "SR");
  100 + cpu_ssr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  101 + offsetof(CPUState, ssr), "SSR");
  102 + cpu_spc = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  103 + offsetof(CPUState, spc), "SPC");
  104 + cpu_gbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  105 + offsetof(CPUState, gbr), "GBR");
  106 + cpu_vbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  107 + offsetof(CPUState, vbr), "VBR");
  108 + cpu_sgr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  109 + offsetof(CPUState, sgr), "SGR");
  110 + cpu_dbr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  111 + offsetof(CPUState, dbr), "DBR");
  112 + cpu_mach = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  113 + offsetof(CPUState, mach), "MACH");
  114 + cpu_macl = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  115 + offsetof(CPUState, macl), "MACL");
  116 + cpu_pr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  117 + offsetof(CPUState, pr), "PR");
  118 + cpu_fpscr = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  119 + offsetof(CPUState, fpscr), "FPSCR");
  120 + cpu_fpul = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
  121 + offsetof(CPUState, fpul), "FPUL");
  122 +
93 123 /* register helpers */
94 124 #undef DEF_HELPER
95 125 #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
... ... @@ -204,10 +234,10 @@ static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest)
204 234 !ctx->singlestep_enabled) {
205 235 /* Use a direct jump if in same page and singlestep not enabled */
206 236 tcg_gen_goto_tb(n);
207   - gen_op_movl_imm_PC(dest);
  237 + tcg_gen_movi_i32(cpu_pc, dest);
208 238 tcg_gen_exit_tb((long) tb + n);
209 239 } else {
210   - gen_op_movl_imm_PC(dest);
  240 + tcg_gen_movi_i32(cpu_pc, dest);
211 241 if (ctx->singlestep_enabled)
212 242 gen_op_debug();
213 243 tcg_gen_exit_tb(0);
... ... @@ -286,7 +316,7 @@ void _decode_opc(DisasContext * ctx)
286 316 #endif
287 317 switch (ctx->opcode) {
288 318 case 0x0019: /* div0u */
289   - gen_op_div0u();
  319 + tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T));
290 320 return;
291 321 case 0x000b: /* rts */
292 322 CHECK_NOT_DELAY_SLOT gen_op_rts();
... ... @@ -294,13 +324,14 @@ void _decode_opc(DisasContext * ctx)
294 324 ctx->delayed_pc = (uint32_t) - 1;
295 325 return;
296 326 case 0x0028: /* clrmac */
297   - gen_op_clrmac();
  327 + tcg_gen_movi_i32(cpu_mach, 0);
  328 + tcg_gen_movi_i32(cpu_macl, 0);
298 329 return;
299 330 case 0x0048: /* clrs */
300   - gen_op_clrs();
  331 + tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S);
301 332 return;
302 333 case 0x0008: /* clrt */
303   - gen_op_clrt();
  334 + tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
304 335 return;
305 336 case 0x0038: /* ldtlb */
306 337 #if defined(CONFIG_USER_ONLY)
... ... @@ -315,10 +346,10 @@ void _decode_opc(DisasContext * ctx)
315 346 ctx->delayed_pc = (uint32_t) - 1;
316 347 return;
317 348 case 0x0058: /* sets */
318   - gen_op_sets();
  349 + tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S);
319 350 return;
320 351 case 0x0018: /* sett */
321   - gen_op_sett();
  352 + tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
322 353 return;
323 354 case 0xfbfd: /* frchg */
324 355 gen_op_frchg();
... ... @@ -850,7 +881,7 @@ void _decode_opc(DisasContext * ctx)
850 881 return;
851 882 case 0xcd00: /* and.b #imm,@(R0,GBR) */
852 883 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
853   - gen_op_addl_GBR_T0();
  884 + tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr);
854 885 tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
855 886 gen_op_ldub_T0_T0(ctx);
856 887 tcg_gen_andi_i32(cpu_T[0], cpu_T[0], B7_0);
... ... @@ -954,14 +985,14 @@ void _decode_opc(DisasContext * ctx)
954 985 return;
955 986 case 0xcf00: /* or.b #imm,@(R0,GBR) */
956 987 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
957   - gen_op_addl_GBR_T0();
  988 + tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr);
958 989 tcg_gen_mov_i32(cpu_T[0], cpu_T[1]);
959 990 gen_op_ldub_T0_T0(ctx);
960 991 tcg_gen_ori_i32(cpu_T[0], cpu_T[0], B7_0);
961 992 gen_op_stb_T0_T1(ctx);
962 993 return;
963 994 case 0xc300: /* trapa #imm */
964   - CHECK_NOT_DELAY_SLOT gen_op_movl_imm_PC(ctx->pc);
  995 + CHECK_NOT_DELAY_SLOT tcg_gen_movi_i32(cpu_pc, ctx->pc);
965 996 gen_op_trapa(B7_0);
966 997 ctx->bstate = BS_BRANCH;
967 998 return;
... ... @@ -970,7 +1001,7 @@ void _decode_opc(DisasContext * ctx)
970 1001 return;
971 1002 case 0xcc00: /* tst.b #imm,@(R0,GBR) */
972 1003 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
973   - gen_op_addl_GBR_T0();
  1004 + tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr);
974 1005 gen_op_ldub_T0_T0(ctx);
975 1006 gen_op_tst_imm_T0(B7_0);
976 1007 return;
... ... @@ -979,7 +1010,7 @@ void _decode_opc(DisasContext * ctx)
979 1010 return;
980 1011 case 0xce00: /* xor.b #imm,@(R0,GBR) */
981 1012 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(0)]);
982   - gen_op_addl_GBR_T0();
  1013 + tcg_gen_add_i32(cpu_T[0], cpu_T[0], cpu_gbr);
983 1014 tcg_gen_mov_i32(cpu_T[1], cpu_T[0]);
984 1015 gen_op_ldub_T0_T0(ctx);
985 1016 tcg_gen_xori_i32(cpu_T[0], cpu_T[0], B7_0);
... ... @@ -1096,7 +1127,7 @@ void _decode_opc(DisasContext * ctx)
1096 1127 gen_op_stl_T0_T1(ctx);
1097 1128 return;
1098 1129 case 0x0029: /* movt Rn */
1099   - gen_op_movt_rN(REG(B11_8));
  1130 + tcg_gen_andi_i32(cpu_gregs[REG(B11_8)], cpu_sr, SR_T);
1100 1131 return;
1101 1132 case 0x0093: /* ocbi @Rn */
1102 1133 tcg_gen_mov_i32(cpu_T[0], cpu_gregs[REG(B11_8)]);
... ... @@ -1329,7 +1360,7 @@ gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
1329 1360 for (i = 0; i < env->nb_breakpoints; i++) {
1330 1361 if (ctx.pc == env->breakpoints[i]) {
1331 1362 /* We have hit a breakpoint - make sure PC is up-to-date */
1332   - gen_op_movl_imm_PC(ctx.pc);
  1363 + tcg_gen_movi_i32(cpu_pc, ctx.pc);
1333 1364 gen_op_debug();
1334 1365 ctx.bstate = BS_EXCP;
1335 1366 break;
... ...