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/*
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* QEMU 16550 A UART emulation
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*
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* Copyright ( c ) 2003 - 2004 Fabrice Bellard
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* Copyright ( c ) 2008 Citrix Systems , Inc .
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*
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* Permission is hereby granted , free of charge , to any person obtaining a copy
* of this software and associated documentation files ( the "Software" ), to deal
* in the Software without restriction , including without limitation the rights
* to use , copy , modify , merge , publish , distribute , sublicense , and / or sell
* copies of the Software , and to permit persons to whom the Software is
* furnished to do so , subject to the following conditions :
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software .
*
* THE SOFTWARE IS PROVIDED "AS IS" , WITHOUT WARRANTY OF ANY KIND , EXPRESS OR
* IMPLIED , INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY ,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT . IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM , DAMAGES OR OTHER
* LIABILITY , WHETHER IN AN ACTION OF CONTRACT , TORT OR OTHERWISE , ARISING FROM ,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE .
*/
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# include "hw.h"
# include "qemu-char.h"
# include "isa.h"
# include "pc.h"
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# include "qemu-timer.h"
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// # define DEBUG_SERIAL
# define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
# define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
# define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
# define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
# define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
# define UART_IIR_NO_INT 0x01 /* No interrupts pending */
# define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
# define UART_IIR_MSI 0x00 /* Modem status interrupt */
# define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
# define UART_IIR_RDI 0x04 /* Receiver data interrupt */
# define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
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# define UART_IIR_CTI 0x0C /* Character Timeout Indication */
# define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */
# define UART_IIR_FE 0xC0 /* Fifo enabled */
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/*
* These are the definitions for the Modem Control Register
*/
# define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
# define UART_MCR_OUT2 0x08 /* Out2 complement */
# define UART_MCR_OUT1 0x04 /* Out1 complement */
# define UART_MCR_RTS 0x02 /* RTS complement */
# define UART_MCR_DTR 0x01 /* DTR complement */
/*
* These are the definitions for the Modem Status Register
*/
# define UART_MSR_DCD 0x80 /* Data Carrier Detect */
# define UART_MSR_RI 0x40 /* Ring Indicator */
# define UART_MSR_DSR 0x20 /* Data Set Ready */
# define UART_MSR_CTS 0x10 /* Clear to Send */
# define UART_MSR_DDCD 0x08 /* Delta DCD */
# define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
# define UART_MSR_DDSR 0x02 /* Delta DSR */
# define UART_MSR_DCTS 0x01 /* Delta CTS */
# define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
# define UART_LSR_TEMT 0x40 /* Transmitter empty */
# define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
# define UART_LSR_BI 0x10 /* Break interrupt indicator */
# define UART_LSR_FE 0x08 /* Frame error indicator */
# define UART_LSR_PE 0x04 /* Parity error indicator */
# define UART_LSR_OE 0x02 /* Overrun error indicator */
# define UART_LSR_DR 0x01 /* Receiver data ready */
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# define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */
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/* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
# define UART_FCR_ITL_1 0x00 /* 1 byte ITL */
# define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */
# define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */
# define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */
# define UART_FCR_DMS 0x08 /* DMA Mode Select */
# define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */
# define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */
# define UART_FCR_FE 0x01 /* FIFO Enable */
# define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */
# define XMIT_FIFO 0
# define RECV_FIFO 1
# define MAX_XMIT_RETRY 4
struct SerialFIFO {
uint8_t data [ UART_FIFO_LENGTH ];
uint8_t count ;
uint8_t itl ; /* Interrupt Trigger Level */
uint8_t tail ;
uint8_t head ;
} typedef SerialFIFO ;
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struct SerialState {
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uint16_t divider ;
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uint8_t rbr ; /* receive register */
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uint8_t thr ; /* transmit holding register */
uint8_t tsr ; /* transmit shift register */
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uint8_t ier ;
uint8_t iir ; /* read only */
uint8_t lcr ;
uint8_t mcr ;
uint8_t lsr ; /* read only */
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uint8_t msr ; /* read only */
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uint8_t scr ;
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uint8_t fcr ;
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/* NOTE : this hidden state is necessary for tx irq generation as
it can be reset while reading iir */
int thr_ipending ;
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qemu_irq irq ;
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CharDriverState * chr ;
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int last_break_enable ;
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target_phys_addr_t base ;
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int it_shift ;
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int baudbase ;
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int tsr_retry ;
uint64_t last_xmit_ts ; /* Time when the last byte was successfully sent out of the tsr */
SerialFIFO recv_fifo ;
SerialFIFO xmit_fifo ;
struct QEMUTimer * fifo_timeout_timer ;
int timeout_ipending ; /* timeout interrupt pending state */
struct QEMUTimer * transmit_timer ;
uint64_t char_transmit_time ; /* time to transmit a char in ticks*/
int poll_msl ;
struct QEMUTimer * modem_status_poll ;
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};
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static void serial_receive1 ( void * opaque , const uint8_t * buf , int size );
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static void fifo_clear ( SerialState * s , int fifo )
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{
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SerialFIFO * f = ( fifo ) ? & s -> recv_fifo : & s -> xmit_fifo ;
memset ( f -> data , 0 , UART_FIFO_LENGTH );
f -> count = 0 ;
f -> head = 0 ;
f -> tail = 0 ;
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}
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static int fifo_put ( SerialState * s , int fifo , uint8_t chr )
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{
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SerialFIFO * f = ( fifo ) ? & s -> recv_fifo : & s -> xmit_fifo ;
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f -> data [ f -> head ++ ] = chr ;
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if ( f -> head == UART_FIFO_LENGTH )
f -> head = 0 ;
f -> count ++ ;
return 1 ;
}
static uint8_t fifo_get ( SerialState * s , int fifo )
{
SerialFIFO * f = ( fifo ) ? & s -> recv_fifo : & s -> xmit_fifo ;
uint8_t c ;
if ( f -> count == 0 )
return 0 ;
c = f -> data [ f -> tail ++ ];
if ( f -> tail == UART_FIFO_LENGTH )
f -> tail = 0 ;
f -> count -- ;
return c ;
}
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static void serial_update_irq ( SerialState * s )
{
uint8_t tmp_iir = UART_IIR_NO_INT ;
if (( s -> ier & UART_IER_RLSI ) && ( s -> lsr & UART_LSR_INT_ANY )) {
tmp_iir = UART_IIR_RLSI ;
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} else if (( s -> ier & UART_IER_RDI ) && s -> timeout_ipending ) {
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/* Note that ( s -> ier & UART_IER_RDI ) can mask this interrupt ,
* this is not in the specification but is observed on existing
* hardware . */
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tmp_iir = UART_IIR_CTI ;
} else if (( s -> ier & UART_IER_RDI ) && ( s -> lsr & UART_LSR_DR )) {
if ( ! ( s -> fcr & UART_FCR_FE )) {
tmp_iir = UART_IIR_RDI ;
} else if ( s -> recv_fifo . count >= s -> recv_fifo . itl ) {
tmp_iir = UART_IIR_RDI ;
}
} else if (( s -> ier & UART_IER_THRI ) && s -> thr_ipending ) {
tmp_iir = UART_IIR_THRI ;
} else if (( s -> ier & UART_IER_MSI ) && ( s -> msr & UART_MSR_ANY_DELTA )) {
tmp_iir = UART_IIR_MSI ;
}
s -> iir = tmp_iir | ( s -> iir & 0xF0 );
if ( tmp_iir != UART_IIR_NO_INT ) {
qemu_irq_raise ( s -> irq );
} else {
qemu_irq_lower ( s -> irq );
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}
}
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static void serial_update_parameters ( SerialState * s )
{
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int speed , parity , data_bits , stop_bits , frame_size ;
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QEMUSerialSetParams ssp ;
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if ( s -> divider == 0 )
return ;
frame_size = 1 ;
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if ( s -> lcr & 0x08 ) {
if ( s -> lcr & 0x10 )
parity = 'E' ;
else
parity = 'O' ;
} else {
parity = 'N' ;
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frame_size = 0 ;
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}
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if ( s -> lcr & 0x04 )
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stop_bits = 2 ;
else
stop_bits = 1 ;
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data_bits = ( s -> lcr & 0x03 ) + 5 ;
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frame_size += data_bits + stop_bits ;
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speed = s -> baudbase / s -> divider ;
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ssp . speed = speed ;
ssp . parity = parity ;
ssp . data_bits = data_bits ;
ssp . stop_bits = stop_bits ;
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s -> char_transmit_time = ( ticks_per_sec / speed ) * frame_size ;
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qemu_chr_ioctl ( s -> chr , CHR_IOCTL_SERIAL_SET_PARAMS , & ssp );
# if 0
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printf ( "speed=%d parity=%c data=%d stop=%d \n " ,
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speed , parity , data_bits , stop_bits );
# endif
}
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static void serial_update_msl ( SerialState * s )
{
uint8_t omsr ;
int flags ;
qemu_del_timer ( s -> modem_status_poll );
if ( qemu_chr_ioctl ( s -> chr , CHR_IOCTL_SERIAL_GET_TIOCM , & flags ) == - ENOTSUP ) {
s -> poll_msl = - 1 ;
return ;
}
omsr = s -> msr ;
s -> msr = ( flags & CHR_TIOCM_CTS ) ? s -> msr | UART_MSR_CTS : s -> msr & ~ UART_MSR_CTS ;
s -> msr = ( flags & CHR_TIOCM_DSR ) ? s -> msr | UART_MSR_DSR : s -> msr & ~ UART_MSR_DSR ;
s -> msr = ( flags & CHR_TIOCM_CAR ) ? s -> msr | UART_MSR_DCD : s -> msr & ~ UART_MSR_DCD ;
s -> msr = ( flags & CHR_TIOCM_RI ) ? s -> msr | UART_MSR_RI : s -> msr & ~ UART_MSR_RI ;
if ( s -> msr != omsr ) {
/* Set delta bits */
s -> msr = s -> msr | (( s -> msr >> 4 ) ^ ( omsr >> 4 ));
/* UART_MSR_TERI only if change was from 1 -> 0 */
if (( s -> msr & UART_MSR_TERI ) && ! ( omsr & UART_MSR_RI ))
s -> msr &= ~ UART_MSR_TERI ;
serial_update_irq ( s );
}
/* The real 16550 A apparently has a 250 ns response latency to line status changes .
We ' ll be lazy and poll only every 10 ms , and only poll it at all if MSI interrupts are turned on */
if ( s -> poll_msl )
qemu_mod_timer ( s -> modem_status_poll , qemu_get_clock ( vm_clock ) + ticks_per_sec / 100 );
}
static void serial_xmit ( void * opaque )
{
SerialState * s = opaque ;
uint64_t new_xmit_ts = qemu_get_clock ( vm_clock );
if ( s -> tsr_retry <= 0 ) {
if ( s -> fcr & UART_FCR_FE ) {
s -> tsr = fifo_get ( s , XMIT_FIFO );
if ( ! s -> xmit_fifo . count )
s -> lsr |= UART_LSR_THRE ;
} else {
s -> tsr = s -> thr ;
s -> lsr |= UART_LSR_THRE ;
}
}
if ( s -> mcr & UART_MCR_LOOP ) {
/* in loopback mode, say that we just received a char */
serial_receive1 ( s , & s -> tsr , 1 );
} else if ( qemu_chr_write ( s -> chr , & s -> tsr , 1 ) != 1 ) {
if (( s -> tsr_retry > 0 ) && ( s -> tsr_retry <= MAX_XMIT_RETRY )) {
s -> tsr_retry ++ ;
qemu_mod_timer ( s -> transmit_timer , new_xmit_ts + s -> char_transmit_time );
return ;
} else if ( s -> poll_msl < 0 ) {
/* If we exceed MAX_XMIT_RETRY and the backend is not a real serial port , then
drop any further failed writes instantly , until we get one that goes through .
This is to prevent guests that log to unconnected pipes or pty ' s from stalling . */
s -> tsr_retry = - 1 ;
}
}
else {
s -> tsr_retry = 0 ;
}
s -> last_xmit_ts = qemu_get_clock ( vm_clock );
if ( ! ( s -> lsr & UART_LSR_THRE ))
qemu_mod_timer ( s -> transmit_timer , s -> last_xmit_ts + s -> char_transmit_time );
if ( s -> lsr & UART_LSR_THRE ) {
s -> lsr |= UART_LSR_TEMT ;
s -> thr_ipending = 1 ;
serial_update_irq ( s );
}
}
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static void serial_ioport_write ( void * opaque , uint32_t addr , uint32_t val )
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{
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SerialState * s = opaque ;
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addr &= 7 ;
# ifdef DEBUG_SERIAL
printf ( "serial: write addr=0x%02x val=0x%02x \n " , addr , val );
# endif
switch ( addr ) {
default :
case 0 :
if ( s -> lcr & UART_LCR_DLAB ) {
s -> divider = ( s -> divider & 0xff00 ) | val ;
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serial_update_parameters ( s );
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} else {
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s -> thr = ( uint8_t ) val ;
if ( s -> fcr & UART_FCR_FE ) {
fifo_put ( s , XMIT_FIFO , s -> thr );
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s -> thr_ipending = 0 ;
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s -> lsr &= ~ UART_LSR_TEMT ;
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s -> lsr &= ~ UART_LSR_THRE ;
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serial_update_irq ( s );
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} else {
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s -> thr_ipending = 0 ;
s -> lsr &= ~ UART_LSR_THRE ;
serial_update_irq ( s );
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}
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serial_xmit ( s );
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}
break ;
case 1 :
if ( s -> lcr & UART_LCR_DLAB ) {
s -> divider = ( s -> divider & 0x00ff ) | ( val << 8 );
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serial_update_parameters ( s );
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} else {
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s -> ier = val & 0x0f ;
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/* If the backend device is a real serial port , turn polling of the modem
status lines on physical port on or off depending on UART_IER_MSI state */
if ( s -> poll_msl >= 0 ) {
if ( s -> ier & UART_IER_MSI ) {
s -> poll_msl = 1 ;
serial_update_msl ( s );
} else {
qemu_del_timer ( s -> modem_status_poll );
s -> poll_msl = 0 ;
}
}
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if ( s -> lsr & UART_LSR_THRE ) {
s -> thr_ipending = 1 ;
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serial_update_irq ( s );
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}
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}
break ;
case 2 :
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val = val & 0xFF ;
if ( s -> fcr == val )
break ;
/* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
if (( val ^ s -> fcr ) & UART_FCR_FE )
val |= UART_FCR_XFR | UART_FCR_RFR ;
/* FIFO clear */
if ( val & UART_FCR_RFR ) {
qemu_del_timer ( s -> fifo_timeout_timer );
s -> timeout_ipending = 0 ;
fifo_clear ( s , RECV_FIFO );
}
if ( val & UART_FCR_XFR ) {
fifo_clear ( s , XMIT_FIFO );
}
if ( val & UART_FCR_FE ) {
s -> iir |= UART_IIR_FE ;
/* Set RECV_FIFO trigger Level */
switch ( val & 0xC0 ) {
case UART_FCR_ITL_1 :
s -> recv_fifo . itl = 1 ;
break ;
case UART_FCR_ITL_2 :
s -> recv_fifo . itl = 4 ;
break ;
case UART_FCR_ITL_3 :
s -> recv_fifo . itl = 8 ;
break ;
case UART_FCR_ITL_4 :
s -> recv_fifo . itl = 14 ;
break ;
}
} else
s -> iir &= ~ UART_IIR_FE ;
/* Set fcr - or at least the bits in it that are supposed to "stick" */
s -> fcr = val & 0xC9 ;
serial_update_irq ( s );
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break ;
case 3 :
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{
int break_enable ;
s -> lcr = val ;
serial_update_parameters ( s );
break_enable = ( val >> 6 ) & 1 ;
if ( break_enable != s -> last_break_enable ) {
s -> last_break_enable = break_enable ;
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qemu_chr_ioctl ( s -> chr , CHR_IOCTL_SERIAL_SET_BREAK ,
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& break_enable );
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}
}
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break ;
case 4 :
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{
int flags ;
int old_mcr = s -> mcr ;
s -> mcr = val & 0x1f ;
if ( val & UART_MCR_LOOP )
break ;
if ( s -> poll_msl >= 0 && old_mcr != s -> mcr ) {
qemu_chr_ioctl ( s -> chr , CHR_IOCTL_SERIAL_GET_TIOCM , & flags );
flags &= ~ ( CHR_TIOCM_RTS | CHR_TIOCM_DTR );
if ( val & UART_MCR_RTS )
flags |= CHR_TIOCM_RTS ;
if ( val & UART_MCR_DTR )
flags |= CHR_TIOCM_DTR ;
qemu_chr_ioctl ( s -> chr , CHR_IOCTL_SERIAL_SET_TIOCM , & flags );
/* Update the modem status after a one - character - send wait - time , since there may be a response
from the device / computer at the other end of the serial line */
qemu_mod_timer ( s -> modem_status_poll , qemu_get_clock ( vm_clock ) + s -> char_transmit_time );
}
}
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break ;
case 5 :
break ;
case 6 :
break ;
case 7 :
s -> scr = val ;
break ;
}
}
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static uint32_t serial_ioport_read ( void * opaque , uint32_t addr )
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{
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SerialState * s = opaque ;
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uint32_t ret ;
addr &= 7 ;
switch ( addr ) {
default :
case 0 :
if ( s -> lcr & UART_LCR_DLAB ) {
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ret = s -> divider & 0xff ;
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} else {
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if ( s -> fcr & UART_FCR_FE ) {
ret = fifo_get ( s , RECV_FIFO );
if ( s -> recv_fifo . count == 0 )
s -> lsr &= ~ ( UART_LSR_DR | UART_LSR_BI );
else
qemu_mod_timer ( s -> fifo_timeout_timer , qemu_get_clock ( vm_clock ) + s -> char_transmit_time * 4 );
s -> timeout_ipending = 0 ;
} else {
ret = s -> rbr ;
s -> lsr &= ~ ( UART_LSR_DR | UART_LSR_BI );
}
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serial_update_irq ( s );
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if ( ! ( s -> mcr & UART_MCR_LOOP )) {
/* in loopback mode, don't receive any data */
qemu_chr_accept_input ( s -> chr );
}
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}
break ;
case 1 :
if ( s -> lcr & UART_LCR_DLAB ) {
ret = ( s -> divider >> 8 ) & 0xff ;
} else {
ret = s -> ier ;
}
break ;
case 2 :
ret = s -> iir ;
s -> thr_ipending = 0 ;
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serial_update_irq ( s );
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break ;
case 3 :
ret = s -> lcr ;
break ;
case 4 :
ret = s -> mcr ;
break ;
case 5 :
ret = s -> lsr ;
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/* Clear break interrupt */
if ( s -> lsr & UART_LSR_BI ) {
s -> lsr &= ~ UART_LSR_BI ;
serial_update_irq ( s );
}
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break ;
case 6 :
if ( s -> mcr & UART_MCR_LOOP ) {
/* in loopback , the modem output pins are connected to the
inputs */
ret = ( s -> mcr & 0x0c ) << 4 ;
ret |= ( s -> mcr & 0x02 ) << 3 ;
ret |= ( s -> mcr & 0x01 ) << 5 ;
} else {
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if ( s -> poll_msl >= 0 )
serial_update_msl ( s );
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ret = s -> msr ;
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/* Clear delta bits & msr int after read, if they were set */
if ( s -> msr & UART_MSR_ANY_DELTA ) {
s -> msr &= 0xF0 ;
serial_update_irq ( s );
}
560
561
562
563
564
565
566
567
568
569
570
571
}
break ;
case 7 :
ret = s -> scr ;
break ;
}
# ifdef DEBUG_SERIAL
printf ( "serial: read addr=0x%02x val=0x%02x \n " , addr , ret );
# endif
return ret ;
}
572
static int serial_can_receive ( SerialState * s )
573
{
574
575
576
577
578
579
580
581
582
if ( s -> fcr & UART_FCR_FE ) {
if ( s -> recv_fifo . count < UART_FIFO_LENGTH )
/* Advertise ( fifo . itl - fifo . count ) bytes when count < ITL , and 1 if above . If UART_FIFO_LENGTH - fifo . count is
advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond ,
effectively overriding the ITL that the guest has set . */
return ( s -> recv_fifo . count <= s -> recv_fifo . itl ) ? s -> recv_fifo . itl - s -> recv_fifo . count : 1 ;
else
return 0 ;
} else {
583
return ! ( s -> lsr & UART_LSR_DR );
584
}
585
586
}
587
static void serial_receive_break ( SerialState * s )
588
589
590
{
s -> rbr = 0 ;
s -> lsr |= UART_LSR_BI | UART_LSR_DR ;
591
serial_update_irq ( s );
592
593
}
594
595
596
597
598
599
600
601
602
/* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
static void fifo_timeout_int ( void * opaque ) {
SerialState * s = opaque ;
if ( s -> recv_fifo . count ) {
s -> timeout_ipending = 1 ;
serial_update_irq ( s );
}
}
603
static int serial_can_receive1 ( void * opaque )
604
{
605
606
607
608
609
610
611
SerialState * s = opaque ;
return serial_can_receive ( s );
}
static void serial_receive1 ( void * opaque , const uint8_t * buf , int size )
{
SerialState * s = opaque ;
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620
621
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623
624
if ( s -> fcr & UART_FCR_FE ) {
int i ;
for ( i = 0 ; i < size ; i ++ ) {
fifo_put ( s , RECV_FIFO , buf [ i ]);
}
s -> lsr |= UART_LSR_DR ;
/* call the timeout receive callback in 4 char transmit time */
qemu_mod_timer ( s -> fifo_timeout_timer , qemu_get_clock ( vm_clock ) + s -> char_transmit_time * 4 );
} else {
s -> rbr = buf [ 0 ];
s -> lsr |= UART_LSR_DR ;
}
serial_update_irq ( s );
625
}
626
627
628
629
static void serial_event ( void * opaque , int event )
{
SerialState * s = opaque ;
630
631
632
# ifdef DEBUG_SERIAL
printf ( "serial: event %x \n " , event );
# endif
633
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635
636
if ( event == CHR_EVENT_BREAK )
serial_receive_break ( s );
}
637
638
639
640
static void serial_save ( QEMUFile * f , void * opaque )
{
SerialState * s = opaque ;
641
qemu_put_be16s ( f , & s -> divider );
642
643
644
645
646
647
648
649
qemu_put_8s ( f , & s -> rbr );
qemu_put_8s ( f , & s -> ier );
qemu_put_8s ( f , & s -> iir );
qemu_put_8s ( f , & s -> lcr );
qemu_put_8s ( f , & s -> mcr );
qemu_put_8s ( f , & s -> lsr );
qemu_put_8s ( f , & s -> msr );
qemu_put_8s ( f , & s -> scr );
650
qemu_put_8s ( f , & s -> fcr );
651
652
653
654
655
}
static int serial_load ( QEMUFile * f , void * opaque , int version_id )
{
SerialState * s = opaque ;
656
uint8_t fcr = 0 ;
657
658
if ( version_id > 3 )
659
660
return - EINVAL ;
661
662
663
664
if ( version_id >= 2 )
qemu_get_be16s ( f , & s -> divider );
else
s -> divider = qemu_get_byte ( f );
665
666
667
668
669
670
671
672
673
qemu_get_8s ( f , & s -> rbr );
qemu_get_8s ( f , & s -> ier );
qemu_get_8s ( f , & s -> iir );
qemu_get_8s ( f , & s -> lcr );
qemu_get_8s ( f , & s -> mcr );
qemu_get_8s ( f , & s -> lsr );
qemu_get_8s ( f , & s -> msr );
qemu_get_8s ( f , & s -> scr );
674
675
676
677
678
if ( version_id >= 3 )
qemu_get_8s ( f , & fcr );
/* Initialize fcr via setter to perform essential side-effects */
serial_ioport_write ( s , 0x02 , fcr );
679
680
681
return 0 ;
}
682
683
684
685
686
687
688
689
690
691
static void serial_reset ( void * opaque )
{
SerialState * s = opaque ;
s -> rbr = 0 ;
s -> ier = 0 ;
s -> iir = UART_IIR_NO_INT ;
s -> lcr = 0 ;
s -> lsr = UART_LSR_TEMT | UART_LSR_THRE ;
s -> msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS ;
692
693
694
/* Default to 9600 baud, no parity, one stop bit */
s -> divider = 0x0C ;
s -> mcr = UART_MCR_OUT2 ;
695
s -> scr = 0 ;
696
697
698
699
700
701
702
703
s -> tsr_retry = 0 ;
s -> char_transmit_time = ( ticks_per_sec / 9600 ) * 9 ;
s -> poll_msl = 0 ;
fifo_clear ( s , RECV_FIFO );
fifo_clear ( s , XMIT_FIFO );
s -> last_xmit_ts = qemu_get_clock ( vm_clock );
704
705
706
707
708
709
s -> thr_ipending = 0 ;
s -> last_break_enable = 0 ;
qemu_irq_lower ( s -> irq );
}
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
static void serial_init_core ( SerialState * s , qemu_irq irq , int baudbase ,
CharDriverState * chr )
{
s -> irq = irq ;
s -> baudbase = baudbase ;
s -> chr = chr ;
s -> modem_status_poll = qemu_new_timer ( vm_clock , ( QEMUTimerCB * ) serial_update_msl , s );
s -> fifo_timeout_timer = qemu_new_timer ( vm_clock , ( QEMUTimerCB * ) fifo_timeout_int , s );
s -> transmit_timer = qemu_new_timer ( vm_clock , ( QEMUTimerCB * ) serial_xmit , s );
qemu_register_reset ( serial_reset , s );
serial_reset ( s );
}
727
/* If fd is zero, it means that the serial device uses the console */
728
729
SerialState * serial_init ( int base , qemu_irq irq , int baudbase ,
CharDriverState * chr )
730
731
732
733
734
735
{
SerialState * s ;
s = qemu_mallocz ( sizeof ( SerialState ));
if ( ! s )
return NULL ;
736
737
serial_init_core ( s , irq , baudbase , chr );
738
739
register_savevm ( "serial" , base , 3 , serial_save , serial_load , s );
740
741
742
register_ioport_write ( base , 8 , 1 , serial_ioport_write , s );
register_ioport_read ( base , 8 , 1 , serial_ioport_read , s );
743
744
qemu_chr_add_handlers ( chr , serial_can_receive1 , serial_receive1 ,
serial_event , s );
745
return s ;
746
}
747
748
/* Memory mapped interface */
ths
authored
18 years ago
749
uint32_t serial_mm_readb ( void * opaque , target_phys_addr_t addr )
750
751
752
753
754
755
{
SerialState * s = opaque ;
return serial_ioport_read ( s , ( addr - s -> base ) >> s -> it_shift ) & 0xFF ;
}
ths
authored
18 years ago
756
757
void serial_mm_writeb ( void * opaque ,
target_phys_addr_t addr , uint32_t value )
758
759
760
761
762
763
{
SerialState * s = opaque ;
serial_ioport_write ( s , ( addr - s -> base ) >> s -> it_shift , value & 0xFF );
}
ths
authored
18 years ago
764
uint32_t serial_mm_readw ( void * opaque , target_phys_addr_t addr )
765
766
{
SerialState * s = opaque ;
ths
authored
18 years ago
767
uint32_t val ;
768
ths
authored
18 years ago
769
770
771
772
773
val = serial_ioport_read ( s , ( addr - s -> base ) >> s -> it_shift ) & 0xFFFF ;
# ifdef TARGET_WORDS_BIGENDIAN
val = bswap16 ( val );
# endif
return val ;
774
775
}
ths
authored
18 years ago
776
777
void serial_mm_writew ( void * opaque ,
target_phys_addr_t addr , uint32_t value )
778
779
{
SerialState * s = opaque ;
ths
authored
18 years ago
780
781
782
# ifdef TARGET_WORDS_BIGENDIAN
value = bswap16 ( value );
# endif
783
784
785
serial_ioport_write ( s , ( addr - s -> base ) >> s -> it_shift , value & 0xFFFF );
}
ths
authored
18 years ago
786
uint32_t serial_mm_readl ( void * opaque , target_phys_addr_t addr )
787
788
{
SerialState * s = opaque ;
ths
authored
18 years ago
789
uint32_t val ;
790
ths
authored
18 years ago
791
792
793
794
795
val = serial_ioport_read ( s , ( addr - s -> base ) >> s -> it_shift );
# ifdef TARGET_WORDS_BIGENDIAN
val = bswap32 ( val );
# endif
return val ;
796
797
}
ths
authored
18 years ago
798
799
void serial_mm_writel ( void * opaque ,
target_phys_addr_t addr , uint32_t value )
800
801
{
SerialState * s = opaque ;
ths
authored
18 years ago
802
803
804
# ifdef TARGET_WORDS_BIGENDIAN
value = bswap32 ( value );
# endif
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
serial_ioport_write ( s , ( addr - s -> base ) >> s -> it_shift , value );
}
static CPUReadMemoryFunc * serial_mm_read [] = {
& serial_mm_readb ,
& serial_mm_readw ,
& serial_mm_readl ,
};
static CPUWriteMemoryFunc * serial_mm_write [] = {
& serial_mm_writeb ,
& serial_mm_writew ,
& serial_mm_writel ,
};
820
SerialState * serial_mm_init ( target_phys_addr_t base , int it_shift ,
821
822
qemu_irq irq , int baudbase ,
CharDriverState * chr , int ioregister )
823
824
825
826
827
828
829
{
SerialState * s ;
int s_io_memory ;
s = qemu_mallocz ( sizeof ( SerialState ));
if ( ! s )
return NULL ;
830
831
832
833
s -> base = base ;
s -> it_shift = it_shift ;
834
835
serial_init_core ( s , irq , baudbase , chr );
register_savevm ( "serial" , base , 3 , serial_save , serial_load , s );
836
ths
authored
18 years ago
837
838
839
840
841
if ( ioregister ) {
s_io_memory = cpu_register_io_memory ( 0 , serial_mm_read ,
serial_mm_write , s );
cpu_register_physical_memory ( base , 8 << it_shift , s_io_memory );
}
842
843
qemu_chr_add_handlers ( chr , serial_can_receive1 , serial_receive1 ,
serial_event , s );
844
serial_update_msl ( s );
845
846
return s ;
}