gwj / at91sam9263 · Commits

Commit a4bc3afc09b27cca4adfc1500551cc9a36219edf

Authored by ths
1 parent c62db105

Malta CBUS UART support. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2557 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 5 changed files with 60 additions and 18 deletions
hw/mips_int.c
  View file @a4bc3af
... ... @@ -27,7 +27,7 @@ void cpu_mips_irq_request(void *opaque, int irq, int level)
27 27 if (level) {
28 28 env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
29 29 } else {
30   - env->CP0_Cause &= ~(1 << (irq +CP0Ca_IP));
  30 + env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
31 31 }
32 32 cpu_mips_update_irq(env);
33 33 }
... ...
hw/mips_malta.c
  View file @a4bc3af
... ... @@ -55,6 +55,7 @@ typedef struct {
55 55 uint32_t i2csel;
56 56 CharDriverState *display;
57 57 char display_text[9];
  58 + SerialState *uart;
58 59 } MaltaFPGAState;
59 60  
60 61 static PITState *pit;
... ... @@ -241,6 +242,18 @@ static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr)
241 242 val = s->brk;
242 243 break;
243 244  
  245 + /* UART Registers */
  246 + case 0x00900:
  247 + case 0x00904:
  248 + case 0x00908:
  249 + case 0x0090c:
  250 + case 0x00910:
  251 + case 0x00914:
  252 + case 0x00918:
  253 + case 0x0091c:
  254 + val = serial_mm_readl(s->uart, addr);
  255 + break;
  256 +
244 257 /* GPOUT Register */
245 258 case 0x00a00:
246 259 val = s->gpout;
... ... @@ -341,6 +354,18 @@ static void malta_fpga_writel(void *opaque, target_phys_addr_t addr,
341 354 s->brk = val & 0xff;
342 355 break;
343 356  
  357 + /* UART Registers */
  358 + case 0x00900:
  359 + case 0x00904:
  360 + case 0x00908:
  361 + case 0x0090c:
  362 + case 0x00910:
  363 + case 0x00914:
  364 + case 0x00918:
  365 + case 0x0091c:
  366 + serial_mm_writel(s->uart, addr, val);
  367 + break;
  368 +
344 369 /* GPOUT Register */
345 370 case 0x00a00:
346 371 s->gpout = val & 0xff;
... ... @@ -400,15 +425,17 @@ void malta_fpga_reset(void *opaque)
400 425 malta_fpga_update_display(s);
401 426 }
402 427  
403   -MaltaFPGAState *malta_fpga_init(target_phys_addr_t base)
  428 +MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
404 429 {
405 430 MaltaFPGAState *s;
  431 + CharDriverState *uart_chr;
406 432 int malta;
407 433  
408 434 s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState));
409 435  
410 436 malta = cpu_register_io_memory(0, malta_fpga_read,
411 437 malta_fpga_write, s);
  438 +
412 439 cpu_register_physical_memory(base, 0x100000, malta);
413 440  
414 441 s->display = qemu_chr_open("vc");
... ... @@ -422,6 +449,11 @@ MaltaFPGAState *malta_fpga_init(target_phys_addr_t base)
422 449 qemu_chr_printf(s->display, "+ +\r\n");
423 450 qemu_chr_printf(s->display, "+--------+\r\n");
424 451  
  452 + uart_chr = qemu_chr_open("vc");
  453 + qemu_chr_printf(uart_chr, "CBUS UART\r\n");
  454 + s->uart = serial_mm_init(&cpu_mips_irq_request, env, base, 3, 2,
  455 + uart_chr, 0);
  456 +
425 457 malta_fpga_reset(s);
426 458 qemu_register_reset(malta_fpga_reset, s);
427 459  
... ... @@ -683,7 +715,7 @@ void mips_malta_init (int ram_size, int vga_ram_size, int boot_device,
683 715 cpu_mips_irqctrl_init();
684 716  
685 717 /* FPGA */
686   - malta_fpga = malta_fpga_init(0x1f000000LL);
  718 + malta_fpga = malta_fpga_init(0x1f000000LL, env);
687 719  
688 720 /* Interrupt controller */
689 721 isa_pic = pic_init(pic_irq_request, env);
... ...
hw/serial.c
  View file @a4bc3af
... ... @@ -371,45 +371,45 @@ SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
371 371 }
372 372  
373 373 /* Memory mapped interface */
374   -static uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
  374 +uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
375 375 {
376 376 SerialState *s = opaque;
377 377  
378 378 return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
379 379 }
380 380  
381   -static void serial_mm_writeb (void *opaque,
382   - target_phys_addr_t addr, uint32_t value)
  381 +void serial_mm_writeb (void *opaque,
  382 + target_phys_addr_t addr, uint32_t value)
383 383 {
384 384 SerialState *s = opaque;
385 385  
386 386 serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
387 387 }
388 388  
389   -static uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
  389 +uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
390 390 {
391 391 SerialState *s = opaque;
392 392  
393 393 return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
394 394 }
395 395  
396   -static void serial_mm_writew (void *opaque,
397   - target_phys_addr_t addr, uint32_t value)
  396 +void serial_mm_writew (void *opaque,
  397 + target_phys_addr_t addr, uint32_t value)
398 398 {
399 399 SerialState *s = opaque;
400 400  
401 401 serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
402 402 }
403 403  
404   -static uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
  404 +uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
405 405 {
406 406 SerialState *s = opaque;
407 407  
408 408 return serial_ioport_read(s, (addr - s->base) >> s->it_shift);
409 409 }
410 410  
411   -static void serial_mm_writel (void *opaque,
412   - target_phys_addr_t addr, uint32_t value)
  411 +void serial_mm_writel (void *opaque,
  412 + target_phys_addr_t addr, uint32_t value)
413 413 {
414 414 SerialState *s = opaque;
415 415  
... ... @@ -430,7 +430,8 @@ static CPUWriteMemoryFunc *serial_mm_write[] = {
430 430  
431 431 SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
432 432 target_ulong base, int it_shift,
433   - int irq, CharDriverState *chr)
  433 + int irq, CharDriverState *chr,
  434 + int ioregister)
434 435 {
435 436 SerialState *s;
436 437 int s_io_memory;
... ... @@ -449,9 +450,11 @@ SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
449 450  
450 451 register_savevm("serial", base, 2, serial_save, serial_load, s);
451 452  
452   - s_io_memory = cpu_register_io_memory(0, serial_mm_read,
453   - serial_mm_write, s);
454   - cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
  453 + if (ioregister) {
  454 + s_io_memory = cpu_register_io_memory(0, serial_mm_read,
  455 + serial_mm_write, s);
  456 + cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
  457 + }
455 458 s->chr = chr;
456 459 qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
457 460 serial_event, s);
... ...
target-mips/exec.h
  View file @a4bc3af
... ... @@ -163,7 +163,7 @@ uint32_t cpu_mips_get_random (CPUState *env);
163 163 uint32_t cpu_mips_get_count (CPUState *env);
164 164 void cpu_mips_store_count (CPUState *env, uint32_t value);
165 165 void cpu_mips_store_compare (CPUState *env, uint32_t value);
166   -void cpu_mips_update_irq(CPUState *env);
  166 +void cpu_mips_update_irq (CPUState *env);
167 167 void cpu_mips_clock_init (CPUState *env);
168 168 void cpu_mips_tlb_flush (CPUState *env, int flush_global);
169 169  
... ...
... ... @@ -1035,7 +1035,14 @@ SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
1035 1035 int base, int irq, CharDriverState *chr);
1036 1036 SerialState *serial_mm_init (SetIRQFunc *set_irq, void *opaque,
1037 1037 target_ulong base, int it_shift,
1038   - int irq, CharDriverState *chr);
  1038 + int irq, CharDriverState *chr,
  1039 + int ioregister);
  1040 +uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
  1041 +void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
  1042 +uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
  1043 +void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
  1044 +uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
  1045 +void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1039 1046  
1040 1047 /* parallel.c */
1041 1048  
... ...