gwj / at91sam9263 · Commits

Commit b6cd0ea1205dd4623ccfe796ee6c1a4da3141d99

Authored by aurel32
1 parent 6936bfe5

8250: Customized base baudrate 

(Jan Kiszka)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4336 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 14 changed files with 36 additions and 25 deletions
hw/mips_jazz.c
  View file @b6cd0ea
... ... @@ -234,9 +234,9 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
234 234  
235 235 /* Serial ports */
236 236 if (serial_hds[0])
237   - serial_mm_init(0x80006000, 0, rc4030[8], serial_hds[0], 1);
  237 + serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1);
238 238 if (serial_hds[1])
239   - serial_mm_init(0x80007000, 0, rc4030[9], serial_hds[1], 1);
  239 + serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1);
240 240  
241 241 /* Parallel port */
242 242 if (parallel_hds[0])
... ...
hw/mips_malta.c
  View file @b6cd0ea
... ... @@ -449,7 +449,8 @@ static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
449 449  
450 450 uart_chr = qemu_chr_open("vc:80Cx24C");
451 451 qemu_chr_printf(uart_chr, "CBUS UART\r\n");
452   - s->uart = serial_mm_init(base + 0x900, 3, env->irq[2], uart_chr, 1);
  452 + s->uart =
  453 + serial_mm_init(base + 0x900, 3, env->irq[2], 230400, uart_chr, 1);
453 454  
454 455 malta_fpga_reset(s);
455 456 qemu_register_reset(malta_fpga_reset, s);
... ... @@ -918,9 +919,9 @@ void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
918 919 i8042_init(i8259[1], i8259[12], 0x60);
919 920 rtc_state = rtc_init(0x70, i8259[8]);
920 921 if (serial_hds[0])
921   - serial_init(0x3f8, i8259[4], serial_hds[0]);
  922 + serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
922 923 if (serial_hds[1])
923   - serial_init(0x2f8, i8259[3], serial_hds[1]);
  924 + serial_init(0x2f8, i8259[3], 115200, serial_hds[1]);
924 925 if (parallel_hds[0])
925 926 parallel_init(0x378, i8259[7], parallel_hds[0]);
926 927 for(i = 0; i < MAX_FD; i++) {
... ...
hw/mips_mipssim.c
  View file @b6cd0ea
... ... @@ -174,7 +174,7 @@ mips_mipssim_init (ram_addr_t ram_size, int vga_ram_size,
174 174 /* A single 16450 sits at offset 0x3f8. It is attached to
175 175 MIPS CPU INT2, which is interrupt 4. */
176 176 if (serial_hds[0])
177   - serial_init(0x3f8, env->irq[4], serial_hds[0]);
  177 + serial_init(0x3f8, env->irq[4], 115200, serial_hds[0]);
178 178  
179 179 if (nd_table[0].vlan) {
180 180 if (nd_table[0].model == NULL
... ...
hw/mips_r4k.c
  View file @b6cd0ea
... ... @@ -241,7 +241,8 @@ void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size,
241 241  
242 242 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
243 243 if (serial_hds[i]) {
244   - serial_init(serial_io[i], i8259[serial_irq[i]], serial_hds[i]);
  244 + serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
  245 + serial_hds[i]);
245 246 }
246 247 }
247 248  
... ...
hw/musicpal.c
  View file @b6cd0ea
... ... @@ -1448,10 +1448,10 @@ static void musicpal_init(ram_addr_t ram_size, int vga_ram_size,
1448 1448 mv88w8618_pit_init(MP_PIT_BASE, pic, MP_TIMER1_IRQ);
1449 1449  
1450 1450 if (serial_hds[0])
1451   - serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], /*1825000,*/
  1451 + serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
1452 1452 serial_hds[0], 1);
1453 1453 if (serial_hds[1])
1454   - serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], /*1825000,*/
  1454 + serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
1455 1455 serial_hds[1], 1);
1456 1456  
1457 1457 /* Register flash */
... ...
hw/omap1.c
  View file @b6cd0ea
... ... @@ -2006,7 +2006,8 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
2006 2006 struct omap_uart_s *s = (struct omap_uart_s *)
2007 2007 qemu_mallocz(sizeof(struct omap_uart_s));
2008 2008  
2009   - s->serial = serial_mm_init(base, 2, irq, chr ?: qemu_chr_open("null"), 1);
  2009 + s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
  2010 + chr ?: qemu_chr_open("null"), 1);
2010 2011  
2011 2012 return s;
2012 2013 }
... ...
... ... @@ -930,7 +930,8 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
930 930  
931 931 for(i = 0; i < MAX_SERIAL_PORTS; i++) {
932 932 if (serial_hds[i]) {
933   - serial_init(serial_io[i], i8259[serial_irq[i]], serial_hds[i]);
  933 + serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
  934 + serial_hds[i]);
934 935 }
935 936 }
936 937  
... ...
... ... @@ -4,10 +4,11 @@
4 4  
5 5 /* serial.c */
6 6  
7   -SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
  7 +SerialState *serial_init(int base, qemu_irq irq, int baudbase,
  8 + CharDriverState *chr);
8 9 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
9   - qemu_irq irq, CharDriverState *chr,
10   - int ioregister);
  10 + qemu_irq irq, int baudbase,
  11 + CharDriverState *chr, int ioregister);
11 12 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
12 13 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
13 14 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
... ...
hw/ppc405_uc.c
  View file @b6cd0ea
... ... @@ -1223,7 +1223,7 @@ void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
1223 1223 #ifdef DEBUG_SERIAL
1224 1224 printf("%s: offset " PADDRX "\n", __func__, offset);
1225 1225 #endif
1226   - serial = serial_mm_init(offset, 0, irq, chr, 0);
  1226 + serial = serial_mm_init(offset, 0, irq, 399193, chr, 0);
1227 1227 ppc4xx_mmio_register(env, mmio, offset, 0x008,
1228 1228 serial_mm_read, serial_mm_write, serial);
1229 1229 }
... ...
hw/ppc_chrp.c
  View file @b6cd0ea
... ... @@ -264,7 +264,7 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
264 264 dummy_irq = i8259_init(NULL);
265 265  
266 266 /* XXX: use Mac Serial port */
267   - serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
  267 + serial_init(0x3f8, dummy_irq[4], 115200, serial_hds[0]);
268 268 for(i = 0; i < nb_nics; i++) {
269 269 if (!nd_table[i].model)
270 270 nd_table[i].model = "ne2k_pci";
... ...
hw/ppc_oldworld.c
  View file @b6cd0ea
... ... @@ -287,7 +287,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
287 287 dummy_irq = i8259_init(NULL);
288 288  
289 289 /* XXX: use Mac Serial port */
290   - serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
  290 + serial_init(0x3f8, dummy_irq[4], 115200, serial_hds[0]);
291 291  
292 292 for(i = 0; i < nb_nics; i++) {
293 293 if (!nd_table[i].model)
... ...
hw/ppc_prep.c
  View file @b6cd0ea
... ... @@ -667,7 +667,7 @@ static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
667 667 // pit = pit_init(0x40, i8259[0]);
668 668 rtc_init(0x70, i8259[8]);
669 669  
670   - serial_init(0x3f8, i8259[4], serial_hds[0]);
  670 + serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
671 671 nb_nics1 = nb_nics;
672 672 if (nb_nics1 > NE2000_NB_MAX)
673 673 nb_nics1 = NE2000_NB_MAX;
... ...
hw/pxa2xx.c
  View file @b6cd0ea
... ... @@ -2077,7 +2077,8 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
2077 2077 for (i = 0; pxa270_serial[i].io_base; i ++)
2078 2078 if (serial_hds[i])
2079 2079 serial_mm_init(pxa270_serial[i].io_base, 2,
2080   - s->pic[pxa270_serial[i].irqn], serial_hds[i], 1);
  2080 + s->pic[pxa270_serial[i].irqn], 14857000/16,
  2081 + serial_hds[i], 1);
2081 2082 else
2082 2083 break;
2083 2084 if (serial_hds[i])
... ... @@ -2202,7 +2203,8 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
2202 2203 for (i = 0; pxa255_serial[i].io_base; i ++)
2203 2204 if (serial_hds[i])
2204 2205 serial_mm_init(pxa255_serial[i].io_base, 2,
2205   - s->pic[pxa255_serial[i].irqn], serial_hds[i], 1);
  2206 + s->pic[pxa255_serial[i].irqn], 14745600/16,
  2207 + serial_hds[i], 1);
2206 2208 else
2207 2209 break;
2208 2210 if (serial_hds[i])
... ...
hw/serial.c
  View file @b6cd0ea
... ... @@ -99,6 +99,7 @@ struct SerialState {
99 99 int last_break_enable;
100 100 target_phys_addr_t base;
101 101 int it_shift;
  102 + int baudbase;
102 103 QEMUTimer *tx_timer;
103 104 int tx_burst;
104 105 };
... ... @@ -135,7 +136,7 @@ static void serial_tx_done(void *opaque)
135 136  
136 137 /* We assume 10 bits/char, OK for this purpose. */
137 138 s->tx_burst = THROTTLE_TX_INTERVAL * 1000 /
138   - (1000000 * 10 / (115200 / divider));
  139 + (1000000 * 10 / (s->baudbase / divider));
139 140 }
140 141 s->thr_ipending = 1;
141 142 s->lsr |= UART_LSR_THRE;
... ... @@ -163,7 +164,7 @@ static void serial_update_parameters(SerialState *s)
163 164 data_bits = (s->lcr & 0x03) + 5;
164 165 if (s->divider == 0)
165 166 return;
166   - speed = 115200 / s->divider;
  167 + speed = s->baudbase / s->divider;
167 168 ssp.speed = speed;
168 169 ssp.parity = parity;
169 170 ssp.data_bits = data_bits;
... ... @@ -413,7 +414,8 @@ static void serial_reset(void *opaque)
413 414 }
414 415  
415 416 /* If fd is zero, it means that the serial device uses the console */
416   -SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr)
  417 +SerialState *serial_init(int base, qemu_irq irq, int baudbase,
  418 + CharDriverState *chr)
417 419 {
418 420 SerialState *s;
419 421  
... ... @@ -421,6 +423,7 @@ SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr)
421 423 if (!s)
422 424 return NULL;
423 425 s->irq = irq;
  426 + s->baudbase = baudbase;
424 427  
425 428 s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s);
426 429 if (!s->tx_timer)
... ... @@ -512,8 +515,8 @@ static CPUWriteMemoryFunc *serial_mm_write[] = {
512 515 };
513 516  
514 517 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
515   - qemu_irq irq, CharDriverState *chr,
516   - int ioregister)
  518 + qemu_irq irq, int baudbase,
  519 + CharDriverState *chr, int ioregister)
517 520 {
518 521 SerialState *s;
519 522 int s_io_memory;
... ... @@ -524,6 +527,7 @@ SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
524 527 s->irq = irq;
525 528 s->base = base;
526 529 s->it_shift = it_shift;
  530 + s->baudbase= baudbase;
527 531  
528 532 s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s);
529 533 if (!s->tx_timer)
... ...