8250: Customized base baudrate

(Jan Kiszka) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4336 c046a42c-6fe2-441c-8c8c-71466251a162

8250: Customized base baudrate
(Jan Kiszka) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4336 c046a42c-6fe2-441c-8c8c-71466251a162
aurel32
1 parent 6936bfe5
Showing 14 changed files with 36 additions and 25 deletions
hw/mips_jazz.c
hw/mips_malta.c
hw/mips_mipssim.c
hw/mips_r4k.c
hw/musicpal.c
hw/omap1.c
hw/pc.c
hw/pc.h
hw/ppc405_uc.c
hw/ppc_chrp.c
hw/ppc_oldworld.c
hw/ppc_prep.c
hw/pxa2xx.c
hw/serial.c
@@ -234,9 +234,9 @@ void mips_jazz_init (ram_addr_t ram_size, int vga_ram_size,
     /* Serial ports */
     if (serial_hds[0])
-        serial_mm_init(0x80006000, 0, rc4030[8], serial_hds[0], 1);
+        serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1);
     if (serial_hds[1])
-        serial_mm_init(0x80007000, 0, rc4030[9], serial_hds[1], 1);
+        serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1);
     /* Parallel port */
     if (parallel_hds[0])
@@ -449,7 +449,8 @@ static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, CPUState *env)
     uart_chr = qemu_chr_open("vc:80Cx24C");
     qemu_chr_printf(uart_chr, "CBUS UART\r\n");
-    s->uart = serial_mm_init(base + 0x900, 3, env->irq[2], uart_chr, 1);
+    s->uart =
+        serial_mm_init(base + 0x900, 3, env->irq[2], 230400, uart_chr, 1);
     malta_fpga_reset(s);
     qemu_register_reset(malta_fpga_reset, s);
@@ -918,9 +919,9 @@ void mips_malta_init (ram_addr_t ram_size, int vga_ram_size,
     i8042_init(i8259[1], i8259[12], 0x60);
     rtc_state = rtc_init(0x70, i8259[8]);
     if (serial_hds[0])
-        serial_init(0x3f8, i8259[4], serial_hds[0]);
+        serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
     if (serial_hds[1])
-        serial_init(0x2f8, i8259[3], serial_hds[1]);
+        serial_init(0x2f8, i8259[3], 115200, serial_hds[1]);
     if (parallel_hds[0])
         parallel_init(0x378, i8259[7], parallel_hds[0]);
     for(i = 0; i < MAX_FD; i++) {
@@ -174,7 +174,7 @@ mips_mipssim_init (ram_addr_t ram_size, int vga_ram_size,
     /* A single 16450 sits at offset 0x3f8. It is attached to
        MIPS CPU INT2, which is interrupt 4. */
     if (serial_hds[0])
-        serial_init(0x3f8, env->irq[4], serial_hds[0]);
+        serial_init(0x3f8, env->irq[4], 115200, serial_hds[0]);
     if (nd_table[0].vlan) {
         if (nd_table[0].model == NULL
@@ -241,7 +241,8 @@ void mips_r4k_init (ram_addr_t ram_size, int vga_ram_size,
     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
         if (serial_hds[i]) {
-            serial_init(serial_io[i], i8259[serial_irq[i]], serial_hds[i]);
+            serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
+                        serial_hds[i]);
         }
     }
@@ -1448,10 +1448,10 @@ static void musicpal_init(ram_addr_t ram_size, int vga_ram_size,
     mv88w8618_pit_init(MP_PIT_BASE, pic, MP_TIMER1_IRQ);
     if (serial_hds[0])
-        serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], /*1825000,*/
+        serial_mm_init(MP_UART1_BASE, 2, pic[MP_UART1_IRQ], 1825000,
                    serial_hds[0], 1);
     if (serial_hds[1])
-        serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], /*1825000,*/
+        serial_mm_init(MP_UART2_BASE, 2, pic[MP_UART2_IRQ], 1825000,
                    serial_hds[1], 1);
     /* Register flash */
@@ -2006,7 +2006,8 @@ struct omap_uart_s *omap_uart_init(target_phys_addr_t base,
     struct omap_uart_s *s = (struct omap_uart_s *)
             qemu_mallocz(sizeof(struct omap_uart_s));
-    s->serial = serial_mm_init(base, 2, irq, chr ?: qemu_chr_open("null"), 1);
+    s->serial = serial_mm_init(base, 2, irq, omap_clk_getrate(fclk)/16,
+                               chr ?: qemu_chr_open("null"), 1);
     return s;
 }
@@ -930,7 +930,8 @@ static void pc_init1(ram_addr_t ram_size, int vga_ram_size,
     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
         if (serial_hds[i]) {
-            serial_init(serial_io[i], i8259[serial_irq[i]], serial_hds[i]);
+            serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
+                        serial_hds[i]);
         }
     }
@@ -4,10 +4,11 @@
 /* serial.c */
-SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
+SerialState *serial_init(int base, qemu_irq irq, int baudbase,
+                         CharDriverState *chr);
 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
-                             qemu_irq irq, CharDriverState *chr,
-                             int ioregister);
+                             qemu_irq irq, int baudbase,
+                             CharDriverState *chr, int ioregister);
 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
@@ -1223,7 +1223,7 @@ void ppc405_serial_init (CPUState *env, ppc4xx_mmio_t *mmio,
 #ifdef DEBUG_SERIAL
     printf("%s: offset " PADDRX "\n", __func__, offset);
 #endif
-    serial = serial_mm_init(offset, 0, irq, chr, 0);
+    serial = serial_mm_init(offset, 0, irq, 399193, chr, 0);
     ppc4xx_mmio_register(env, mmio, offset, 0x008,
                          serial_mm_read, serial_mm_write, serial);
 }
@@ -264,7 +264,7 @@ static void ppc_core99_init (ram_addr_t ram_size, int vga_ram_size,
     dummy_irq = i8259_init(NULL);
     /* XXX: use Mac Serial port */
-    serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
+    serial_init(0x3f8, dummy_irq[4], 115200, serial_hds[0]);
     for(i = 0; i < nb_nics; i++) {
         if (!nd_table[i].model)
             nd_table[i].model = "ne2k_pci";
@@ -287,7 +287,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, int vga_ram_size,
     dummy_irq = i8259_init(NULL);
     /* XXX: use Mac Serial port */
-    serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
+    serial_init(0x3f8, dummy_irq[4], 115200, serial_hds[0]);
     for(i = 0; i < nb_nics; i++) {
         if (!nd_table[i].model)
@@ -667,7 +667,7 @@ static void ppc_prep_init (ram_addr_t ram_size, int vga_ram_size,
     //    pit = pit_init(0x40, i8259[0]);
     rtc_init(0x70, i8259[8]);
-    serial_init(0x3f8, i8259[4], serial_hds[0]);
+    serial_init(0x3f8, i8259[4], 115200, serial_hds[0]);
     nb_nics1 = nb_nics;
     if (nb_nics1 > NE2000_NB_MAX)
         nb_nics1 = NE2000_NB_MAX;
@@ -2077,7 +2077,8 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
     for (i = 0; pxa270_serial[i].io_base; i ++)
         if (serial_hds[i])
             serial_mm_init(pxa270_serial[i].io_base, 2,
-                            s->pic[pxa270_serial[i].irqn], serial_hds[i], 1);
+                           s->pic[pxa270_serial[i].irqn], 14857000/16,
+                           serial_hds[i], 1);
         else
             break;
     if (serial_hds[i])
@@ -2202,7 +2203,8 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
     for (i = 0; pxa255_serial[i].io_base; i ++)
         if (serial_hds[i])
             serial_mm_init(pxa255_serial[i].io_base, 2,
-                            s->pic[pxa255_serial[i].irqn], serial_hds[i], 1);
+                           s->pic[pxa255_serial[i].irqn], 14745600/16,
+                           serial_hds[i], 1);
         else
             break;
     if (serial_hds[i])
@@ -99,6 +99,7 @@ struct SerialState {
     int last_break_enable;
     target_phys_addr_t base;
     int it_shift;
+    int baudbase;
     QEMUTimer *tx_timer;
     int tx_burst;
 };
@@ -135,7 +136,7 @@ static void serial_tx_done(void *opaque)
         /* We assume 10 bits/char, OK for this purpose. */
         s->tx_burst = THROTTLE_TX_INTERVAL * 1000 /
-            (1000000 * 10 / (115200 / divider));
+            (1000000 * 10 / (s->baudbase / divider));
     }
     s->thr_ipending = 1;
     s->lsr |= UART_LSR_THRE;
@@ -163,7 +164,7 @@ static void serial_update_parameters(SerialState *s)
     data_bits = (s->lcr & 0x03) + 5;
     if (s->divider == 0)
         return;
-    speed = 115200 / s->divider;
+    speed = s->baudbase / s->divider;
     ssp.speed = speed;
     ssp.parity = parity;
     ssp.data_bits = data_bits;
@@ -413,7 +414,8 @@ static void serial_reset(void *opaque)
 }
 /* If fd is zero, it means that the serial device uses the console */
-SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr)
+SerialState *serial_init(int base, qemu_irq irq, int baudbase,
+                         CharDriverState *chr)
 {
     SerialState *s;
@@ -421,6 +423,7 @@ SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr)
     if (!s)
         return NULL;
     s->irq = irq;
+    s->baudbase = baudbase;
     s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s);
     if (!s->tx_timer)
@@ -512,8 +515,8 @@ static CPUWriteMemoryFunc *serial_mm_write[] = {
 };
 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
-                             qemu_irq irq, CharDriverState *chr,
-                             int ioregister)
+                             qemu_irq irq, int baudbase,
+                             CharDriverState *chr, int ioregister)
 {
     SerialState *s;
     int s_io_memory;
@@ -524,6 +527,7 @@ SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
     s->irq = irq;
     s->base = base;
     s->it_shift = it_shift;
+    s->baudbase= baudbase;
     s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s);
     if (!s->tx_timer)