gwj / at91sam9263 · Commits

Commit 71db710f7ee00cf324153bbc203e6dad8c99850b

Authored by blueswir1
1 parent 740733bb

Fix incorrect target_ulong use in hw devices 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2962 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 9 changed files with 49 additions and 42 deletions
hw/dma.c
  View file @71db710
... ... @@ -383,7 +383,7 @@ void DMA_register_channel (int nchan,
383 383 int DMA_read_memory (int nchan, void *buf, int pos, int len)
384 384 {
385 385 struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
386   - target_ulong addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
  386 + target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
387 387  
388 388 if (r->mode & 0x20) {
389 389 int i;
... ... @@ -405,7 +405,7 @@ int DMA_read_memory (int nchan, void *buf, int pos, int len)
405 405 int DMA_write_memory (int nchan, void *buf, int pos, int len)
406 406 {
407 407 struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
408   - target_ulong addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
  408 + target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
409 409  
410 410 if (r->mode & 0x20) {
411 411 int i;
... ...
hw/ds1225y.c
  View file @71db710
... ... @@ -33,7 +33,7 @@ typedef enum
33 33  
34 34 struct ds1225y_t
35 35 {
36   - target_ulong mem_base;
  36 + target_phys_addr_t mem_base;
37 37 uint32_t capacity;
38 38 const char *filename;
39 39 QEMUFile *file;
... ... @@ -99,7 +99,7 @@ static CPUWriteMemoryFunc *nvram_none[] = {
99 99 };
100 100  
101 101 /* Initialisation routine */
102   -ds1225y_t *ds1225y_init(target_ulong mem_base, const char *filename)
  102 +ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename)
103 103 {
104 104 ds1225y_t *s;
105 105 int mem_index1, mem_index2;
... ...
hw/pckbd.c
  View file @71db710
... ... @@ -421,8 +421,8 @@ static CPUWriteMemoryFunc *kbd_mm_write[] = {
421 421 &kbd_mm_writeb,
422 422 };
423 423  
424   -void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, target_ulong base,
425   - int it_shift)
  424 +void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
  425 + target_phys_addr_t base, int it_shift)
426 426 {
427 427 KBDState *s = &kbd_state;
428 428 int s_io_memory;
... ...
hw/pflash_cfi02.c
  View file @71db710
... ... @@ -50,9 +50,9 @@ do { \
50 50  
51 51 struct pflash_t {
52 52 BlockDriverState *bs;
53   - target_ulong base;
54   - target_ulong sector_len;
55   - target_ulong total_len;
  53 + target_phys_addr_t base;
  54 + uint32_t sector_len;
  55 + uint32_t total_len;
56 56 int width;
57 57 int wcycle; /* if 0, the flash is read normally */
58 58 int bypass;
... ... @@ -85,9 +85,9 @@ static void pflash_timer (void *opaque)
85 85 pfl->cmd = 0;
86 86 }
87 87  
88   -static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width)
  88 +static uint32_t pflash_read (pflash_t *pfl, uint32_t offset, int width)
89 89 {
90   - target_ulong boff;
  90 + uint32_t boff;
91 91 uint32_t ret;
92 92 uint8_t *p;
93 93  
... ... @@ -199,10 +199,10 @@ static void pflash_update(pflash_t *pfl, int offset,
199 199 }
200 200 }
201 201  
202   -static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
  202 +static void pflash_write (pflash_t *pfl, uint32_t offset, uint32_t value,
203 203 int width)
204 204 {
205   - target_ulong boff;
  205 + uint32_t boff;
206 206 uint8_t *p;
207 207 uint8_t cmd;
208 208  
... ... @@ -219,7 +219,7 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
219 219 DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d %d\n", __func__,
220 220 offset, value, width, pfl->wcycle);
221 221 if (pfl->wcycle == 0)
222   - offset -= (target_ulong)(long)pfl->storage;
  222 + offset -= (uint32_t)(long)pfl->storage;
223 223 else
224 224 offset -= pfl->base;
225 225  
... ... @@ -521,14 +521,14 @@ static int ctz32 (uint32_t n)
521 521 return ret;
522 522 }
523 523  
524   -pflash_t *pflash_register (target_ulong base, ram_addr_t off,
  524 +pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
525 525 BlockDriverState *bs,
526   - target_ulong sector_len, int nb_blocs, int width,
  526 + uint32_t sector_len, int nb_blocs, int width,
527 527 uint16_t id0, uint16_t id1,
528 528 uint16_t id2, uint16_t id3)
529 529 {
530 530 pflash_t *pfl;
531   - target_long total_len;
  531 + int32_t total_len;
532 532  
533 533 total_len = sector_len * nb_blocs;
534 534 /* XXX: to be fixed */
... ...
hw/ppc405.h
  View file @71db710
... ... @@ -83,7 +83,8 @@ qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
83 83 uint32_t dcr_base, int has_ssr, int has_vr);
84 84 /* SDRAM controller */
85 85 void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
86   - target_ulong *ram_bases, target_ulong *ram_sizes,
  86 + target_phys_addr_t *ram_bases,
  87 + target_phys_addr_t *ram_sizes,
87 88 int do_init);
88 89 /* Peripheral controller */
89 90 void ppc405_ebc_init (CPUState *env);
... ... @@ -107,15 +108,17 @@ void ppc4xx_gpt_init (CPUState *env, ppc4xx_mmio_t *mmio,
107 108 /* Memory access layer */
108 109 void ppc405_mal_init (CPUState *env, qemu_irq irqs[4]);
109 110 /* PowerPC 405 microcontrollers */
110   -CPUState *ppc405cr_init (target_ulong ram_bases[4], target_ulong ram_sizes[4],
  111 +CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
  112 + target_phys_addr_t ram_sizes[4],
111 113 uint32_t sysclk, qemu_irq **picp,
112 114 ram_addr_t *offsetp, int do_init);
113   -CPUState *ppc405ep_init (target_ulong ram_bases[2], target_ulong ram_sizes[2],
  115 +CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
  116 + target_phys_addr_t ram_sizes[2],
114 117 uint32_t sysclk, qemu_irq **picp,
115 118 ram_addr_t *offsetp, int do_init);
116 119 /* IBM STBxxx microcontrollers */
117   -CPUState *ppc_stb025_init (target_ulong ram_bases[2],
118   - target_ulong ram_sizes[2],
  120 +CPUState *ppc_stb025_init (target_phys_addr_t ram_bases[2],
  121 + target_phys_addr_t ram_sizes[2],
119 122 uint32_t sysclk, qemu_irq **picp,
120 123 ram_addr_t *offsetp);
121 124  
... ...
hw/ppc405_boards.c
  View file @71db710
... ... @@ -184,7 +184,7 @@ static void ref405ep_init (int ram_size, int vga_ram_size, int boot_device,
184 184 CPUPPCState *env;
185 185 qemu_irq *pic;
186 186 ram_addr_t sram_offset, bios_offset, bdloc;
187   - target_ulong ram_bases[2], ram_sizes[2];
  187 + target_phys_addr_t ram_bases[2], ram_sizes[2];
188 188 target_ulong sram_size, bios_size;
189 189 //int phy_addr = 0;
190 190 //static int phy_addr = 1;
... ... @@ -506,7 +506,7 @@ static void taihu_405ep_init(int ram_size, int vga_ram_size, int boot_device,
506 506 CPUPPCState *env;
507 507 qemu_irq *pic;
508 508 ram_addr_t bios_offset;
509   - target_ulong ram_bases[2], ram_sizes[2];
  509 + target_phys_addr_t ram_bases[2], ram_sizes[2];
510 510 target_ulong bios_size;
511 511 target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
512 512 int linux_boot;
... ...
hw/ppc405_uc.c
  View file @71db710
... ... @@ -903,8 +903,8 @@ typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
903 903 struct ppc4xx_sdram_t {
904 904 uint32_t addr;
905 905 int nbanks;
906   - target_ulong ram_bases[4];
907   - target_ulong ram_sizes[4];
  906 + target_phys_addr_t ram_bases[4];
  907 + target_phys_addr_t ram_sizes[4];
908 908 uint32_t besr0;
909 909 uint32_t besr1;
910 910 uint32_t bear;
... ... @@ -924,7 +924,7 @@ enum {
924 924 SDRAM0_CFGDATA = 0x011,
925 925 };
926 926  
927   -static uint32_t sdram_bcr (target_ulong ram_base, target_ulong ram_size)
  927 +static uint32_t sdram_bcr (target_phys_addr_t ram_base, target_phys_addr_t ram_size)
928 928 {
929 929 uint32_t bcr;
930 930  
... ... @@ -960,7 +960,7 @@ static uint32_t sdram_bcr (target_ulong ram_base, target_ulong ram_size)
960 960 return bcr;
961 961 }
962 962  
963   -static inline target_ulong sdram_base (uint32_t bcr)
  963 +static inline target_phys_addr_t sdram_base (uint32_t bcr)
964 964 {
965 965 return bcr & 0xFF800000;
966 966 }
... ... @@ -1206,7 +1206,8 @@ static void sdram_reset (void *opaque)
1206 1206 }
1207 1207  
1208 1208 void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
1209   - target_ulong *ram_bases, target_ulong *ram_sizes,
  1209 + target_phys_addr_t *ram_bases,
  1210 + target_phys_addr_t *ram_sizes,
1210 1211 int do_init)
1211 1212 {
1212 1213 ppc4xx_sdram_t *sdram;
... ... @@ -1215,10 +1216,10 @@ void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
1215 1216 if (sdram != NULL) {
1216 1217 sdram->irq = irq;
1217 1218 sdram->nbanks = nbanks;
1218   - memset(sdram->ram_bases, 0, 4 * sizeof(target_ulong));
1219   - memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(target_ulong));
1220   - memset(sdram->ram_sizes, 0, 4 * sizeof(target_ulong));
1221   - memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(target_ulong));
  1219 + memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
  1220 + memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(target_phys_addr_t));
  1221 + memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
  1222 + memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(target_phys_addr_t));
1222 1223 sdram_reset(sdram);
1223 1224 qemu_register_reset(&sdram_reset, sdram);
1224 1225 ppc_dcr_register(env, SDRAM0_CFGADDR,
... ... @@ -3017,7 +3018,8 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7],
3017 3018 }
3018 3019 }
3019 3020  
3020   -CPUState *ppc405cr_init (target_ulong ram_bases[4], target_ulong ram_sizes[4],
  3021 +CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
  3022 + target_phys_addr_t ram_sizes[4],
3021 3023 uint32_t sysclk, qemu_irq **picp,
3022 3024 ram_addr_t *offsetp, int do_init)
3023 3025 {
... ... @@ -3365,7 +3367,8 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8],
3365 3367 }
3366 3368 }
3367 3369  
3368   -CPUState *ppc405ep_init (target_ulong ram_bases[2], target_ulong ram_sizes[2],
  3370 +CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
  3371 + target_phys_addr_t ram_sizes[2],
3369 3372 uint32_t sysclk, qemu_irq **picp,
3370 3373 ram_addr_t *offsetp, int do_init)
3371 3374 {
... ...
hw/serial.c
  View file @71db710
... ... @@ -86,7 +86,7 @@ struct SerialState {
86 86 qemu_irq irq;
87 87 CharDriverState *chr;
88 88 int last_break_enable;
89   - target_ulong base;
  89 + target_phys_addr_t base;
90 90 int it_shift;
91 91 };
92 92  
... ... @@ -437,7 +437,7 @@ static CPUWriteMemoryFunc *serial_mm_write[] = {
437 437 &serial_mm_writel,
438 438 };
439 439  
440   -SerialState *serial_mm_init (target_ulong base, int it_shift,
  440 +SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
441 441 qemu_irq irq, CharDriverState *chr,
442 442 int ioregister)
443 443 {
... ...
... ... @@ -994,7 +994,7 @@ int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
994 994  
995 995 /* ds1225y.c */
996 996 typedef struct ds1225y_t ds1225y_t;
997   -ds1225y_t *ds1225y_init(target_ulong mem_base, const char *filename);
  997 +ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
998 998  
999 999 /* es1370.c */
1000 1000 int es1370_init (PCIBus *bus, AudioState *s);
... ... @@ -1059,7 +1059,8 @@ void *vmmouse_init(void *m);
1059 1059 /* pckbd.c */
1060 1060  
1061 1061 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1062   -void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, target_ulong base, int it_shift);
  1062 +void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
  1063 + target_phys_addr_t base, int it_shift);
1063 1064  
1064 1065 /* mc146818rtc.c */
1065 1066  
... ... @@ -1074,7 +1075,7 @@ void rtc_set_date(RTCState *s, const struct tm *tm);
1074 1075  
1075 1076 typedef struct SerialState SerialState;
1076 1077 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1077   -SerialState *serial_mm_init (target_ulong base, int it_shift,
  1078 +SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1078 1079 qemu_irq irq, CharDriverState *chr,
1079 1080 int ioregister);
1080 1081 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
... ... @@ -1485,9 +1486,9 @@ int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1485 1486 extern BlockDriverState *pflash_table[MAX_PFLASH];
1486 1487 typedef struct pflash_t pflash_t;
1487 1488  
1488   -pflash_t *pflash_register (target_ulong base, ram_addr_t off,
  1489 +pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1489 1490 BlockDriverState *bs,
1490   - target_ulong sector_len, int nb_blocs, int width,
  1491 + uint32_t sector_len, int nb_blocs, int width,
1491 1492 uint16_t id0, uint16_t id1,
1492 1493 uint16_t id2, uint16_t id3);
1493 1494  
... ...