Blame view

hw/sun4m.c 10.8 KB
1
2
3
/*
 * QEMU Sun4m System Emulator
 * 
4
 * Copyright (c) 2003-2005 Fabrice Bellard
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

#define KERNEL_LOAD_ADDR     0x00004000
bellard authored
27
#define CMDLINE_ADDR         0x007ff000
bellard authored
28
#define INITRD_LOAD_ADDR     0x00800000
bellard authored
29
#define PROM_SIZE_MAX        (256 * 1024)
bellard authored
30
#define PROM_ADDR	     0xffd00000
bellard authored
31
32
#define PROM_FILENAMEB	     "proll.bin"
#define PROM_FILENAMEE	     "proll.elf"
bellard authored
33
#define PHYS_JJ_EEPROM	0x71200000	/* m48t08 */
34
35
#define PHYS_JJ_IDPROM_OFF	0x1FD8
#define PHYS_JJ_EEPROM_SIZE	0x2000
bellard authored
36
37
38
// IRQs are not PIL ones, but master interrupt controller register
// bits
#define PHYS_JJ_IOMMU	0x10000000	/* I/O MMU */
bellard authored
39
#define PHYS_JJ_TCX_FB	0x50000000	/* TCX frame buffer */
bellard authored
40
#define PHYS_JJ_SLAVIO	0x70000000	/* Slavio base */
bellard authored
41
42
43
#define PHYS_JJ_ESPDMA  0x78400000      /* ESP DMA controller */
#define PHYS_JJ_ESP     0x78800000      /* ESP SCSI */
#define PHYS_JJ_ESP_IRQ    18
bellard authored
44
45
46
47
48
49
50
51
#define PHYS_JJ_LEDMA   0x78400010      /* Lance DMA controller */
#define PHYS_JJ_LE      0x78C00000      /* Lance ethernet */
#define PHYS_JJ_LE_IRQ     16
#define PHYS_JJ_CLOCK	0x71D00000      /* Per-CPU timer/counter, L14 */
#define PHYS_JJ_CLOCK_IRQ  7
#define PHYS_JJ_CLOCK1	0x71D10000      /* System timer/counter, L10 */
#define PHYS_JJ_CLOCK1_IRQ 19
#define PHYS_JJ_INTR0	0x71E00000	/* Per-CPU interrupt control registers */
bellard authored
52
#define PHYS_JJ_INTR_G	0x71E10000	/* Master interrupt control registers */
bellard authored
53
54
55
56
57
58
#define PHYS_JJ_MS_KBD	0x71000000	/* Mouse and keyboard */
#define PHYS_JJ_MS_KBD_IRQ    14
#define PHYS_JJ_SER	0x71100000	/* Serial */
#define PHYS_JJ_SER_IRQ    15
#define PHYS_JJ_FDC	0x71400000	/* Floppy */
#define PHYS_JJ_FLOPPY_IRQ 22
bellard authored
59
#define PHYS_JJ_ME_IRQ 30		/* Module error, power fail */
60
#define MAX_CPUS 16
61
62
63
64
65
66
67
68

/* TSC handling */

uint64_t cpu_get_tsc()
{
    return qemu_get_clock(vm_clock);
}
bellard authored
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
int DMA_get_channel_mode (int nchan)
{
    return 0;
}
int DMA_read_memory (int nchan, void *buf, int pos, int size)
{
    return 0;
}
int DMA_write_memory (int nchan, void *buf, int pos, int size)
{
    return 0;
}
void DMA_hold_DREQ (int nchan) {}
void DMA_release_DREQ (int nchan) {}
void DMA_schedule(int nchan) {}
void DMA_run (void) {}
void DMA_init (int high_page_enable) {}
void DMA_register_channel (int nchan,
                           DMA_transfer_handler transfer_handler,
                           void *opaque)
{
}
92
static void nvram_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value)
bellard authored
93
{
94
95
    m48t59_write(nvram, addr++, (value >> 8) & 0xff);
    m48t59_write(nvram, addr++, value & 0xff);
bellard authored
96
97
}
98
static void nvram_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value)
bellard authored
99
{
100
101
102
103
    m48t59_write(nvram, addr++, value >> 24);
    m48t59_write(nvram, addr++, (value >> 16) & 0xff);
    m48t59_write(nvram, addr++, (value >> 8) & 0xff);
    m48t59_write(nvram, addr++, value & 0xff);
bellard authored
104
105
}
106
static void nvram_set_string (m48t59_t *nvram, uint32_t addr,
bellard authored
107
108
109
110
111
                       const unsigned char *str, uint32_t max)
{
    unsigned int i;

    for (i = 0; i < max && str[i] != '\0'; i++) {
112
        m48t59_write(nvram, addr + i, str[i]);
bellard authored
113
    }
114
    m48t59_write(nvram, addr + max - 1, '\0');
bellard authored
115
}
116
117
static m48t59_t *nvram;
118
bellard authored
119
120
extern int nographic;
121
static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
bellard authored
122
123
124
		       int boot_device, uint32_t RAM_size,
		       uint32_t kernel_size,
		       int width, int height, int depth)
bellard authored
125
126
127
128
{
    unsigned char tmp = 0;
    int i, j;
bellard authored
129
130
131
132
    // Try to match PPC NVRAM
    nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);
    nvram_set_lword(nvram,  0x10, 0x00000001); /* structure v1 */
    // NVRAM_size, arch not applicable
133
134
    m48t59_write(nvram, 0x2D, smp_cpus & 0xff);
    m48t59_write(nvram, 0x2E, 0);
135
    m48t59_write(nvram, 0x2F, nographic & 0xff);
bellard authored
136
    nvram_set_lword(nvram,  0x30, RAM_size);
137
    m48t59_write(nvram, 0x34, boot_device & 0xff);
bellard authored
138
139
    nvram_set_lword(nvram,  0x38, KERNEL_LOAD_ADDR);
    nvram_set_lword(nvram,  0x3C, kernel_size);
bellard authored
140
141
    if (cmdline) {
	strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
bellard authored
142
143
	nvram_set_lword(nvram,  0x40, CMDLINE_ADDR);
        nvram_set_lword(nvram,  0x44, strlen(cmdline));
bellard authored
144
    }
bellard authored
145
146
147
148
    // initrd_image, initrd_size passed differently
    nvram_set_word(nvram,   0x54, width);
    nvram_set_word(nvram,   0x56, height);
    nvram_set_word(nvram,   0x58, depth);
bellard authored
149
bellard authored
150
    // Sun4m specific use
bellard authored
151
    i = 0x1fd8;
152
153
    m48t59_write(nvram, i++, 0x01);
    m48t59_write(nvram, i++, 0x80); /* Sun4m OBP */
bellard authored
154
    j = 0;
155
156
157
158
159
160
    m48t59_write(nvram, i++, macaddr[j++]);
    m48t59_write(nvram, i++, macaddr[j++]);
    m48t59_write(nvram, i++, macaddr[j++]);
    m48t59_write(nvram, i++, macaddr[j++]);
    m48t59_write(nvram, i++, macaddr[j++]);
    m48t59_write(nvram, i, macaddr[j]);
bellard authored
161
162
163

    /* Calculate checksum */
    for (i = 0x1fd8; i < 0x1fe7; i++) {
164
	tmp ^= m48t59_read(nvram, i);
bellard authored
165
    }
166
    m48t59_write(nvram, 0x1fe7, tmp);
bellard authored
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
}

static void *slavio_intctl;

void pic_info()
{
    slavio_pic_info(slavio_intctl);
}

void irq_info()
{
    slavio_irq_info(slavio_intctl);
}

void pic_set_irq(int irq, int level)
{
    slavio_pic_set_irq(slavio_intctl, irq, level);
}
186
187
188
189
190
void pic_set_irq_new(void *opaque, int irq, int level)
{
    pic_set_irq(irq, level);
}
191
192
193
194
195
void pic_set_irq_cpu(int irq, int level, unsigned int cpu)
{
    slavio_pic_set_irq_cpu(slavio_intctl, irq, level, cpu);
}
bellard authored
196
197
198
199
200
201
202
static void *iommu;

uint32_t iommu_translate(uint32_t addr)
{
    return iommu_translate_local(iommu, addr);
}
bellard authored
203
204
205
206
207
208
209
static void *slavio_misc;

void qemu_system_powerdown(void)
{
    slavio_set_power_fail(slavio_misc, 1);
}
bellard authored
210
211
212
213
214
215
static void main_cpu_reset(void *opaque)
{
    CPUState *env = opaque;
    cpu_reset(env);
}
216
/* Sun4m hardware initialisation */
bellard authored
217
218
219
220
static void sun4m_init(int ram_size, int vga_ram_size, int boot_device,
                       DisplayState *ds, const char **fd_filename, int snapshot,
                       const char *kernel_filename, const char *kernel_cmdline,
                       const char *initrd_filename)
221
{
222
    CPUState *env, *envs[MAX_CPUS];
223
    char buf[1024];
bellard authored
224
    int ret, linux_boot;
bellard authored
225
    unsigned int i;
bellard authored
226
    long vram_size = 0x100000, prom_offset, initrd_size, kernel_size;
227
228
229

    linux_boot = (kernel_filename != NULL);
230
231
232
233
234
235
236
237
238
    /* init CPUs */
    for(i = 0; i < smp_cpus; i++) {
        env = cpu_init();
        envs[i] = env;
        if (i != 0)
            env->halted = 1;
        register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
        qemu_register_reset(main_cpu_reset, env);
    }
239
240
241
    /* allocate RAM */
    cpu_register_physical_memory(0, ram_size, 0);
bellard authored
242
243
    iommu = iommu_init(PHYS_JJ_IOMMU);
    slavio_intctl = slavio_intctl_init(PHYS_JJ_INTR0, PHYS_JJ_INTR_G);
244
245
246
247
    for(i = 0; i < smp_cpus; i++) {
        slavio_intctl_set_cpu(slavio_intctl, i, envs[i]);
    }
248
    tcx_init(ds, PHYS_JJ_TCX_FB, phys_ram_base + ram_size, ram_size, vram_size, graphic_width, graphic_height);
249
250
251
252
253
254
255
256
257
    if (nd_table[0].vlan) {
        if (nd_table[0].model == NULL
            || strcmp(nd_table[0].model, "lance") == 0) {
            lance_init(&nd_table[0], PHYS_JJ_LE_IRQ, PHYS_JJ_LE, PHYS_JJ_LEDMA);
        } else {
            fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
            exit (1);
        }
    }
258
    nvram = m48t59_init(0, PHYS_JJ_EEPROM, 0, PHYS_JJ_EEPROM_SIZE, 8);
259
260
261
262
    for (i = 0; i < MAX_CPUS; i++) {
        slavio_timer_init(PHYS_JJ_CLOCK + i * TARGET_PAGE_SIZE, PHYS_JJ_CLOCK_IRQ, 0, i);
    }
    slavio_timer_init(PHYS_JJ_CLOCK1, PHYS_JJ_CLOCK1_IRQ, 2, (unsigned int)-1);
bellard authored
263
    slavio_serial_ms_kbd_init(PHYS_JJ_MS_KBD, PHYS_JJ_MS_KBD_IRQ);
264
265
266
    // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
    // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
    slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]);
bellard authored
267
    fdctrl_init(PHYS_JJ_FLOPPY_IRQ, 0, 1, PHYS_JJ_FDC, fd_table);
bellard authored
268
    esp_init(bs_table, PHYS_JJ_ESP_IRQ, PHYS_JJ_ESP, PHYS_JJ_ESPDMA);
bellard authored
269
    slavio_misc = slavio_misc_init(PHYS_JJ_SLAVIO, PHYS_JJ_ME_IRQ);
270
bellard authored
271
    prom_offset = ram_size + vram_size;
bellard authored
272
273
274
    cpu_register_physical_memory(PROM_ADDR, 
                                 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK, 
                                 prom_offset | IO_MEM_ROM);
bellard authored
275
276

    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE);
277
    ret = load_elf(buf, 0, NULL);
bellard authored
278
    if (ret < 0) {
bellard authored
279
	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB);
bellard authored
280
281
282
283
284
285
286
287
	ret = load_image(buf, phys_ram_base + prom_offset);
    }
    if (ret < 0) {
	fprintf(stderr, "qemu: could not load prom '%s'\n", 
		buf);
	exit(1);
    }
bellard authored
288
    kernel_size = 0;
bellard authored
289
    if (linux_boot) {
290
        kernel_size = load_elf(kernel_filename, -0xf0000000, NULL);
bellard authored
291
292
293
294
295
        if (kernel_size < 0)
	    kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
	if (kernel_size < 0)
	    kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
        if (kernel_size < 0) {
296
            fprintf(stderr, "qemu: could not load kernel '%s'\n", 
bellard authored
297
298
                    kernel_filename);
	    exit(1);
299
        }
bellard authored
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320

        /* load initrd */
        initrd_size = 0;
        if (initrd_filename) {
            initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
            if (initrd_size < 0) {
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 
                        initrd_filename);
                exit(1);
            }
        }
        if (initrd_size > 0) {
	    for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
		if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
		    == 0x48647253) { // HdrS
		    stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
		    stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
		    break;
		}
	    }
        }
321
    }
bellard authored
322
    nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth);
323
}
bellard authored
324
325
326
327
328
329

QEMUMachine sun4m_machine = {
    "sun4m",
    "Sun4m platform",
    sun4m_init,
};