gwj / at91sam9263 · Commits

(Ian Jackson)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4132 c046a42c-6fe2-441c-8c8c-71466251a162

When the card is stopped, it should always accept packets, and then
discard them. Thanks to Paul Brook for the explanations.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4128 c046a42c-6fe2-441c-8c8c-71466251a162

(Hervé Poussineau)


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(Glauber Costa)


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(Tristan Gingold)


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(Tristan Gingold)


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(Tristan Gingold)


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(Samuel Thibault)


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(Sebastian Herbszt)


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Previously, the BIOS would probe the CPUs for SMP guests.  This tends to be
very unreliably because of startup timing issues.  By passing the number of
CPUs in the CMOS, the BIOS can detect the number of CPUs much more reliably.

(Anthony Liguori)


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(Hervé Poussineau)


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(Hervé Poussineau)


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(Anthony Liguori)


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(Jean-Christophe PLAGNIOL-VILLARD)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4060 c046a42c-6fe2-441c-8c8c-71466251a162

…_addr_t instead of target_ulong.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4058 c046a42c-6fe2-441c-8c8c-71466251a162

* Clean up the interrupt handling a bit.
* Connect some NOR flash to the test board.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4055 c046a42c-6fe2-441c-8c8c-71466251a162

- whole nvram was erased in some conditions
- fix out of range accesses
- improve reading speed by keeping contents in memory
- rename capacity to chip_size

(Hervé Poussineau)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4051 c046a42c-6fe2-441c-8c8c-71466251a162

This patch fixes endianness issues in the e1000 nic emulation, which
currently only works on little endian hosts with little endian targets.

Byte swapping does not depend on host endianness, so this patch remove
the use of cpu_to_le32 and le32_to_cpu functions. It depends on the path
from the CPU to the device, which is currently and *wrongly* implemented
in Qemu as a byteswap on big endian targets. This patch does the same
as in other devices emulation as all the currently implemented targets
work with this implementation.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4046 c046a42c-6fe2-441c-8c8c-71466251a162

On big endian targets with mmio accesses, the values are not always
swapped, depending on the accessed register. The Linux 8139too module
was able to cope with that, but not the 8139cp one.


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- Byte swapping for internal GT64XXX registers is controlled by the bit
  12 of the Configuration Register and not by the PCI Internal Command
  register.
- The bit 0 of the PCI Internal Command register controls byte swapping
  for PCI access *except for the internal PCI device*, that is when both
  bus and device numbers are 0.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4035 c046a42c-6fe2-441c-8c8c-71466251a162

According to the Intel 82540EM manual, the mmio space is
128k size.
Copied from Xen list and noted by tina..yang@oracle.com

Signed-off-by: Dor Laor <dor.laor@qumranet.com>


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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4029 c046a42c-6fe2-441c-8c8c-71466251a162

Rename omap files to better reflect OMAP1-specific parts.


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* target-cris/helper.c: Update ERP for user-mode simulation aswell.
* hw/etraxfs_timer.c: Support multiple timers.
* hw/etraxfs_ser.c: Multiple ports, the data just goes to stdout.


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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3978 c046a42c-6fe2-441c-8c8c-71466251a162

…es.  Introduce omap L4 abstraction.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3977 c046a42c-6fe2-441c-8c8c-71466251a162