gwj / at91sam9263 · Commits

Commit ff937dbad1cf5ec787ed86c5e6e17503724e6d4c

Authored by j_mayer
1 parent 71c8b8fd

More PowerPC registers definitions. 

Avoid duplicating code and, as a side effect, fix missing bits in MSR.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3191 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 44 additions and 19 deletions
monitor.c
  View file @ff937db
@@ -1406,21 +1406,7 @@ static target_long monitor_get_msr (struct MonitorDef *md, int val) @@ -1406,21 +1406,7 @@ static target_long monitor_get_msr (struct MonitorDef *md, int val)
1406 CPUState *env = mon_get_cpu(); 1406 CPUState *env = mon_get_cpu();
1407 if (!env) 1407 if (!env)
1408 return 0; 1408 return 0;
1409 - return (env->msr[MSR_POW] << MSR_POW) |  
1410 - (env->msr[MSR_ILE] << MSR_ILE) |  
1411 - (env->msr[MSR_EE] << MSR_EE) |  
1412 - (env->msr[MSR_PR] << MSR_PR) |  
1413 - (env->msr[MSR_FP] << MSR_FP) |  
1414 - (env->msr[MSR_ME] << MSR_ME) |  
1415 - (env->msr[MSR_FE0] << MSR_FE0) |  
1416 - (env->msr[MSR_SE] << MSR_SE) |  
1417 - (env->msr[MSR_BE] << MSR_BE) |  
1418 - (env->msr[MSR_FE1] << MSR_FE1) |  
1419 - (env->msr[MSR_IP] << MSR_IP) |  
1420 - (env->msr[MSR_IR] << MSR_IR) |  
1421 - (env->msr[MSR_DR] << MSR_DR) |  
1422 - (env->msr[MSR_RI] << MSR_RI) |  
1423 - (env->msr[MSR_LE] << MSR_LE); 1409 + return do_load_msr(env);
1424 } 1410 }
1425 1411
1426 static target_long monitor_get_xer (struct MonitorDef *md, int val) 1412 static target_long monitor_get_xer (struct MonitorDef *md, int val)
@@ -1428,10 +1414,7 @@ static target_long monitor_get_xer (struct MonitorDef *md, int val) @@ -1428,10 +1414,7 @@ static target_long monitor_get_xer (struct MonitorDef *md, int val)
1428 CPUState *env = mon_get_cpu(); 1414 CPUState *env = mon_get_cpu();
1429 if (!env) 1415 if (!env)
1430 return 0; 1416 return 0;
1431 - return (env->xer[XER_SO] << XER_SO) |  
1432 - (env->xer[XER_OV] << XER_OV) |  
1433 - (env->xer[XER_CA] << XER_CA) |  
1434 - (env->xer[XER_BC] << XER_BC); 1417 + return ppc_load_xer(env);
1435 } 1418 }
1436 1419
1437 static target_long monitor_get_decr (struct MonitorDef *md, int val) 1420 static target_long monitor_get_decr (struct MonitorDef *md, int val)
@@ -1515,6 +1498,7 @@ static MonitorDef monitor_defs[] = { @@ -1515,6 +1498,7 @@ static MonitorDef monitor_defs[] = {
1515 SEG("gs", R_GS) 1498 SEG("gs", R_GS)
1516 { "pc", 0, monitor_get_pc, }, 1499 { "pc", 0, monitor_get_pc, },
1517 #elif defined(TARGET_PPC) 1500 #elif defined(TARGET_PPC)
  1501 + /* General purpose registers */
1518 { "r0", offsetof(CPUState, gpr[0]) }, 1502 { "r0", offsetof(CPUState, gpr[0]) },
1519 { "r1", offsetof(CPUState, gpr[1]) }, 1503 { "r1", offsetof(CPUState, gpr[1]) },
1520 { "r2", offsetof(CPUState, gpr[2]) }, 1504 { "r2", offsetof(CPUState, gpr[2]) },
@@ -1547,15 +1531,56 @@ static MonitorDef monitor_defs[] = { @@ -1547,15 +1531,56 @@ static MonitorDef monitor_defs[] = {
1547 { "r29", offsetof(CPUState, gpr[29]) }, 1531 { "r29", offsetof(CPUState, gpr[29]) },
1548 { "r30", offsetof(CPUState, gpr[30]) }, 1532 { "r30", offsetof(CPUState, gpr[30]) },
1549 { "r31", offsetof(CPUState, gpr[31]) }, 1533 { "r31", offsetof(CPUState, gpr[31]) },
  1534 + /* Floating point registers */
  1535 + { "f0", offsetof(CPUState, fpr[0]) },
  1536 + { "f1", offsetof(CPUState, fpr[1]) },
  1537 + { "f2", offsetof(CPUState, fpr[2]) },
  1538 + { "f3", offsetof(CPUState, fpr[3]) },
  1539 + { "f4", offsetof(CPUState, fpr[4]) },
  1540 + { "f5", offsetof(CPUState, fpr[5]) },
  1541 + { "f6", offsetof(CPUState, fpr[6]) },
  1542 + { "f7", offsetof(CPUState, fpr[7]) },
  1543 + { "f8", offsetof(CPUState, fpr[8]) },
  1544 + { "f9", offsetof(CPUState, fpr[9]) },
  1545 + { "f10", offsetof(CPUState, fpr[10]) },
  1546 + { "f11", offsetof(CPUState, fpr[11]) },
  1547 + { "f12", offsetof(CPUState, fpr[12]) },
  1548 + { "f13", offsetof(CPUState, fpr[13]) },
  1549 + { "f14", offsetof(CPUState, fpr[14]) },
  1550 + { "f15", offsetof(CPUState, fpr[15]) },
  1551 + { "f16", offsetof(CPUState, fpr[16]) },
  1552 + { "f17", offsetof(CPUState, fpr[17]) },
  1553 + { "f18", offsetof(CPUState, fpr[18]) },
  1554 + { "f19", offsetof(CPUState, fpr[19]) },
  1555 + { "f20", offsetof(CPUState, fpr[20]) },
  1556 + { "f21", offsetof(CPUState, fpr[21]) },
  1557 + { "f22", offsetof(CPUState, fpr[22]) },
  1558 + { "f23", offsetof(CPUState, fpr[23]) },
  1559 + { "f24", offsetof(CPUState, fpr[24]) },
  1560 + { "f25", offsetof(CPUState, fpr[25]) },
  1561 + { "f26", offsetof(CPUState, fpr[26]) },
  1562 + { "f27", offsetof(CPUState, fpr[27]) },
  1563 + { "f28", offsetof(CPUState, fpr[28]) },
  1564 + { "f29", offsetof(CPUState, fpr[29]) },
  1565 + { "f30", offsetof(CPUState, fpr[30]) },
  1566 + { "f31", offsetof(CPUState, fpr[31]) },
  1567 + { "fpscr", offsetof(CPUState, fpscr) },
  1568 + /* Next instruction pointer */
1550 { "nip|pc", offsetof(CPUState, nip) }, 1569 { "nip|pc", offsetof(CPUState, nip) },
1551 { "lr", offsetof(CPUState, lr) }, 1570 { "lr", offsetof(CPUState, lr) },
1552 { "ctr", offsetof(CPUState, ctr) }, 1571 { "ctr", offsetof(CPUState, ctr) },
1553 { "decr", 0, &monitor_get_decr, }, 1572 { "decr", 0, &monitor_get_decr, },
1554 { "ccr", 0, &monitor_get_ccr, }, 1573 { "ccr", 0, &monitor_get_ccr, },
  1574 + /* Machine state register */
1555 { "msr", 0, &monitor_get_msr, }, 1575 { "msr", 0, &monitor_get_msr, },
1556 { "xer", 0, &monitor_get_xer, }, 1576 { "xer", 0, &monitor_get_xer, },
1557 { "tbu", 0, &monitor_get_tbu, }, 1577 { "tbu", 0, &monitor_get_tbu, },
1558 { "tbl", 0, &monitor_get_tbl, }, 1578 { "tbl", 0, &monitor_get_tbl, },
  1579 +#if defined(TARGET_PPC64)
  1580 + /* Address space register */
  1581 + { "asr", offsetof(CPUState, asr) },
  1582 +#endif
  1583 + /* Segment registers */
1559 { "sdr1", offsetof(CPUState, sdr1) }, 1584 { "sdr1", offsetof(CPUState, sdr1) },
1560 { "sr0", offsetof(CPUState, sr[0]) }, 1585 { "sr0", offsetof(CPUState, sr[0]) },
1561 { "sr1", offsetof(CPUState, sr[1]) }, 1586 { "sr1", offsetof(CPUState, sr[1]) },