gwj / at91sam9263 · Commits

Commit f2e63a42c9151d17d734ce5a173d81f1598f0565

Authored by j_mayer
1 parent d26bfc9a

Reorganize the CPUPPCState structure to group features. 

Add #ifdef to avoid compiling not relevant resources:
- MMU related stuff for user-mode only targets
- PowerPC 64 only resources for PowerPC 32 targets
- embedded PowerPC extensions for non-ppcemb targets.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3343 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 3 changed files with 69 additions and 19 deletions
target-ppc/cpu.h
  View file @f2e63a4
... ... @@ -495,9 +495,14 @@ struct CPUPPCState {
495 495 int access_type; /* when a memory exception occurs, the access
496 496 type is stored here */
497 497  
498   - /* MMU context */
  498 + /* MMU context - only relevant for full system emulation */
  499 +#if !defined(CONFIG_USER_ONLY)
  500 +#if defined(TARGET_PPC64)
499 501 /* Address space register */
500 502 target_ulong asr;
  503 + /* PowerPC 64 SLB area */
  504 + int slb_nr;
  505 +#endif
501 506 /* segment registers */
502 507 target_ulong sdr1;
503 508 target_ulong sr[16];
... ... @@ -505,17 +510,31 @@ struct CPUPPCState {
505 510 int nb_BATs;
506 511 target_ulong DBAT[2][8];
507 512 target_ulong IBAT[2][8];
  513 + /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
  514 + int nb_tlb; /* Total number of TLB */
  515 + int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
  516 + int nb_ways; /* Number of ways in the TLB set */
  517 + int last_way; /* Last used way used to allocate TLB in a LRU way */
  518 + int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
  519 + int nb_pids; /* Number of available PID registers */
  520 + ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
  521 + /* 403 dedicated access protection registers */
  522 + target_ulong pb[4];
  523 +#endif
508 524  
509 525 /* Other registers */
510 526 /* Special purpose registers */
511 527 target_ulong spr[1024];
  528 + ppc_spr_t spr_cb[1024];
512 529 /* Altivec registers */
513 530 ppc_avr_t avr[32];
514 531 uint32_t vscr;
  532 +#if defined(TARGET_PPCEMB)
515 533 /* SPE registers */
516 534 ppc_gpr_t spe_acc;
517 535 float_status spe_status;
518 536 uint32_t spe_fscr;
  537 +#endif
519 538  
520 539 /* Internal devices resources */
521 540 /* Time base and decrementer */
... ... @@ -523,19 +542,6 @@ struct CPUPPCState {
523 542 /* Device control registers */
524 543 ppc_dcr_t *dcr_env;
525 544  
526   - /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
527   - int nb_tlb; /* Total number of TLB */
528   - int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
529   - int nb_ways; /* Number of ways in the TLB set */
530   - int last_way; /* Last used way used to allocate TLB in a LRU way */
531   - int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
532   - int nb_pids; /* Number of available PID registers */
533   - ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
534   - /* 403 dedicated access protection registers */
535   - target_ulong pb[4];
536   - /* PowerPC 64 SLB area */
537   - int slb_nr;
538   -
539 545 int dcache_line_size;
540 546 int icache_line_size;
541 547  
... ... @@ -570,8 +576,7 @@ struct CPUPPCState {
570 576 /* Those resources are used only during code translation */
571 577 /* Next instruction pointer */
572 578 target_ulong nip;
573   - /* SPR translation callbacks */
574   - ppc_spr_t spr_cb[1024];
  579 +
575 580 /* opcode handlers */
576 581 opc_handler_t *opcodes[0x40];
577 582  
... ...
target-ppc/translate.c
  View file @f2e63a4
... ... @@ -6448,9 +6448,11 @@ void cpu_dump_state (CPUState *env, FILE *f,
6448 6448 if ((i & (RFPL - 1)) == (RFPL - 1))
6449 6449 cpu_fprintf(f, "\n");
6450 6450 }
  6451 +#if !defined(CONFIG_USER_ONLY)
6451 6452 cpu_fprintf(f, "SRR0 " REGX " SRR1 " REGX " " FILL FILL FILL
6452 6453 "SDR1 " REGX "\n",
6453 6454 env->spr[SPR_SRR0], env->spr[SPR_SRR1], env->sdr1);
  6455 +#endif
6454 6456  
6455 6457 #undef RGPL
6456 6458 #undef RFPL
... ...
target-ppc/translate_init.c
  View file @f2e63a4
... ... @@ -533,6 +533,7 @@ static void gen_spr_ne_601 (CPUPPCState *env)
533 533 /* BATs 0-3 */
534 534 static void gen_low_BATs (CPUPPCState *env)
535 535 {
  536 +#if !defined(CONFIG_USER_ONLY)
536 537 spr_register(env, SPR_IBAT0U, "IBAT0U",
537 538 SPR_NOACCESS, SPR_NOACCESS,
538 539 &spr_read_ibat, &spr_write_ibatu,
... ... @@ -598,11 +599,13 @@ static void gen_low_BATs (CPUPPCState *env)
598 599 &spr_read_dbat, &spr_write_dbatl,
599 600 0x00000000);
600 601 env->nb_BATs += 4;
  602 +#endif
601 603 }
602 604  
603 605 /* BATs 4-7 */
604 606 static void gen_high_BATs (CPUPPCState *env)
605 607 {
  608 +#if !defined(CONFIG_USER_ONLY)
606 609 spr_register(env, SPR_IBAT4U, "IBAT4U",
607 610 SPR_NOACCESS, SPR_NOACCESS,
608 611 &spr_read_ibat_h, &spr_write_ibatu_h,
... ... @@ -668,6 +671,7 @@ static void gen_high_BATs (CPUPPCState *env)
668 671 &spr_read_dbat_h, &spr_write_dbatl_h,
669 672 0x00000000);
670 673 env->nb_BATs += 4;
  674 +#endif
671 675 }
672 676  
673 677 /* Generic PowerPC time base */
... ... @@ -694,6 +698,7 @@ static void gen_tbl (CPUPPCState *env)
694 698 /* Softare table search registers */
695 699 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
696 700 {
  701 +#if !defined(CONFIG_USER_ONLY)
697 702 env->nb_tlb = nb_tlbs;
698 703 env->nb_ways = nb_ways;
699 704 env->id_tlbs = 1;
... ... @@ -725,6 +730,7 @@ static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
725 730 SPR_NOACCESS, SPR_NOACCESS,
726 731 &spr_read_generic, &spr_write_generic,
727 732 0x00000000);
  733 +#endif
728 734 }
729 735  
730 736 /* SPR common to MPC755 and G2 */
... ... @@ -1105,6 +1111,7 @@ static void gen_spr_601 (CPUPPCState *env)
1105 1111 &spr_read_generic, &spr_write_generic,
1106 1112 0x00000000);
1107 1113 /* Memory management */
  1114 +#if !defined(CONFIG_USER_ONLY)
1108 1115 spr_register(env, SPR_IBAT0U, "IBAT0U",
1109 1116 SPR_NOACCESS, SPR_NOACCESS,
1110 1117 &spr_read_601_ubat, &spr_write_601_ubatu,
... ... @@ -1138,6 +1145,7 @@ static void gen_spr_601 (CPUPPCState *env)
1138 1145 &spr_read_601_ubat, &spr_write_601_ubatl,
1139 1146 0x00000000);
1140 1147 env->nb_BATs = 4;
  1148 +#endif
1141 1149 }
1142 1150  
1143 1151 static void gen_spr_74xx (CPUPPCState *env)
... ... @@ -1238,6 +1246,7 @@ static void gen_l3_ctrl (CPUPPCState *env)
1238 1246  
1239 1247 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1240 1248 {
  1249 +#if !defined(CONFIG_USER_ONLY)
1241 1250 env->nb_tlb = nb_tlbs;
1242 1251 env->nb_ways = nb_ways;
1243 1252 env->id_tlbs = 1;
... ... @@ -1256,6 +1265,7 @@ static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1256 1265 SPR_NOACCESS, SPR_NOACCESS,
1257 1266 &spr_read_generic, &spr_write_generic,
1258 1267 0x00000000);
  1268 +#endif
1259 1269 }
1260 1270  
1261 1271 /* PowerPC BookE SPR */
... ... @@ -1512,6 +1522,7 @@ static void gen_spr_BookE (CPUPPCState *env)
1512 1522 /* FSL storage control registers */
1513 1523 static void gen_spr_BookE_FSL (CPUPPCState *env)
1514 1524 {
  1525 +#if !defined(CONFIG_USER_ONLY)
1515 1526 /* TLB assist registers */
1516 1527 /* XXX : not implemented */
1517 1528 spr_register(env, SPR_BOOKE_MAS0, "MAS0",
... ... @@ -1605,6 +1616,7 @@ static void gen_spr_BookE_FSL (CPUPPCState *env)
1605 1616 default:
1606 1617 break;
1607 1618 }
  1619 +#endif
1608 1620 }
1609 1621  
1610 1622 /* SPR specific to PowerPC 440 implementation */
... ... @@ -2616,9 +2628,11 @@ static void init_proc_401x2 (CPUPPCState *env)
2616 2628 gen_spr_401x2(env);
2617 2629 gen_spr_compress(env);
2618 2630 /* Memory management */
  2631 +#if !defined(CONFIG_USER_ONLY)
2619 2632 env->nb_tlb = 64;
2620 2633 env->nb_ways = 1;
2621 2634 env->id_tlbs = 0;
  2635 +#endif
2622 2636 init_excp_4xx_softmmu(env);
2623 2637 env->dcache_line_size = 32;
2624 2638 env->icache_line_size = 32;
... ... @@ -2674,9 +2688,11 @@ static void init_proc_IOP480 (CPUPPCState *env)
2674 2688 gen_spr_401x2(env);
2675 2689 gen_spr_compress(env);
2676 2690 /* Memory management */
  2691 +#if !defined(CONFIG_USER_ONLY)
2677 2692 env->nb_tlb = 64;
2678 2693 env->nb_ways = 1;
2679 2694 env->id_tlbs = 0;
  2695 +#endif
2680 2696 init_excp_4xx_softmmu(env);
2681 2697 env->dcache_line_size = 32;
2682 2698 env->icache_line_size = 32;
... ... @@ -2744,9 +2760,11 @@ static void init_proc_403GCX (CPUPPCState *env)
2744 2760 &spr_read_generic, &spr_write_generic,
2745 2761 0x00000000);
2746 2762 /* Memory management */
  2763 +#if !defined(CONFIG_USER_ONLY)
2747 2764 env->nb_tlb = 64;
2748 2765 env->nb_ways = 1;
2749 2766 env->id_tlbs = 0;
  2767 +#endif
2750 2768 init_excp_4xx_softmmu(env);
2751 2769 env->dcache_line_size = 32;
2752 2770 env->icache_line_size = 32;
... ... @@ -2785,9 +2803,11 @@ static void init_proc_405 (CPUPPCState *env)
2785 2803 &spr_read_generic, &spr_write_generic,
2786 2804 0x00000000);
2787 2805 /* Memory management */
  2806 +#if !defined(CONFIG_USER_ONLY)
2788 2807 env->nb_tlb = 64;
2789 2808 env->nb_ways = 1;
2790 2809 env->id_tlbs = 0;
  2810 +#endif
2791 2811 init_excp_4xx_softmmu(env);
2792 2812 env->dcache_line_size = 32;
2793 2813 env->icache_line_size = 32;
... ... @@ -2832,9 +2852,11 @@ static void init_proc_440EP (CPUPPCState *env)
2832 2852 &spr_read_generic, &spr_write_generic,
2833 2853 0x00000000);
2834 2854 /* Memory management */
  2855 +#if !defined(CONFIG_USER_ONLY)
2835 2856 env->nb_tlb = 64;
2836 2857 env->nb_ways = 1;
2837 2858 env->id_tlbs = 0;
  2859 +#endif
2838 2860 init_excp_BookE(env);
2839 2861 env->dcache_line_size = 32;
2840 2862 env->icache_line_size = 32;
... ... @@ -2860,9 +2882,11 @@ static void init_proc_440GP (CPUPPCState *env)
2860 2882 gen_spr_BookE(env);
2861 2883 gen_spr_440(env);
2862 2884 /* Memory management */
  2885 +#if !defined(CONFIG_USER_ONLY)
2863 2886 env->nb_tlb = 64;
2864 2887 env->nb_ways = 1;
2865 2888 env->id_tlbs = 0;
  2889 +#endif
2866 2890 init_excp_BookE(env);
2867 2891 env->dcache_line_size = 32;
2868 2892 env->icache_line_size = 32;
... ... @@ -2889,9 +2913,11 @@ static void init_proc_440x4 (CPUPPCState *env)
2889 2913 gen_spr_BookE(env);
2890 2914 gen_spr_440(env);
2891 2915 /* Memory management */
  2916 +#if !defined(CONFIG_USER_ONLY)
2892 2917 env->nb_tlb = 64;
2893 2918 env->nb_ways = 1;
2894 2919 env->id_tlbs = 0;
  2920 +#endif
2895 2921 init_excp_BookE(env);
2896 2922 env->dcache_line_size = 32;
2897 2923 env->icache_line_size = 32;
... ... @@ -2935,9 +2961,11 @@ static void init_proc_440x5 (CPUPPCState *env)
2935 2961 &spr_read_generic, &spr_write_generic,
2936 2962 0x00000000);
2937 2963 /* Memory management */
  2964 +#if !defined(CONFIG_USER_ONLY)
2938 2965 env->nb_tlb = 64;
2939 2966 env->nb_ways = 1;
2940 2967 env->id_tlbs = 0;
  2968 +#endif
2941 2969 init_excp_BookE(env);
2942 2970 env->dcache_line_size = 32;
2943 2971 env->icache_line_size = 32;
... ... @@ -2987,9 +3015,11 @@ static void init_proc_460 (CPUPPCState *env)
2987 3015 &spr_read_generic, &spr_write_generic,
2988 3016 0x00000000);
2989 3017 /* Memory management */
  3018 +#if !defined(CONFIG_USER_ONLY)
2990 3019 env->nb_tlb = 64;
2991 3020 env->nb_ways = 1;
2992 3021 env->id_tlbs = 0;
  3022 +#endif
2993 3023 init_excp_BookE(env);
2994 3024 env->dcache_line_size = 32;
2995 3025 env->icache_line_size = 32;
... ... @@ -3042,9 +3072,11 @@ static void init_proc_460F (CPUPPCState *env)
3042 3072 &spr_read_generic, &spr_write_generic,
3043 3073 0x00000000);
3044 3074 /* Memory management */
  3075 +#if !defined(CONFIG_USER_ONLY)
3045 3076 env->nb_tlb = 64;
3046 3077 env->nb_ways = 1;
3047 3078 env->id_tlbs = 0;
  3079 +#endif
3048 3080 init_excp_BookE(env);
3049 3081 env->dcache_line_size = 32;
3050 3082 env->icache_line_size = 32;
... ... @@ -3097,9 +3129,11 @@ static void init_proc_e500 (CPUPPCState *env)
3097 3129 gen_spr_BookE(env);
3098 3130 /* Memory management */
3099 3131 gen_spr_BookE_FSL(env);
  3132 +#if !defined(CONFIG_USER_ONLY)
3100 3133 env->nb_tlb = 64;
3101 3134 env->nb_ways = 1;
3102 3135 env->id_tlbs = 0;
  3136 +#endif
3103 3137 init_excp_BookE(env);
3104 3138 env->dcache_line_size = 32;
3105 3139 env->icache_line_size = 32;
... ... @@ -3167,10 +3201,11 @@ static void init_proc_601 (CPUPPCState *env)
3167 3201 &spr_read_generic, &spr_write_generic,
3168 3202 0x00000000);
3169 3203 /* Memory management */
  3204 +#if !defined(CONFIG_USER_ONLY)
3170 3205 env->nb_tlb = 64;
3171 3206 env->nb_ways = 2;
3172 3207 env->id_tlbs = 0;
3173   - env->id_tlbs = 0;
  3208 +#endif
3174 3209 init_excp_601(env);
3175 3210 env->dcache_line_size = 64;
3176 3211 env->icache_line_size = 64;
... ... @@ -4041,7 +4076,9 @@ static void init_proc_970 (CPUPPCState *env)
4041 4076 #if !defined(CONFIG_USER_ONLY)
4042 4077 env->excp_prefix = 0xFFF00000;
4043 4078 #endif
  4079 +#if !defined(CONFIG_USER_ONLY)
4044 4080 env->slb_nr = 32;
  4081 +#endif
4045 4082 init_excp_970(env);
4046 4083 env->dcache_line_size = 128;
4047 4084 env->icache_line_size = 128;
... ... @@ -4112,7 +4149,9 @@ static void init_proc_970FX (CPUPPCState *env)
4112 4149 #if !defined(CONFIG_USER_ONLY)
4113 4150 env->excp_prefix = 0xFFF00000;
4114 4151 #endif
  4152 +#if !defined(CONFIG_USER_ONLY)
4115 4153 env->slb_nr = 32;
  4154 +#endif
4116 4155 init_excp_970(env);
4117 4156 env->dcache_line_size = 128;
4118 4157 env->icache_line_size = 128;
... ... @@ -4183,7 +4222,9 @@ static void init_proc_970GX (CPUPPCState *env)
4183 4222 #if !defined(CONFIG_USER_ONLY)
4184 4223 env->excp_prefix = 0xFFF00000;
4185 4224 #endif
  4225 +#if !defined(CONFIG_USER_ONLY)
4186 4226 env->slb_nr = 32;
  4227 +#endif
4187 4228 init_excp_970(env);
4188 4229 env->dcache_line_size = 128;
4189 4230 env->icache_line_size = 128;
... ... @@ -5729,11 +5770,11 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
5729 5770 env->excp_prefix = 0x00000000;
5730 5771 env->ivor_mask = 0x00000000;
5731 5772 env->ivpr_mask = 0x00000000;
5732   -#endif
5733 5773 /* Default MMU definitions */
5734 5774 env->nb_BATs = 0;
5735 5775 env->nb_tlb = 0;
5736 5776 env->nb_ways = 0;
  5777 +#endif
5737 5778 /* Register SPR common to all PowerPC implementations */
5738 5779 gen_spr_generic(env);
5739 5780 spr_register(env, SPR_PVR, "PVR",
... ... @@ -5743,6 +5784,7 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
5743 5784 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
5744 5785 (*def->init_proc)(env);
5745 5786 /* Allocate TLBs buffer when needed */
  5787 +#if !defined(CONFIG_USER_ONLY)
5746 5788 if (env->nb_tlb != 0) {
5747 5789 int nb_tlb = env->nb_tlb;
5748 5790 if (env->id_tlbs != 0)
... ... @@ -5751,7 +5793,6 @@ static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
5751 5793 /* Pre-compute some useful values */
5752 5794 env->tlb_per_way = env->nb_tlb / env->nb_ways;
5753 5795 }
5754   -#if !defined(CONFIG_USER_ONLY)
5755 5796 if (env->irq_inputs == NULL) {
5756 5797 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
5757 5798 " Attempt Qemu to crash very soon !\n");
... ... @@ -6171,11 +6212,13 @@ int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
6171 6212 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
6172 6213 " MMU model : %s\n",
6173 6214 def->name, def->pvr, def->msr_mask, mmu_model);
  6215 +#if !defined(CONFIG_USER_ONLY)
6174 6216 if (env->tlb != NULL) {
6175 6217 printf(" %d %s TLB in %d ways\n",
6176 6218 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
6177 6219 env->nb_ways);
6178 6220 }
  6221 +#endif
6179 6222 printf(" Exceptions model : %s\n"
6180 6223 " Bus model : %s\n",
6181 6224 excp_model, bus_model);
... ...