gwj / at91sam9263 · Commits

Commit f1aa63203d53945faa708c821c9d4491e5cc8a27

Authored by ths
1 parent 176a4f29

Switch remaining CP0 instructions to TCG or helper functions. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4708 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 5 changed files with 1179 additions and 1236 deletions
target-mips/exec.h
  View file @f1aa632
@@ -48,28 +48,6 @@ register target_ulong T1 asm(AREG2); @@ -48,28 +48,6 @@ register target_ulong T1 asm(AREG2);
48 #include "softmmu_exec.h" 48 #include "softmmu_exec.h"
49 #endif /* !defined(CONFIG_USER_ONLY) */ 49 #endif /* !defined(CONFIG_USER_ONLY) */
50 50
51 -#if defined(TARGET_MIPS64)  
52 -#if TARGET_LONG_BITS > HOST_LONG_BITS  
53 -void do_dsll (void);  
54 -void do_dsll32 (void);  
55 -void do_dsra (void);  
56 -void do_dsra32 (void);  
57 -void do_dsrl (void);  
58 -void do_dsrl32 (void);  
59 -void do_drotr (void);  
60 -void do_drotr32 (void);  
61 -void do_dsllv (void);  
62 -void do_dsrav (void);  
63 -void do_dsrlv (void);  
64 -void do_drotrv (void);  
65 -void do_dclo (void);  
66 -void do_dclz (void);  
67 -#endif  
68 -#endif  
69 -  
70 -#if HOST_LONG_BITS < 64  
71 -void do_div (void);  
72 -#endif  
73 #if TARGET_LONG_BITS > HOST_LONG_BITS 51 #if TARGET_LONG_BITS > HOST_LONG_BITS
74 void do_mult (void); 52 void do_mult (void);
75 void do_multu (void); 53 void do_multu (void);
@@ -92,15 +70,7 @@ void do_mulhiu (void); @@ -92,15 +70,7 @@ void do_mulhiu (void);
92 void do_mulshi (void); 70 void do_mulshi (void);
93 void do_mulshiu (void); 71 void do_mulshiu (void);
94 #endif 72 #endif
95 -#if defined(TARGET_MIPS64)  
96 -void do_ddiv (void);  
97 -#if TARGET_LONG_BITS > HOST_LONG_BITS  
98 -void do_ddivu (void);  
99 -#endif  
100 -#endif  
101 -void do_mfc0_random(void);  
102 -void do_mfc0_count(void);  
103 -void do_mtc0_entryhi(uint32_t in); 73 +
104 void do_mtc0_status_debug(uint32_t old, uint32_t val); 74 void do_mtc0_status_debug(uint32_t old, uint32_t val);
105 void do_mtc0_status_irqraise_debug(void); 75 void do_mtc0_status_irqraise_debug(void);
106 void dump_fpu(CPUState *env); 76 void dump_fpu(CPUState *env);
@@ -133,9 +103,6 @@ void cpu_mips_update_irq (CPUState *env); @@ -133,9 +103,6 @@ void cpu_mips_update_irq (CPUState *env);
133 void cpu_mips_clock_init (CPUState *env); 103 void cpu_mips_clock_init (CPUState *env);
134 void cpu_mips_tlb_flush (CPUState *env, int flush_global); 104 void cpu_mips_tlb_flush (CPUState *env, int flush_global);
135 105
136 -void do_cfc1 (int reg);  
137 -void do_ctc1 (int reg);  
138 -  
139 #define FOP_PROTO(op) \ 106 #define FOP_PROTO(op) \
140 void do_float_ ## op ## _s(void); \ 107 void do_float_ ## op ## _s(void); \
141 void do_float_ ## op ## _d(void); 108 void do_float_ ## op ## _d(void);
target-mips/helper.h
  View file @f1aa632
@@ -12,3 +12,121 @@ DEF_HELPER(void, do_clz, (void)) @@ -12,3 +12,121 @@ DEF_HELPER(void, do_clz, (void))
12 DEF_HELPER(void, do_dclo, (void)) 12 DEF_HELPER(void, do_dclo, (void))
13 DEF_HELPER(void, do_dclz, (void)) 13 DEF_HELPER(void, do_dclz, (void))
14 #endif 14 #endif
  15 +
  16 +/* CP0 helpers */
  17 +#ifndef CONFIG_USER_ONLY
  18 +DEF_HELPER(void, do_mfc0_mvpcontrol, (void))
  19 +DEF_HELPER(void, do_mfc0_mvpconf0, (void))
  20 +DEF_HELPER(void, do_mfc0_mvpconf1, (void))
  21 +DEF_HELPER(void, do_mfc0_random, (void))
  22 +DEF_HELPER(void, do_mfc0_tcstatus, (void))
  23 +DEF_HELPER(void, do_mftc0_tcstatus, (void))
  24 +DEF_HELPER(void, do_mfc0_tcbind, (void))
  25 +DEF_HELPER(void, do_mftc0_tcbind, (void))
  26 +DEF_HELPER(void, do_mfc0_tcrestart, (void))
  27 +DEF_HELPER(void, do_mftc0_tcrestart, (void))
  28 +DEF_HELPER(void, do_mfc0_tchalt, (void))
  29 +DEF_HELPER(void, do_mftc0_tchalt, (void))
  30 +DEF_HELPER(void, do_mfc0_tccontext, (void))
  31 +DEF_HELPER(void, do_mftc0_tccontext, (void))
  32 +DEF_HELPER(void, do_mfc0_tcschedule, (void))
  33 +DEF_HELPER(void, do_mftc0_tcschedule, (void))
  34 +DEF_HELPER(void, do_mfc0_tcschefback, (void))
  35 +DEF_HELPER(void, do_mftc0_tcschefback, (void))
  36 +DEF_HELPER(void, do_mfc0_count, (void))
  37 +DEF_HELPER(void, do_mftc0_entryhi, (void))
  38 +DEF_HELPER(void, do_mftc0_status, (void))
  39 +DEF_HELPER(void, do_mfc0_lladdr, (void))
  40 +DEF_HELPER(void, do_mfc0_watchlo, (uint32_t sel))
  41 +DEF_HELPER(void, do_mfc0_watchhi, (uint32_t sel))
  42 +DEF_HELPER(void, do_mfc0_debug, (void))
  43 +DEF_HELPER(void, do_mftc0_debug, (void))
  44 +#ifdef TARGET_MIPS64
  45 +DEF_HELPER(void, do_dmfc0_tcrestart, (void))
  46 +DEF_HELPER(void, do_dmfc0_tchalt, (void))
  47 +DEF_HELPER(void, do_dmfc0_tccontext, (void))
  48 +DEF_HELPER(void, do_dmfc0_tcschedule, (void))
  49 +DEF_HELPER(void, do_dmfc0_tcschefback, (void))
  50 +DEF_HELPER(void, do_dmfc0_lladdr, (void))
  51 +DEF_HELPER(void, do_dmfc0_watchlo, (uint32_t sel))
  52 +#endif /* TARGET_MIPS64 */
  53 +
  54 +DEF_HELPER(void, do_mtc0_index, (void))
  55 +DEF_HELPER(void, do_mtc0_mvpcontrol, (void))
  56 +DEF_HELPER(void, do_mtc0_vpecontrol, (void))
  57 +DEF_HELPER(void, do_mtc0_vpeconf0, (void))
  58 +DEF_HELPER(void, do_mtc0_vpeconf1, (void))
  59 +DEF_HELPER(void, do_mtc0_yqmask, (void))
  60 +DEF_HELPER(void, do_mtc0_vpeopt, (void))
  61 +DEF_HELPER(void, do_mtc0_entrylo0, (void))
  62 +DEF_HELPER(void, do_mtc0_tcstatus, (void))
  63 +DEF_HELPER(void, do_mttc0_tcstatus, (void))
  64 +DEF_HELPER(void, do_mtc0_tcbind, (void))
  65 +DEF_HELPER(void, do_mttc0_tcbind, (void))
  66 +DEF_HELPER(void, do_mtc0_tcrestart, (void))
  67 +DEF_HELPER(void, do_mttc0_tcrestart, (void))
  68 +DEF_HELPER(void, do_mtc0_tchalt, (void))
  69 +DEF_HELPER(void, do_mttc0_tchalt, (void))
  70 +DEF_HELPER(void, do_mtc0_tccontext, (void))
  71 +DEF_HELPER(void, do_mttc0_tccontext, (void))
  72 +DEF_HELPER(void, do_mtc0_tcschedule, (void))
  73 +DEF_HELPER(void, do_mttc0_tcschedule, (void))
  74 +DEF_HELPER(void, do_mtc0_tcschefback, (void))
  75 +DEF_HELPER(void, do_mttc0_tcschefback, (void))
  76 +DEF_HELPER(void, do_mtc0_entrylo1, (void))
  77 +DEF_HELPER(void, do_mtc0_context, (void))
  78 +DEF_HELPER(void, do_mtc0_pagemask, (void))
  79 +DEF_HELPER(void, do_mtc0_pagegrain, (void))
  80 +DEF_HELPER(void, do_mtc0_wired, (void))
  81 +DEF_HELPER(void, do_mtc0_srsconf0, (void))
  82 +DEF_HELPER(void, do_mtc0_srsconf1, (void))
  83 +DEF_HELPER(void, do_mtc0_srsconf2, (void))
  84 +DEF_HELPER(void, do_mtc0_srsconf3, (void))
  85 +DEF_HELPER(void, do_mtc0_srsconf4, (void))
  86 +DEF_HELPER(void, do_mtc0_hwrena, (void))
  87 +DEF_HELPER(void, do_mtc0_count, (void))
  88 +DEF_HELPER(void, do_mtc0_entryhi, (void))
  89 +DEF_HELPER(void, do_mttc0_entryhi, (void))
  90 +DEF_HELPER(void, do_mtc0_compare, (void))
  91 +DEF_HELPER(void, do_mtc0_status, (void))
  92 +DEF_HELPER(void, do_mttc0_status, (void))
  93 +DEF_HELPER(void, do_mtc0_intctl, (void))
  94 +DEF_HELPER(void, do_mtc0_srsctl, (void))
  95 +DEF_HELPER(void, do_mtc0_cause, (void))
  96 +DEF_HELPER(void, do_mtc0_ebase, (void))
  97 +DEF_HELPER(void, do_mtc0_config0, (void))
  98 +DEF_HELPER(void, do_mtc0_config2, (void))
  99 +DEF_HELPER(void, do_mtc0_watchlo, (uint32_t sel))
  100 +DEF_HELPER(void, do_mtc0_watchhi, (uint32_t sel))
  101 +DEF_HELPER(void, do_mtc0_xcontext, (void))
  102 +DEF_HELPER(void, do_mtc0_framemask, (void))
  103 +DEF_HELPER(void, do_mtc0_debug, (void))
  104 +DEF_HELPER(void, do_mttc0_debug, (void))
  105 +DEF_HELPER(void, do_mtc0_performance0, (void))
  106 +DEF_HELPER(void, do_mtc0_taglo, (void))
  107 +DEF_HELPER(void, do_mtc0_datalo, (void))
  108 +DEF_HELPER(void, do_mtc0_taghi, (void))
  109 +DEF_HELPER(void, do_mtc0_datahi, (void))
  110 +#endif /* !CONFIG_USER_ONLY */
  111 +
  112 +/* MIPS MT functions */
  113 +DEF_HELPER(void, do_mftgpr, (uint32_t sel))
  114 +DEF_HELPER(void, do_mftlo, (uint32_t sel))
  115 +DEF_HELPER(void, do_mfthi, (uint32_t sel))
  116 +DEF_HELPER(void, do_mftacx, (uint32_t sel))
  117 +DEF_HELPER(void, do_mftdsp, (void))
  118 +DEF_HELPER(void, do_mttgpr, (uint32_t sel))
  119 +DEF_HELPER(void, do_mttlo, (uint32_t sel))
  120 +DEF_HELPER(void, do_mtthi, (uint32_t sel))
  121 +DEF_HELPER(void, do_mttacx, (uint32_t sel))
  122 +DEF_HELPER(void, do_mttdsp, (void))
  123 +DEF_HELPER(void, do_dmt, (void))
  124 +DEF_HELPER(void, do_emt, (void))
  125 +DEF_HELPER(void, do_dvpe, (void))
  126 +DEF_HELPER(void, do_evpe, (void))
  127 +DEF_HELPER(void, do_fork, (void))
  128 +DEF_HELPER(void, do_yield, (void))
  129 +
  130 +/* CP1 functions */
  131 +DEF_HELPER(void, do_cfc1, (uint32_t reg))
  132 +DEF_HELPER(void, do_ctc1, (uint32_t reg))
target-mips/op.c
  View file @f1aa632
@@ -460,946 +460,6 @@ void op_dmultu (void) @@ -460,946 +460,6 @@ void op_dmultu (void)
460 } 460 }
461 #endif 461 #endif
462 462
463 -/* CP0 functions */  
464 -void op_mfc0_mvpcontrol (void)  
465 -{  
466 - T0 = env->mvp->CP0_MVPControl;  
467 - FORCE_RET();  
468 -}  
469 -  
470 -void op_mfc0_mvpconf0 (void)  
471 -{  
472 - T0 = env->mvp->CP0_MVPConf0;  
473 - FORCE_RET();  
474 -}  
475 -  
476 -void op_mfc0_mvpconf1 (void)  
477 -{  
478 - T0 = env->mvp->CP0_MVPConf1;  
479 - FORCE_RET();  
480 -}  
481 -  
482 -void op_mfc0_random (void)  
483 -{  
484 - CALL_FROM_TB0(do_mfc0_random);  
485 - FORCE_RET();  
486 -}  
487 -  
488 -void op_mfc0_tcstatus (void)  
489 -{  
490 - T0 = env->CP0_TCStatus[env->current_tc];  
491 - FORCE_RET();  
492 -}  
493 -  
494 -void op_mftc0_tcstatus(void)  
495 -{  
496 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
497 -  
498 - T0 = env->CP0_TCStatus[other_tc];  
499 - FORCE_RET();  
500 -}  
501 -  
502 -void op_mfc0_tcbind (void)  
503 -{  
504 - T0 = env->CP0_TCBind[env->current_tc];  
505 - FORCE_RET();  
506 -}  
507 -  
508 -void op_mftc0_tcbind(void)  
509 -{  
510 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
511 -  
512 - T0 = env->CP0_TCBind[other_tc];  
513 - FORCE_RET();  
514 -}  
515 -  
516 -void op_mfc0_tcrestart (void)  
517 -{  
518 - T0 = env->PC[env->current_tc];  
519 - FORCE_RET();  
520 -}  
521 -  
522 -void op_mftc0_tcrestart(void)  
523 -{  
524 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
525 -  
526 - T0 = env->PC[other_tc];  
527 - FORCE_RET();  
528 -}  
529 -  
530 -void op_mfc0_tchalt (void)  
531 -{  
532 - T0 = env->CP0_TCHalt[env->current_tc];  
533 - FORCE_RET();  
534 -}  
535 -  
536 -void op_mftc0_tchalt(void)  
537 -{  
538 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
539 -  
540 - T0 = env->CP0_TCHalt[other_tc];  
541 - FORCE_RET();  
542 -}  
543 -  
544 -void op_mfc0_tccontext (void)  
545 -{  
546 - T0 = env->CP0_TCContext[env->current_tc];  
547 - FORCE_RET();  
548 -}  
549 -  
550 -void op_mftc0_tccontext(void)  
551 -{  
552 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
553 -  
554 - T0 = env->CP0_TCContext[other_tc];  
555 - FORCE_RET();  
556 -}  
557 -  
558 -void op_mfc0_tcschedule (void)  
559 -{  
560 - T0 = env->CP0_TCSchedule[env->current_tc];  
561 - FORCE_RET();  
562 -}  
563 -  
564 -void op_mftc0_tcschedule(void)  
565 -{  
566 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
567 -  
568 - T0 = env->CP0_TCSchedule[other_tc];  
569 - FORCE_RET();  
570 -}  
571 -  
572 -void op_mfc0_tcschefback (void)  
573 -{  
574 - T0 = env->CP0_TCScheFBack[env->current_tc];  
575 - FORCE_RET();  
576 -}  
577 -  
578 -void op_mftc0_tcschefback(void)  
579 -{  
580 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
581 -  
582 - T0 = env->CP0_TCScheFBack[other_tc];  
583 - FORCE_RET();  
584 -}  
585 -  
586 -void op_mfc0_count (void)  
587 -{  
588 - CALL_FROM_TB0(do_mfc0_count);  
589 - FORCE_RET();  
590 -}  
591 -  
592 -void op_mftc0_entryhi(void)  
593 -{  
594 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
595 -  
596 - T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);  
597 - FORCE_RET();  
598 -}  
599 -  
600 -void op_mftc0_status(void)  
601 -{  
602 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
603 - uint32_t tcstatus = env->CP0_TCStatus[other_tc];  
604 -  
605 - T0 = env->CP0_Status & ~0xf1000018;  
606 - T0 |= tcstatus & (0xf << CP0TCSt_TCU0);  
607 - T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);  
608 - T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);  
609 - FORCE_RET();  
610 -}  
611 -  
612 -void op_mfc0_lladdr (void)  
613 -{  
614 - T0 = (int32_t)env->CP0_LLAddr >> 4;  
615 - FORCE_RET();  
616 -}  
617 -  
618 -void op_mfc0_watchlo (void)  
619 -{  
620 - T0 = (int32_t)env->CP0_WatchLo[PARAM1];  
621 - FORCE_RET();  
622 -}  
623 -  
624 -void op_mfc0_watchhi (void)  
625 -{  
626 - T0 = env->CP0_WatchHi[PARAM1];  
627 - FORCE_RET();  
628 -}  
629 -  
630 -void op_mfc0_debug (void)  
631 -{  
632 - T0 = env->CP0_Debug;  
633 - if (env->hflags & MIPS_HFLAG_DM)  
634 - T0 |= 1 << CP0DB_DM;  
635 - FORCE_RET();  
636 -}  
637 -  
638 -void op_mftc0_debug(void)  
639 -{  
640 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
641 -  
642 - /* XXX: Might be wrong, check with EJTAG spec. */  
643 - T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |  
644 - (env->CP0_Debug_tcstatus[other_tc] &  
645 - ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));  
646 - FORCE_RET();  
647 -}  
648 -  
649 -void op_mtc0_index (void)  
650 -{  
651 - int num = 1;  
652 - unsigned int tmp = env->tlb->nb_tlb;  
653 -  
654 - do {  
655 - tmp >>= 1;  
656 - num <<= 1;  
657 - } while (tmp);  
658 - env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (num - 1));  
659 - FORCE_RET();  
660 -}  
661 -  
662 -void op_mtc0_mvpcontrol (void)  
663 -{  
664 - uint32_t mask = 0;  
665 - uint32_t newval;  
666 -  
667 - if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))  
668 - mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |  
669 - (1 << CP0MVPCo_EVP);  
670 - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))  
671 - mask |= (1 << CP0MVPCo_STLB);  
672 - newval = (env->mvp->CP0_MVPControl & ~mask) | (T0 & mask);  
673 -  
674 - // TODO: Enable/disable shared TLB, enable/disable VPEs.  
675 -  
676 - env->mvp->CP0_MVPControl = newval;  
677 - FORCE_RET();  
678 -}  
679 -  
680 -void op_mtc0_vpecontrol (void)  
681 -{  
682 - uint32_t mask;  
683 - uint32_t newval;  
684 -  
685 - mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |  
686 - (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);  
687 - newval = (env->CP0_VPEControl & ~mask) | (T0 & mask);  
688 -  
689 - /* Yield scheduler intercept not implemented. */  
690 - /* Gating storage scheduler intercept not implemented. */  
691 -  
692 - // TODO: Enable/disable TCs.  
693 -  
694 - env->CP0_VPEControl = newval;  
695 - FORCE_RET();  
696 -}  
697 -  
698 -void op_mtc0_vpeconf0 (void)  
699 -{  
700 - uint32_t mask = 0;  
701 - uint32_t newval;  
702 -  
703 - if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {  
704 - if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))  
705 - mask |= (0xff << CP0VPEC0_XTC);  
706 - mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);  
707 - }  
708 - newval = (env->CP0_VPEConf0 & ~mask) | (T0 & mask);  
709 -  
710 - // TODO: TC exclusive handling due to ERL/EXL.  
711 -  
712 - env->CP0_VPEConf0 = newval;  
713 - FORCE_RET();  
714 -}  
715 -  
716 -void op_mtc0_vpeconf1 (void)  
717 -{  
718 - uint32_t mask = 0;  
719 - uint32_t newval;  
720 -  
721 - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))  
722 - mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |  
723 - (0xff << CP0VPEC1_NCP1);  
724 - newval = (env->CP0_VPEConf1 & ~mask) | (T0 & mask);  
725 -  
726 - /* UDI not implemented. */  
727 - /* CP2 not implemented. */  
728 -  
729 - // TODO: Handle FPU (CP1) binding.  
730 -  
731 - env->CP0_VPEConf1 = newval;  
732 - FORCE_RET();  
733 -}  
734 -  
735 -void op_mtc0_yqmask (void)  
736 -{  
737 - /* Yield qualifier inputs not implemented. */  
738 - env->CP0_YQMask = 0x00000000;  
739 - FORCE_RET();  
740 -}  
741 -  
742 -void op_mtc0_vpeschedule (void)  
743 -{  
744 - env->CP0_VPESchedule = T0;  
745 - FORCE_RET();  
746 -}  
747 -  
748 -void op_mtc0_vpeschefback (void)  
749 -{  
750 - env->CP0_VPEScheFBack = T0;  
751 - FORCE_RET();  
752 -}  
753 -  
754 -void op_mtc0_vpeopt (void)  
755 -{  
756 - env->CP0_VPEOpt = T0 & 0x0000ffff;  
757 - FORCE_RET();  
758 -}  
759 -  
760 -void op_mtc0_entrylo0 (void)  
761 -{  
762 - /* Large physaddr (PABITS) not implemented */  
763 - /* 1k pages not implemented */  
764 - env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;  
765 - FORCE_RET();  
766 -}  
767 -  
768 -void op_mtc0_tcstatus (void)  
769 -{  
770 - uint32_t mask = env->CP0_TCStatus_rw_bitmask;  
771 - uint32_t newval;  
772 -  
773 - newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (T0 & mask);  
774 -  
775 - // TODO: Sync with CP0_Status.  
776 -  
777 - env->CP0_TCStatus[env->current_tc] = newval;  
778 - FORCE_RET();  
779 -}  
780 -  
781 -void op_mttc0_tcstatus (void)  
782 -{  
783 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
784 -  
785 - // TODO: Sync with CP0_Status.  
786 -  
787 - env->CP0_TCStatus[other_tc] = T0;  
788 - FORCE_RET();  
789 -}  
790 -  
791 -void op_mtc0_tcbind (void)  
792 -{  
793 - uint32_t mask = (1 << CP0TCBd_TBE);  
794 - uint32_t newval;  
795 -  
796 - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))  
797 - mask |= (1 << CP0TCBd_CurVPE);  
798 - newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (T0 & mask);  
799 - env->CP0_TCBind[env->current_tc] = newval;  
800 - FORCE_RET();  
801 -}  
802 -  
803 -void op_mttc0_tcbind (void)  
804 -{  
805 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
806 - uint32_t mask = (1 << CP0TCBd_TBE);  
807 - uint32_t newval;  
808 -  
809 - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))  
810 - mask |= (1 << CP0TCBd_CurVPE);  
811 - newval = (env->CP0_TCBind[other_tc] & ~mask) | (T0 & mask);  
812 - env->CP0_TCBind[other_tc] = newval;  
813 - FORCE_RET();  
814 -}  
815 -  
816 -void op_mtc0_tcrestart (void)  
817 -{  
818 - env->PC[env->current_tc] = T0;  
819 - env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS);  
820 - env->CP0_LLAddr = 0ULL;  
821 - /* MIPS16 not implemented. */  
822 - FORCE_RET();  
823 -}  
824 -  
825 -void op_mttc0_tcrestart (void)  
826 -{  
827 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
828 -  
829 - env->PC[other_tc] = T0;  
830 - env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS);  
831 - env->CP0_LLAddr = 0ULL;  
832 - /* MIPS16 not implemented. */  
833 - FORCE_RET();  
834 -}  
835 -  
836 -void op_mtc0_tchalt (void)  
837 -{  
838 - env->CP0_TCHalt[env->current_tc] = T0 & 0x1;  
839 -  
840 - // TODO: Halt TC / Restart (if allocated+active) TC.  
841 -  
842 - FORCE_RET();  
843 -}  
844 -  
845 -void op_mttc0_tchalt (void)  
846 -{  
847 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
848 -  
849 - // TODO: Halt TC / Restart (if allocated+active) TC.  
850 -  
851 - env->CP0_TCHalt[other_tc] = T0;  
852 - FORCE_RET();  
853 -}  
854 -  
855 -void op_mtc0_tccontext (void)  
856 -{  
857 - env->CP0_TCContext[env->current_tc] = T0;  
858 - FORCE_RET();  
859 -}  
860 -  
861 -void op_mttc0_tccontext (void)  
862 -{  
863 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
864 -  
865 - env->CP0_TCContext[other_tc] = T0;  
866 - FORCE_RET();  
867 -}  
868 -  
869 -void op_mtc0_tcschedule (void)  
870 -{  
871 - env->CP0_TCSchedule[env->current_tc] = T0;  
872 - FORCE_RET();  
873 -}  
874 -  
875 -void op_mttc0_tcschedule (void)  
876 -{  
877 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
878 -  
879 - env->CP0_TCSchedule[other_tc] = T0;  
880 - FORCE_RET();  
881 -}  
882 -  
883 -void op_mtc0_tcschefback (void)  
884 -{  
885 - env->CP0_TCScheFBack[env->current_tc] = T0;  
886 - FORCE_RET();  
887 -}  
888 -  
889 -void op_mttc0_tcschefback (void)  
890 -{  
891 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
892 -  
893 - env->CP0_TCScheFBack[other_tc] = T0;  
894 - FORCE_RET();  
895 -}  
896 -  
897 -void op_mtc0_entrylo1 (void)  
898 -{  
899 - /* Large physaddr (PABITS) not implemented */  
900 - /* 1k pages not implemented */  
901 - env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;  
902 - FORCE_RET();  
903 -}  
904 -  
905 -void op_mtc0_context (void)  
906 -{  
907 - env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);  
908 - FORCE_RET();  
909 -}  
910 -  
911 -void op_mtc0_pagemask (void)  
912 -{  
913 - /* 1k pages not implemented */  
914 - env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));  
915 - FORCE_RET();  
916 -}  
917 -  
918 -void op_mtc0_pagegrain (void)  
919 -{  
920 - /* SmartMIPS not implemented */  
921 - /* Large physaddr (PABITS) not implemented */  
922 - /* 1k pages not implemented */  
923 - env->CP0_PageGrain = 0;  
924 - FORCE_RET();  
925 -}  
926 -  
927 -void op_mtc0_wired (void)  
928 -{  
929 - env->CP0_Wired = T0 % env->tlb->nb_tlb;  
930 - FORCE_RET();  
931 -}  
932 -  
933 -void op_mtc0_srsconf0 (void)  
934 -{  
935 - env->CP0_SRSConf0 |= T0 & env->CP0_SRSConf0_rw_bitmask;  
936 - FORCE_RET();  
937 -}  
938 -  
939 -void op_mtc0_srsconf1 (void)  
940 -{  
941 - env->CP0_SRSConf1 |= T0 & env->CP0_SRSConf1_rw_bitmask;  
942 - FORCE_RET();  
943 -}  
944 -  
945 -void op_mtc0_srsconf2 (void)  
946 -{  
947 - env->CP0_SRSConf2 |= T0 & env->CP0_SRSConf2_rw_bitmask;  
948 - FORCE_RET();  
949 -}  
950 -  
951 -void op_mtc0_srsconf3 (void)  
952 -{  
953 - env->CP0_SRSConf3 |= T0 & env->CP0_SRSConf3_rw_bitmask;  
954 - FORCE_RET();  
955 -}  
956 -  
957 -void op_mtc0_srsconf4 (void)  
958 -{  
959 - env->CP0_SRSConf4 |= T0 & env->CP0_SRSConf4_rw_bitmask;  
960 - FORCE_RET();  
961 -}  
962 -  
963 -void op_mtc0_hwrena (void)  
964 -{  
965 - env->CP0_HWREna = T0 & 0x0000000F;  
966 - FORCE_RET();  
967 -}  
968 -  
969 -void op_mtc0_count (void)  
970 -{  
971 - CALL_FROM_TB2(cpu_mips_store_count, env, T0);  
972 - FORCE_RET();  
973 -}  
974 -  
975 -void op_mtc0_entryhi (void)  
976 -{  
977 - target_ulong old, val;  
978 -  
979 - /* 1k pages not implemented */  
980 - val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF);  
981 -#if defined(TARGET_MIPS64)  
982 - val &= env->SEGMask;  
983 -#endif  
984 - old = env->CP0_EntryHi;  
985 - env->CP0_EntryHi = val;  
986 - if (env->CP0_Config3 & (1 << CP0C3_MT)) {  
987 - uint32_t tcst = env->CP0_TCStatus[env->current_tc] & ~0xff;  
988 - env->CP0_TCStatus[env->current_tc] = tcst | (val & 0xff);  
989 - }  
990 - /* If the ASID changes, flush qemu's TLB. */  
991 - if ((old & 0xFF) != (val & 0xFF))  
992 - CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);  
993 - FORCE_RET();  
994 -}  
995 -  
996 -void op_mttc0_entryhi(void)  
997 -{  
998 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
999 -  
1000 - env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (T0 & ~0xff);  
1001 - env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (T0 & 0xff);  
1002 - FORCE_RET();  
1003 -}  
1004 -  
1005 -void op_mtc0_compare (void)  
1006 -{  
1007 - CALL_FROM_TB2(cpu_mips_store_compare, env, T0);  
1008 - FORCE_RET();  
1009 -}  
1010 -  
1011 -void op_mtc0_status (void)  
1012 -{  
1013 - uint32_t val, old;  
1014 - uint32_t mask = env->CP0_Status_rw_bitmask;  
1015 -  
1016 - val = T0 & mask;  
1017 - old = env->CP0_Status;  
1018 - env->CP0_Status = (env->CP0_Status & ~mask) | val;  
1019 - CALL_FROM_TB1(compute_hflags, env);  
1020 - if (loglevel & CPU_LOG_EXEC)  
1021 - CALL_FROM_TB2(do_mtc0_status_debug, old, val);  
1022 - CALL_FROM_TB1(cpu_mips_update_irq, env);  
1023 - FORCE_RET();  
1024 -}  
1025 -  
1026 -void op_mttc0_status(void)  
1027 -{  
1028 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
1029 - uint32_t tcstatus = env->CP0_TCStatus[other_tc];  
1030 -  
1031 - env->CP0_Status = T0 & ~0xf1000018;  
1032 - tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (T0 & (0xf << CP0St_CU0));  
1033 - tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((T0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));  
1034 - tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((T0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));  
1035 - env->CP0_TCStatus[other_tc] = tcstatus;  
1036 - FORCE_RET();  
1037 -}  
1038 -  
1039 -void op_mtc0_intctl (void)  
1040 -{  
1041 - /* vectored interrupts not implemented, no performance counters. */  
1042 - env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (T0 & 0x000002e0);  
1043 - FORCE_RET();  
1044 -}  
1045 -  
1046 -void op_mtc0_srsctl (void)  
1047 -{  
1048 - uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);  
1049 - env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (T0 & mask);  
1050 - FORCE_RET();  
1051 -}  
1052 -  
1053 -void op_mtc0_srsmap (void)  
1054 -{  
1055 - env->CP0_SRSMap = T0;  
1056 - FORCE_RET();  
1057 -}  
1058 -  
1059 -void op_mtc0_cause (void)  
1060 -{  
1061 - uint32_t mask = 0x00C00300;  
1062 - uint32_t old = env->CP0_Cause;  
1063 -  
1064 - if (env->insn_flags & ISA_MIPS32R2)  
1065 - mask |= 1 << CP0Ca_DC;  
1066 -  
1067 - env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);  
1068 -  
1069 - if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {  
1070 - if (env->CP0_Cause & (1 << CP0Ca_DC))  
1071 - CALL_FROM_TB1(cpu_mips_stop_count, env);  
1072 - else  
1073 - CALL_FROM_TB1(cpu_mips_start_count, env);  
1074 - }  
1075 -  
1076 - /* Handle the software interrupt as an hardware one, as they  
1077 - are very similar */  
1078 - if (T0 & CP0Ca_IP_mask) {  
1079 - CALL_FROM_TB1(cpu_mips_update_irq, env);  
1080 - }  
1081 - FORCE_RET();  
1082 -}  
1083 -  
1084 -void op_mtc0_epc (void)  
1085 -{  
1086 - env->CP0_EPC = T0;  
1087 - FORCE_RET();  
1088 -}  
1089 -  
1090 -void op_mtc0_ebase (void)  
1091 -{  
1092 - /* vectored interrupts not implemented */  
1093 - /* Multi-CPU not implemented */  
1094 - env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);  
1095 - FORCE_RET();  
1096 -}  
1097 -  
1098 -void op_mtc0_config0 (void)  
1099 -{  
1100 - env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007);  
1101 - FORCE_RET();  
1102 -}  
1103 -  
1104 -void op_mtc0_config2 (void)  
1105 -{  
1106 - /* tertiary/secondary caches not implemented */  
1107 - env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);  
1108 - FORCE_RET();  
1109 -}  
1110 -  
1111 -void op_mtc0_watchlo (void)  
1112 -{  
1113 - /* Watch exceptions for instructions, data loads, data stores  
1114 - not implemented. */  
1115 - env->CP0_WatchLo[PARAM1] = (T0 & ~0x7);  
1116 - FORCE_RET();  
1117 -}  
1118 -  
1119 -void op_mtc0_watchhi (void)  
1120 -{  
1121 - env->CP0_WatchHi[PARAM1] = (T0 & 0x40FF0FF8);  
1122 - env->CP0_WatchHi[PARAM1] &= ~(env->CP0_WatchHi[PARAM1] & T0 & 0x7);  
1123 - FORCE_RET();  
1124 -}  
1125 -  
1126 -void op_mtc0_xcontext (void)  
1127 -{  
1128 - target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;  
1129 - env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask);  
1130 - FORCE_RET();  
1131 -}  
1132 -  
1133 -void op_mtc0_framemask (void)  
1134 -{  
1135 - env->CP0_Framemask = T0; /* XXX */  
1136 - FORCE_RET();  
1137 -}  
1138 -  
1139 -void op_mtc0_debug (void)  
1140 -{  
1141 - env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);  
1142 - if (T0 & (1 << CP0DB_DM))  
1143 - env->hflags |= MIPS_HFLAG_DM;  
1144 - else  
1145 - env->hflags &= ~MIPS_HFLAG_DM;  
1146 - FORCE_RET();  
1147 -}  
1148 -  
1149 -void op_mttc0_debug(void)  
1150 -{  
1151 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
1152 -  
1153 - /* XXX: Might be wrong, check with EJTAG spec. */  
1154 - env->CP0_Debug_tcstatus[other_tc] = T0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));  
1155 - env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |  
1156 - (T0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));  
1157 - FORCE_RET();  
1158 -}  
1159 -  
1160 -void op_mtc0_depc (void)  
1161 -{  
1162 - env->CP0_DEPC = T0;  
1163 - FORCE_RET();  
1164 -}  
1165 -  
1166 -void op_mtc0_performance0 (void)  
1167 -{  
1168 - env->CP0_Performance0 = T0 & 0x000007ff;  
1169 - FORCE_RET();  
1170 -}  
1171 -  
1172 -void op_mtc0_taglo (void)  
1173 -{  
1174 - env->CP0_TagLo = T0 & 0xFFFFFCF6;  
1175 - FORCE_RET();  
1176 -}  
1177 -  
1178 -void op_mtc0_datalo (void)  
1179 -{  
1180 - env->CP0_DataLo = T0; /* XXX */  
1181 - FORCE_RET();  
1182 -}  
1183 -  
1184 -void op_mtc0_taghi (void)  
1185 -{  
1186 - env->CP0_TagHi = T0; /* XXX */  
1187 - FORCE_RET();  
1188 -}  
1189 -  
1190 -void op_mtc0_datahi (void)  
1191 -{  
1192 - env->CP0_DataHi = T0; /* XXX */  
1193 - FORCE_RET();  
1194 -}  
1195 -  
1196 -void op_mtc0_errorepc (void)  
1197 -{  
1198 - env->CP0_ErrorEPC = T0;  
1199 - FORCE_RET();  
1200 -}  
1201 -  
1202 -void op_mtc0_desave (void)  
1203 -{  
1204 - env->CP0_DESAVE = T0;  
1205 - FORCE_RET();  
1206 -}  
1207 -  
1208 -#if defined(TARGET_MIPS64)  
1209 -void op_dmfc0_tcrestart (void)  
1210 -{  
1211 - T0 = env->PC[env->current_tc];  
1212 - FORCE_RET();  
1213 -}  
1214 -  
1215 -void op_dmfc0_tchalt (void)  
1216 -{  
1217 - T0 = env->CP0_TCHalt[env->current_tc];  
1218 - FORCE_RET();  
1219 -}  
1220 -  
1221 -void op_dmfc0_tccontext (void)  
1222 -{  
1223 - T0 = env->CP0_TCContext[env->current_tc];  
1224 - FORCE_RET();  
1225 -}  
1226 -  
1227 -void op_dmfc0_tcschedule (void)  
1228 -{  
1229 - T0 = env->CP0_TCSchedule[env->current_tc];  
1230 - FORCE_RET();  
1231 -}  
1232 -  
1233 -void op_dmfc0_tcschefback (void)  
1234 -{  
1235 - T0 = env->CP0_TCScheFBack[env->current_tc];  
1236 - FORCE_RET();  
1237 -}  
1238 -  
1239 -void op_dmfc0_lladdr (void)  
1240 -{  
1241 - T0 = env->CP0_LLAddr >> 4;  
1242 - FORCE_RET();  
1243 -}  
1244 -  
1245 -void op_dmfc0_watchlo (void)  
1246 -{  
1247 - T0 = env->CP0_WatchLo[PARAM1];  
1248 - FORCE_RET();  
1249 -}  
1250 -#endif /* TARGET_MIPS64 */  
1251 -  
1252 -/* MIPS MT functions */  
1253 -void op_mftgpr(void)  
1254 -{  
1255 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
1256 -  
1257 - T0 = env->gpr[other_tc][PARAM1];  
1258 - FORCE_RET();  
1259 -}  
1260 -  
1261 -void op_mftlo(void)  
1262 -{  
1263 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
1264 -  
1265 - T0 = env->LO[other_tc][PARAM1];  
1266 - FORCE_RET();  
1267 -}  
1268 -  
1269 -void op_mfthi(void)  
1270 -{  
1271 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
1272 -  
1273 - T0 = env->HI[other_tc][PARAM1];  
1274 - FORCE_RET();  
1275 -}  
1276 -  
1277 -void op_mftacx(void)  
1278 -{  
1279 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
1280 -  
1281 - T0 = env->ACX[other_tc][PARAM1];  
1282 - FORCE_RET();  
1283 -}  
1284 -  
1285 -void op_mftdsp(void)  
1286 -{  
1287 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
1288 -  
1289 - T0 = env->DSPControl[other_tc];  
1290 - FORCE_RET();  
1291 -}  
1292 -  
1293 -void op_mttgpr(void)  
1294 -{  
1295 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
1296 -  
1297 - T0 = env->gpr[other_tc][PARAM1];  
1298 - FORCE_RET();  
1299 -}  
1300 -  
1301 -void op_mttlo(void)  
1302 -{  
1303 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
1304 -  
1305 - T0 = env->LO[other_tc][PARAM1];  
1306 - FORCE_RET();  
1307 -}  
1308 -  
1309 -void op_mtthi(void)  
1310 -{  
1311 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
1312 -  
1313 - T0 = env->HI[other_tc][PARAM1];  
1314 - FORCE_RET();  
1315 -}  
1316 -  
1317 -void op_mttacx(void)  
1318 -{  
1319 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
1320 -  
1321 - T0 = env->ACX[other_tc][PARAM1];  
1322 - FORCE_RET();  
1323 -}  
1324 -  
1325 -void op_mttdsp(void)  
1326 -{  
1327 - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);  
1328 -  
1329 - T0 = env->DSPControl[other_tc];  
1330 - FORCE_RET();  
1331 -}  
1332 -  
1333 -  
1334 -void op_dmt(void)  
1335 -{  
1336 - // TODO  
1337 - T0 = 0;  
1338 - // rt = T0  
1339 - FORCE_RET();  
1340 -}  
1341 -  
1342 -void op_emt(void)  
1343 -{  
1344 - // TODO  
1345 - T0 = 0;  
1346 - // rt = T0  
1347 - FORCE_RET();  
1348 -}  
1349 -  
1350 -void op_dvpe(void)  
1351 -{  
1352 - // TODO  
1353 - T0 = 0;  
1354 - // rt = T0  
1355 - FORCE_RET();  
1356 -}  
1357 -  
1358 -void op_evpe(void)  
1359 -{  
1360 - // TODO  
1361 - T0 = 0;  
1362 - // rt = T0  
1363 - FORCE_RET();  
1364 -}  
1365 -  
1366 -void op_fork(void)  
1367 -{  
1368 - // T0 = rt, T1 = rs  
1369 - T0 = 0;  
1370 - // TODO: store to TC register  
1371 - FORCE_RET();  
1372 -}  
1373 -  
1374 -void op_yield(void)  
1375 -{  
1376 - if (T0 < 0) {  
1377 - /* No scheduling policy implemented. */  
1378 - if (T0 != -2) {  
1379 - if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&  
1380 - env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) {  
1381 - env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);  
1382 - env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;  
1383 - CALL_FROM_TB1(do_raise_exception, EXCP_THREAD);  
1384 - }  
1385 - }  
1386 - } else if (T0 == 0) {  
1387 - if (0 /* TODO: TC underflow */) {  
1388 - env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);  
1389 - CALL_FROM_TB1(do_raise_exception, EXCP_THREAD);  
1390 - } else {  
1391 - // TODO: Deallocate TC  
1392 - }  
1393 - } else if (T0 > 0) {  
1394 - /* Yield qualifier inputs not implemented. */  
1395 - env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);  
1396 - env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;  
1397 - CALL_FROM_TB1(do_raise_exception, EXCP_THREAD);  
1398 - }  
1399 - T0 = env->CP0_YQMask;  
1400 - FORCE_RET();  
1401 -}  
1402 -  
1403 /* CP1 functions */ 463 /* CP1 functions */
1404 #if 0 464 #if 0
1405 # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env) 465 # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
@@ -1407,20 +467,6 @@ void op_yield(void) @@ -1407,20 +467,6 @@ void op_yield(void)
1407 # define DEBUG_FPU_STATE() do { } while(0) 467 # define DEBUG_FPU_STATE() do { } while(0)
1408 #endif 468 #endif
1409 469
1410 -void op_cfc1 (void)  
1411 -{  
1412 - CALL_FROM_TB1(do_cfc1, PARAM1);  
1413 - DEBUG_FPU_STATE();  
1414 - FORCE_RET();  
1415 -}  
1416 -  
1417 -void op_ctc1 (void)  
1418 -{  
1419 - CALL_FROM_TB1(do_ctc1, PARAM1);  
1420 - DEBUG_FPU_STATE();  
1421 - FORCE_RET();  
1422 -}  
1423 -  
1424 void op_mfc1 (void) 470 void op_mfc1 (void)
1425 { 471 {
1426 T0 = (int32_t)WT0; 472 T0 = (int32_t)WT0;
target-mips/op_helper.c
  View file @f1aa632
@@ -306,7 +306,7 @@ void do_mulshiu (void) @@ -306,7 +306,7 @@ void do_mulshiu (void)
306 } 306 }
307 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ 307 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
308 308
309 -#if defined(CONFIG_USER_ONLY) 309 +#ifdef CONFIG_USER_ONLY
310 void do_mfc0_random (void) 310 void do_mfc0_random (void)
311 { 311 {
312 cpu_abort(env, "mfc0 random\n"); 312 cpu_abort(env, "mfc0 random\n");
@@ -360,16 +360,662 @@ void cpu_mips_tlb_flush (CPUState *env, int flush_global) @@ -360,16 +360,662 @@ void cpu_mips_tlb_flush (CPUState *env, int flush_global)
360 #else 360 #else
361 361
362 /* CP0 helpers */ 362 /* CP0 helpers */
  363 +void do_mfc0_mvpcontrol (void)
  364 +{
  365 + T0 = env->mvp->CP0_MVPControl;
  366 +}
  367 +
  368 +void do_mfc0_mvpconf0 (void)
  369 +{
  370 + T0 = env->mvp->CP0_MVPConf0;
  371 +}
  372 +
  373 +void do_mfc0_mvpconf1 (void)
  374 +{
  375 + T0 = env->mvp->CP0_MVPConf1;
  376 +}
  377 +
363 void do_mfc0_random (void) 378 void do_mfc0_random (void)
364 { 379 {
365 T0 = (int32_t)cpu_mips_get_random(env); 380 T0 = (int32_t)cpu_mips_get_random(env);
366 } 381 }
367 382
  383 +void do_mfc0_tcstatus (void)
  384 +{
  385 + T0 = env->CP0_TCStatus[env->current_tc];
  386 +}
  387 +
  388 +void do_mftc0_tcstatus(void)
  389 +{
  390 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  391 +
  392 + T0 = env->CP0_TCStatus[other_tc];
  393 +}
  394 +
  395 +void do_mfc0_tcbind (void)
  396 +{
  397 + T0 = env->CP0_TCBind[env->current_tc];
  398 +}
  399 +
  400 +void do_mftc0_tcbind(void)
  401 +{
  402 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  403 +
  404 + T0 = env->CP0_TCBind[other_tc];
  405 +}
  406 +
  407 +void do_mfc0_tcrestart (void)
  408 +{
  409 + T0 = env->PC[env->current_tc];
  410 +}
  411 +
  412 +void do_mftc0_tcrestart(void)
  413 +{
  414 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  415 +
  416 + T0 = env->PC[other_tc];
  417 +}
  418 +
  419 +void do_mfc0_tchalt (void)
  420 +{
  421 + T0 = env->CP0_TCHalt[env->current_tc];
  422 +}
  423 +
  424 +void do_mftc0_tchalt(void)
  425 +{
  426 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  427 +
  428 + T0 = env->CP0_TCHalt[other_tc];
  429 +}
  430 +
  431 +void do_mfc0_tccontext (void)
  432 +{
  433 + T0 = env->CP0_TCContext[env->current_tc];
  434 +}
  435 +
  436 +void do_mftc0_tccontext(void)
  437 +{
  438 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  439 +
  440 + T0 = env->CP0_TCContext[other_tc];
  441 +}
  442 +
  443 +void do_mfc0_tcschedule (void)
  444 +{
  445 + T0 = env->CP0_TCSchedule[env->current_tc];
  446 +}
  447 +
  448 +void do_mftc0_tcschedule(void)
  449 +{
  450 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  451 +
  452 + T0 = env->CP0_TCSchedule[other_tc];
  453 +}
  454 +
  455 +void do_mfc0_tcschefback (void)
  456 +{
  457 + T0 = env->CP0_TCScheFBack[env->current_tc];
  458 +}
  459 +
  460 +void do_mftc0_tcschefback(void)
  461 +{
  462 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  463 +
  464 + T0 = env->CP0_TCScheFBack[other_tc];
  465 +}
  466 +
368 void do_mfc0_count (void) 467 void do_mfc0_count (void)
369 { 468 {
370 T0 = (int32_t)cpu_mips_get_count(env); 469 T0 = (int32_t)cpu_mips_get_count(env);
371 } 470 }
372 471
  472 +void do_mftc0_entryhi(void)
  473 +{
  474 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  475 +
  476 + T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);
  477 +}
  478 +
  479 +void do_mftc0_status(void)
  480 +{
  481 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  482 + uint32_t tcstatus = env->CP0_TCStatus[other_tc];
  483 +
  484 + T0 = env->CP0_Status & ~0xf1000018;
  485 + T0 |= tcstatus & (0xf << CP0TCSt_TCU0);
  486 + T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
  487 + T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
  488 +}
  489 +
  490 +void do_mfc0_lladdr (void)
  491 +{
  492 + T0 = (int32_t)env->CP0_LLAddr >> 4;
  493 +}
  494 +
  495 +void do_mfc0_watchlo (uint32_t sel)
  496 +{
  497 + T0 = (int32_t)env->CP0_WatchLo[sel];
  498 +}
  499 +
  500 +void do_mfc0_watchhi (uint32_t sel)
  501 +{
  502 + T0 = env->CP0_WatchHi[sel];
  503 +}
  504 +
  505 +void do_mfc0_debug (void)
  506 +{
  507 + T0 = env->CP0_Debug;
  508 + if (env->hflags & MIPS_HFLAG_DM)
  509 + T0 |= 1 << CP0DB_DM;
  510 +}
  511 +
  512 +void do_mftc0_debug(void)
  513 +{
  514 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  515 +
  516 + /* XXX: Might be wrong, check with EJTAG spec. */
  517 + T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
  518 + (env->CP0_Debug_tcstatus[other_tc] &
  519 + ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
  520 +}
  521 +
  522 +#if defined(TARGET_MIPS64)
  523 +void do_dmfc0_tcrestart (void)
  524 +{
  525 + T0 = env->PC[env->current_tc];
  526 +}
  527 +
  528 +void do_dmfc0_tchalt (void)
  529 +{
  530 + T0 = env->CP0_TCHalt[env->current_tc];
  531 +}
  532 +
  533 +void do_dmfc0_tccontext (void)
  534 +{
  535 + T0 = env->CP0_TCContext[env->current_tc];
  536 +}
  537 +
  538 +void do_dmfc0_tcschedule (void)
  539 +{
  540 + T0 = env->CP0_TCSchedule[env->current_tc];
  541 +}
  542 +
  543 +void do_dmfc0_tcschefback (void)
  544 +{
  545 + T0 = env->CP0_TCScheFBack[env->current_tc];
  546 +}
  547 +
  548 +void do_dmfc0_lladdr (void)
  549 +{
  550 + T0 = env->CP0_LLAddr >> 4;
  551 +}
  552 +
  553 +void do_dmfc0_watchlo (uint32_t sel)
  554 +{
  555 + T0 = env->CP0_WatchLo[sel];
  556 +}
  557 +#endif /* TARGET_MIPS64 */
  558 +
  559 +void do_mtc0_index (void)
  560 +{
  561 + int num = 1;
  562 + unsigned int tmp = env->tlb->nb_tlb;
  563 +
  564 + do {
  565 + tmp >>= 1;
  566 + num <<= 1;
  567 + } while (tmp);
  568 + env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (num - 1));
  569 +}
  570 +
  571 +void do_mtc0_mvpcontrol (void)
  572 +{
  573 + uint32_t mask = 0;
  574 + uint32_t newval;
  575 +
  576 + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
  577 + mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
  578 + (1 << CP0MVPCo_EVP);
  579 + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
  580 + mask |= (1 << CP0MVPCo_STLB);
  581 + newval = (env->mvp->CP0_MVPControl & ~mask) | (T0 & mask);
  582 +
  583 + // TODO: Enable/disable shared TLB, enable/disable VPEs.
  584 +
  585 + env->mvp->CP0_MVPControl = newval;
  586 +}
  587 +
  588 +void do_mtc0_vpecontrol (void)
  589 +{
  590 + uint32_t mask;
  591 + uint32_t newval;
  592 +
  593 + mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
  594 + (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
  595 + newval = (env->CP0_VPEControl & ~mask) | (T0 & mask);
  596 +
  597 + /* Yield scheduler intercept not implemented. */
  598 + /* Gating storage scheduler intercept not implemented. */
  599 +
  600 + // TODO: Enable/disable TCs.
  601 +
  602 + env->CP0_VPEControl = newval;
  603 +}
  604 +
  605 +void do_mtc0_vpeconf0 (void)
  606 +{
  607 + uint32_t mask = 0;
  608 + uint32_t newval;
  609 +
  610 + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
  611 + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
  612 + mask |= (0xff << CP0VPEC0_XTC);
  613 + mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
  614 + }
  615 + newval = (env->CP0_VPEConf0 & ~mask) | (T0 & mask);
  616 +
  617 + // TODO: TC exclusive handling due to ERL/EXL.
  618 +
  619 + env->CP0_VPEConf0 = newval;
  620 +}
  621 +
  622 +void do_mtc0_vpeconf1 (void)
  623 +{
  624 + uint32_t mask = 0;
  625 + uint32_t newval;
  626 +
  627 + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
  628 + mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
  629 + (0xff << CP0VPEC1_NCP1);
  630 + newval = (env->CP0_VPEConf1 & ~mask) | (T0 & mask);
  631 +
  632 + /* UDI not implemented. */
  633 + /* CP2 not implemented. */
  634 +
  635 + // TODO: Handle FPU (CP1) binding.
  636 +
  637 + env->CP0_VPEConf1 = newval;
  638 +}
  639 +
  640 +void do_mtc0_yqmask (void)
  641 +{
  642 + /* Yield qualifier inputs not implemented. */
  643 + env->CP0_YQMask = 0x00000000;
  644 +}
  645 +
  646 +void do_mtc0_vpeopt (void)
  647 +{
  648 + env->CP0_VPEOpt = T0 & 0x0000ffff;
  649 +}
  650 +
  651 +void do_mtc0_entrylo0 (void)
  652 +{
  653 + /* Large physaddr (PABITS) not implemented */
  654 + /* 1k pages not implemented */
  655 + env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
  656 +}
  657 +
  658 +void do_mtc0_tcstatus (void)
  659 +{
  660 + uint32_t mask = env->CP0_TCStatus_rw_bitmask;
  661 + uint32_t newval;
  662 +
  663 + newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (T0 & mask);
  664 +
  665 + // TODO: Sync with CP0_Status.
  666 +
  667 + env->CP0_TCStatus[env->current_tc] = newval;
  668 +}
  669 +
  670 +void do_mttc0_tcstatus (void)
  671 +{
  672 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  673 +
  674 + // TODO: Sync with CP0_Status.
  675 +
  676 + env->CP0_TCStatus[other_tc] = T0;
  677 +}
  678 +
  679 +void do_mtc0_tcbind (void)
  680 +{
  681 + uint32_t mask = (1 << CP0TCBd_TBE);
  682 + uint32_t newval;
  683 +
  684 + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
  685 + mask |= (1 << CP0TCBd_CurVPE);
  686 + newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (T0 & mask);
  687 + env->CP0_TCBind[env->current_tc] = newval;
  688 +}
  689 +
  690 +void do_mttc0_tcbind (void)
  691 +{
  692 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  693 + uint32_t mask = (1 << CP0TCBd_TBE);
  694 + uint32_t newval;
  695 +
  696 + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
  697 + mask |= (1 << CP0TCBd_CurVPE);
  698 + newval = (env->CP0_TCBind[other_tc] & ~mask) | (T0 & mask);
  699 + env->CP0_TCBind[other_tc] = newval;
  700 +}
  701 +
  702 +void do_mtc0_tcrestart (void)
  703 +{
  704 + env->PC[env->current_tc] = T0;
  705 + env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS);
  706 + env->CP0_LLAddr = 0ULL;
  707 + /* MIPS16 not implemented. */
  708 +}
  709 +
  710 +void do_mttc0_tcrestart (void)
  711 +{
  712 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  713 +
  714 + env->PC[other_tc] = T0;
  715 + env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS);
  716 + env->CP0_LLAddr = 0ULL;
  717 + /* MIPS16 not implemented. */
  718 +}
  719 +
  720 +void do_mtc0_tchalt (void)
  721 +{
  722 + env->CP0_TCHalt[env->current_tc] = T0 & 0x1;
  723 +
  724 + // TODO: Halt TC / Restart (if allocated+active) TC.
  725 +}
  726 +
  727 +void do_mttc0_tchalt (void)
  728 +{
  729 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  730 +
  731 + // TODO: Halt TC / Restart (if allocated+active) TC.
  732 +
  733 + env->CP0_TCHalt[other_tc] = T0;
  734 +}
  735 +
  736 +void do_mtc0_tccontext (void)
  737 +{
  738 + env->CP0_TCContext[env->current_tc] = T0;
  739 +}
  740 +
  741 +void do_mttc0_tccontext (void)
  742 +{
  743 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  744 +
  745 + env->CP0_TCContext[other_tc] = T0;
  746 +}
  747 +
  748 +void do_mtc0_tcschedule (void)
  749 +{
  750 + env->CP0_TCSchedule[env->current_tc] = T0;
  751 +}
  752 +
  753 +void do_mttc0_tcschedule (void)
  754 +{
  755 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  756 +
  757 + env->CP0_TCSchedule[other_tc] = T0;
  758 +}
  759 +
  760 +void do_mtc0_tcschefback (void)
  761 +{
  762 + env->CP0_TCScheFBack[env->current_tc] = T0;
  763 +}
  764 +
  765 +void do_mttc0_tcschefback (void)
  766 +{
  767 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  768 +
  769 + env->CP0_TCScheFBack[other_tc] = T0;
  770 +}
  771 +
  772 +void do_mtc0_entrylo1 (void)
  773 +{
  774 + /* Large physaddr (PABITS) not implemented */
  775 + /* 1k pages not implemented */
  776 + env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
  777 +}
  778 +
  779 +void do_mtc0_context (void)
  780 +{
  781 + env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
  782 +}
  783 +
  784 +void do_mtc0_pagemask (void)
  785 +{
  786 + /* 1k pages not implemented */
  787 + env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
  788 +}
  789 +
  790 +void do_mtc0_pagegrain (void)
  791 +{
  792 + /* SmartMIPS not implemented */
  793 + /* Large physaddr (PABITS) not implemented */
  794 + /* 1k pages not implemented */
  795 + env->CP0_PageGrain = 0;
  796 +}
  797 +
  798 +void do_mtc0_wired (void)
  799 +{
  800 + env->CP0_Wired = T0 % env->tlb->nb_tlb;
  801 +}
  802 +
  803 +void do_mtc0_srsconf0 (void)
  804 +{
  805 + env->CP0_SRSConf0 |= T0 & env->CP0_SRSConf0_rw_bitmask;
  806 +}
  807 +
  808 +void do_mtc0_srsconf1 (void)
  809 +{
  810 + env->CP0_SRSConf1 |= T0 & env->CP0_SRSConf1_rw_bitmask;
  811 +}
  812 +
  813 +void do_mtc0_srsconf2 (void)
  814 +{
  815 + env->CP0_SRSConf2 |= T0 & env->CP0_SRSConf2_rw_bitmask;
  816 +}
  817 +
  818 +void do_mtc0_srsconf3 (void)
  819 +{
  820 + env->CP0_SRSConf3 |= T0 & env->CP0_SRSConf3_rw_bitmask;
  821 +}
  822 +
  823 +void do_mtc0_srsconf4 (void)
  824 +{
  825 + env->CP0_SRSConf4 |= T0 & env->CP0_SRSConf4_rw_bitmask;
  826 +}
  827 +
  828 +void do_mtc0_hwrena (void)
  829 +{
  830 + env->CP0_HWREna = T0 & 0x0000000F;
  831 +}
  832 +
  833 +void do_mtc0_count (void)
  834 +{
  835 + cpu_mips_store_count(env, T0);
  836 +}
  837 +
  838 +void do_mtc0_entryhi (void)
  839 +{
  840 + target_ulong old, val;
  841 +
  842 + /* 1k pages not implemented */
  843 + val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
  844 +#if defined(TARGET_MIPS64)
  845 + val &= env->SEGMask;
  846 +#endif
  847 + old = env->CP0_EntryHi;
  848 + env->CP0_EntryHi = val;
  849 + if (env->CP0_Config3 & (1 << CP0C3_MT)) {
  850 + uint32_t tcst = env->CP0_TCStatus[env->current_tc] & ~0xff;
  851 + env->CP0_TCStatus[env->current_tc] = tcst | (val & 0xff);
  852 + }
  853 + /* If the ASID changes, flush qemu's TLB. */
  854 + if ((old & 0xFF) != (val & 0xFF))
  855 + cpu_mips_tlb_flush(env, 1);
  856 +}
  857 +
  858 +void do_mttc0_entryhi(void)
  859 +{
  860 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  861 +
  862 + env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (T0 & ~0xff);
  863 + env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (T0 & 0xff);
  864 +}
  865 +
  866 +void do_mtc0_compare (void)
  867 +{
  868 + cpu_mips_store_compare(env, T0);
  869 +}
  870 +
  871 +void do_mtc0_status (void)
  872 +{
  873 + uint32_t val, old;
  874 + uint32_t mask = env->CP0_Status_rw_bitmask;
  875 +
  876 + val = T0 & mask;
  877 + old = env->CP0_Status;
  878 + env->CP0_Status = (env->CP0_Status & ~mask) | val;
  879 + compute_hflags(env);
  880 + if (loglevel & CPU_LOG_EXEC)
  881 + do_mtc0_status_debug(old, val);
  882 + cpu_mips_update_irq(env);
  883 +}
  884 +
  885 +void do_mttc0_status(void)
  886 +{
  887 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  888 + uint32_t tcstatus = env->CP0_TCStatus[other_tc];
  889 +
  890 + env->CP0_Status = T0 & ~0xf1000018;
  891 + tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (T0 & (0xf << CP0St_CU0));
  892 + tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((T0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
  893 + tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((T0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
  894 + env->CP0_TCStatus[other_tc] = tcstatus;
  895 +}
  896 +
  897 +void do_mtc0_intctl (void)
  898 +{
  899 + /* vectored interrupts not implemented, no performance counters. */
  900 + env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (T0 & 0x000002e0);
  901 +}
  902 +
  903 +void do_mtc0_srsctl (void)
  904 +{
  905 + uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
  906 + env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (T0 & mask);
  907 +}
  908 +
  909 +void do_mtc0_cause (void)
  910 +{
  911 + uint32_t mask = 0x00C00300;
  912 + uint32_t old = env->CP0_Cause;
  913 +
  914 + if (env->insn_flags & ISA_MIPS32R2)
  915 + mask |= 1 << CP0Ca_DC;
  916 +
  917 + env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);
  918 +
  919 + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
  920 + if (env->CP0_Cause & (1 << CP0Ca_DC))
  921 + cpu_mips_stop_count(env);
  922 + else
  923 + cpu_mips_start_count(env);
  924 + }
  925 +
  926 + /* Handle the software interrupt as an hardware one, as they
  927 + are very similar */
  928 + if (T0 & CP0Ca_IP_mask) {
  929 + cpu_mips_update_irq(env);
  930 + }
  931 +}
  932 +
  933 +void do_mtc0_ebase (void)
  934 +{
  935 + /* vectored interrupts not implemented */
  936 + /* Multi-CPU not implemented */
  937 + env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
  938 +}
  939 +
  940 +void do_mtc0_config0 (void)
  941 +{
  942 + env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007);
  943 +}
  944 +
  945 +void do_mtc0_config2 (void)
  946 +{
  947 + /* tertiary/secondary caches not implemented */
  948 + env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
  949 +}
  950 +
  951 +void do_mtc0_watchlo (uint32_t sel)
  952 +{
  953 + /* Watch exceptions for instructions, data loads, data stores
  954 + not implemented. */
  955 + env->CP0_WatchLo[sel] = (T0 & ~0x7);
  956 +}
  957 +
  958 +void do_mtc0_watchhi (uint32_t sel)
  959 +{
  960 + env->CP0_WatchHi[sel] = (T0 & 0x40FF0FF8);
  961 + env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & T0 & 0x7);
  962 +}
  963 +
  964 +void do_mtc0_xcontext (void)
  965 +{
  966 + target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
  967 + env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask);
  968 +}
  969 +
  970 +void do_mtc0_framemask (void)
  971 +{
  972 + env->CP0_Framemask = T0; /* XXX */
  973 +}
  974 +
  975 +void do_mtc0_debug (void)
  976 +{
  977 + env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
  978 + if (T0 & (1 << CP0DB_DM))
  979 + env->hflags |= MIPS_HFLAG_DM;
  980 + else
  981 + env->hflags &= ~MIPS_HFLAG_DM;
  982 +}
  983 +
  984 +void do_mttc0_debug(void)
  985 +{
  986 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  987 +
  988 + /* XXX: Might be wrong, check with EJTAG spec. */
  989 + env->CP0_Debug_tcstatus[other_tc] = T0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
  990 + env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
  991 + (T0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
  992 +}
  993 +
  994 +void do_mtc0_performance0 (void)
  995 +{
  996 + env->CP0_Performance0 = T0 & 0x000007ff;
  997 +}
  998 +
  999 +void do_mtc0_taglo (void)
  1000 +{
  1001 + env->CP0_TagLo = T0 & 0xFFFFFCF6;
  1002 +}
  1003 +
  1004 +void do_mtc0_datalo (void)
  1005 +{
  1006 + env->CP0_DataLo = T0; /* XXX */
  1007 +}
  1008 +
  1009 +void do_mtc0_taghi (void)
  1010 +{
  1011 + env->CP0_TagHi = T0; /* XXX */
  1012 +}
  1013 +
  1014 +void do_mtc0_datahi (void)
  1015 +{
  1016 + env->CP0_DataHi = T0; /* XXX */
  1017 +}
  1018 +
373 void do_mtc0_status_debug(uint32_t old, uint32_t val) 1019 void do_mtc0_status_debug(uint32_t old, uint32_t val)
374 { 1020 {
375 fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x", 1021 fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
@@ -388,7 +1034,144 @@ void do_mtc0_status_irqraise_debug(void) @@ -388,7 +1034,144 @@ void do_mtc0_status_irqraise_debug(void)
388 { 1034 {
389 fprintf(logfile, "Raise pending IRQs\n"); 1035 fprintf(logfile, "Raise pending IRQs\n");
390 } 1036 }
  1037 +#endif /* !CONFIG_USER_ONLY */
  1038 +
  1039 +/* MIPS MT functions */
  1040 +void do_mftgpr(uint32_t sel)
  1041 +{
  1042 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1043 +
  1044 + T0 = env->gpr[other_tc][sel];
  1045 +}
  1046 +
  1047 +void do_mftlo(uint32_t sel)
  1048 +{
  1049 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1050 +
  1051 + T0 = env->LO[other_tc][sel];
  1052 +}
  1053 +
  1054 +void do_mfthi(uint32_t sel)
  1055 +{
  1056 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1057 +
  1058 + T0 = env->HI[other_tc][sel];
  1059 +}
  1060 +
  1061 +void do_mftacx(uint32_t sel)
  1062 +{
  1063 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1064 +
  1065 + T0 = env->ACX[other_tc][sel];
  1066 +}
  1067 +
  1068 +void do_mftdsp(void)
  1069 +{
  1070 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1071 +
  1072 + T0 = env->DSPControl[other_tc];
  1073 +}
391 1074
  1075 +void do_mttgpr(uint32_t sel)
  1076 +{
  1077 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1078 +
  1079 + T0 = env->gpr[other_tc][sel];
  1080 +}
  1081 +
  1082 +void do_mttlo(uint32_t sel)
  1083 +{
  1084 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1085 +
  1086 + T0 = env->LO[other_tc][sel];
  1087 +}
  1088 +
  1089 +void do_mtthi(uint32_t sel)
  1090 +{
  1091 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1092 +
  1093 + T0 = env->HI[other_tc][sel];
  1094 +}
  1095 +
  1096 +void do_mttacx(uint32_t sel)
  1097 +{
  1098 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1099 +
  1100 + T0 = env->ACX[other_tc][sel];
  1101 +}
  1102 +
  1103 +void do_mttdsp(void)
  1104 +{
  1105 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1106 +
  1107 + T0 = env->DSPControl[other_tc];
  1108 +}
  1109 +
  1110 +/* MIPS MT functions */
  1111 +void do_dmt(void)
  1112 +{
  1113 + // TODO
  1114 + T0 = 0;
  1115 + // rt = T0
  1116 +}
  1117 +
  1118 +void do_emt(void)
  1119 +{
  1120 + // TODO
  1121 + T0 = 0;
  1122 + // rt = T0
  1123 +}
  1124 +
  1125 +void do_dvpe(void)
  1126 +{
  1127 + // TODO
  1128 + T0 = 0;
  1129 + // rt = T0
  1130 +}
  1131 +
  1132 +void do_evpe(void)
  1133 +{
  1134 + // TODO
  1135 + T0 = 0;
  1136 + // rt = T0
  1137 +}
  1138 +
  1139 +void do_fork(void)
  1140 +{
  1141 + // T0 = rt, T1 = rs
  1142 + T0 = 0;
  1143 + // TODO: store to TC register
  1144 +}
  1145 +
  1146 +void do_yield(void)
  1147 +{
  1148 + if (T0 < 0) {
  1149 + /* No scheduling policy implemented. */
  1150 + if (T0 != -2) {
  1151 + if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
  1152 + env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) {
  1153 + env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
  1154 + env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
  1155 + do_raise_exception(EXCP_THREAD);
  1156 + }
  1157 + }
  1158 + } else if (T0 == 0) {
  1159 + if (0 /* TODO: TC underflow */) {
  1160 + env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
  1161 + do_raise_exception(EXCP_THREAD);
  1162 + } else {
  1163 + // TODO: Deallocate TC
  1164 + }
  1165 + } else if (T0 > 0) {
  1166 + /* Yield qualifier inputs not implemented. */
  1167 + env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
  1168 + env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
  1169 + do_raise_exception(EXCP_THREAD);
  1170 + }
  1171 + T0 = env->CP0_YQMask;
  1172 +}
  1173 +
  1174 +/* CP1 functions */
392 void fpu_handle_exception(void) 1175 void fpu_handle_exception(void)
393 { 1176 {
394 #ifdef CONFIG_SOFTFLOAT 1177 #ifdef CONFIG_SOFTFLOAT
@@ -426,6 +1209,7 @@ void fpu_handle_exception(void) @@ -426,6 +1209,7 @@ void fpu_handle_exception(void)
426 #endif 1209 #endif
427 } 1210 }
428 1211
  1212 +#ifndef CONFIG_USER_ONLY
429 /* TLB management */ 1213 /* TLB management */
430 void cpu_mips_tlb_flush (CPUState *env, int flush_global) 1214 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
431 { 1215 {
@@ -679,7 +1463,7 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec, @@ -679,7 +1463,7 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
679 else 1463 else
680 do_raise_exception(EXCP_DBE); 1464 do_raise_exception(EXCP_DBE);
681 } 1465 }
682 -#endif 1466 +#endif /* !CONFIG_USER_ONLY */
683 1467
684 /* Complex FPU operations which may need stack space. */ 1468 /* Complex FPU operations which may need stack space. */
685 1469
@@ -703,7 +1487,7 @@ unsigned int ieee_rm[] = { @@ -703,7 +1487,7 @@ unsigned int ieee_rm[] = {
703 #define RESTORE_ROUNDING_MODE \ 1487 #define RESTORE_ROUNDING_MODE \
704 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status) 1488 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
705 1489
706 -void do_cfc1 (int reg) 1490 +void do_cfc1 (uint32_t reg)
707 { 1491 {
708 switch (reg) { 1492 switch (reg) {
709 case 0: 1493 case 0:
@@ -724,7 +1508,7 @@ void do_cfc1 (int reg) @@ -724,7 +1508,7 @@ void do_cfc1 (int reg)
724 } 1508 }
725 } 1509 }
726 1510
727 -void do_ctc1 (int reg) 1511 +void do_ctc1 (uint32_t reg)
728 { 1512 {
729 switch(reg) { 1513 switch(reg) {
730 case 25: 1514 case 25:
target-mips/translate.c
  View file @f1aa632
@@ -2583,6 +2583,7 @@ fail: @@ -2583,6 +2583,7 @@ fail:
2583 } 2583 }
2584 2584
2585 /* CP0 (MMU and control) */ 2585 /* CP0 (MMU and control) */
  2586 +#ifndef CONFIG_USER_ONLY
2586 static inline void gen_mfc0_load32 (TCGv t, target_ulong off) 2587 static inline void gen_mfc0_load32 (TCGv t, target_ulong off)
2587 { 2588 {
2588 TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32); 2589 TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
@@ -2601,6 +2602,24 @@ static inline void gen_mfc0_load64 (TCGv t, target_ulong off) @@ -2601,6 +2602,24 @@ static inline void gen_mfc0_load64 (TCGv t, target_ulong off)
2601 tcg_temp_free(r_tmp); 2602 tcg_temp_free(r_tmp);
2602 } 2603 }
2603 2604
  2605 +static inline void gen_mtc0_store32 (TCGv t, target_ulong off)
  2606 +{
  2607 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
  2608 +
  2609 + tcg_gen_trunc_tl_i32(r_tmp, t);
  2610 + tcg_gen_st_i32(r_tmp, cpu_env, off);
  2611 + tcg_temp_free(r_tmp);
  2612 +}
  2613 +
  2614 +static inline void gen_mtc0_store64 (TCGv t, target_ulong off)
  2615 +{
  2616 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_I64);
  2617 +
  2618 + tcg_gen_ext_tl_i64(r_tmp, t);
  2619 + tcg_gen_st_i64(r_tmp, cpu_env, off);
  2620 + tcg_temp_free(r_tmp);
  2621 +}
  2622 +
2604 static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) 2623 static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2605 { 2624 {
2606 const char *rn = "invalid"; 2625 const char *rn = "invalid";
@@ -2617,17 +2636,17 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2617,17 +2636,17 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2617 break; 2636 break;
2618 case 1: 2637 case 1:
2619 check_insn(env, ctx, ASE_MT); 2638 check_insn(env, ctx, ASE_MT);
2620 - gen_op_mfc0_mvpcontrol(); 2639 + tcg_gen_helper_0_0(do_mfc0_mvpcontrol);
2621 rn = "MVPControl"; 2640 rn = "MVPControl";
2622 break; 2641 break;
2623 case 2: 2642 case 2:
2624 check_insn(env, ctx, ASE_MT); 2643 check_insn(env, ctx, ASE_MT);
2625 - gen_op_mfc0_mvpconf0(); 2644 + tcg_gen_helper_0_0(do_mfc0_mvpconf0);
2626 rn = "MVPConf0"; 2645 rn = "MVPConf0";
2627 break; 2646 break;
2628 case 3: 2647 case 3:
2629 check_insn(env, ctx, ASE_MT); 2648 check_insn(env, ctx, ASE_MT);
2630 - gen_op_mfc0_mvpconf1(); 2649 + tcg_gen_helper_0_0(do_mfc0_mvpconf1);
2631 rn = "MVPConf1"; 2650 rn = "MVPConf1";
2632 break; 2651 break;
2633 default: 2652 default:
@@ -2637,7 +2656,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2637,7 +2656,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2637 case 1: 2656 case 1:
2638 switch (sel) { 2657 switch (sel) {
2639 case 0: 2658 case 0:
2640 - gen_op_mfc0_random(); 2659 + tcg_gen_helper_0_0(do_mfc0_random);
2641 rn = "Random"; 2660 rn = "Random";
2642 break; 2661 break;
2643 case 1: 2662 case 1:
@@ -2688,37 +2707,37 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2688,37 +2707,37 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2688 break; 2707 break;
2689 case 1: 2708 case 1:
2690 check_insn(env, ctx, ASE_MT); 2709 check_insn(env, ctx, ASE_MT);
2691 - gen_op_mfc0_tcstatus(); 2710 + tcg_gen_helper_0_0(do_mfc0_tcstatus);
2692 rn = "TCStatus"; 2711 rn = "TCStatus";
2693 break; 2712 break;
2694 case 2: 2713 case 2:
2695 check_insn(env, ctx, ASE_MT); 2714 check_insn(env, ctx, ASE_MT);
2696 - gen_op_mfc0_tcbind(); 2715 + tcg_gen_helper_0_0(do_mfc0_tcbind);
2697 rn = "TCBind"; 2716 rn = "TCBind";
2698 break; 2717 break;
2699 case 3: 2718 case 3:
2700 check_insn(env, ctx, ASE_MT); 2719 check_insn(env, ctx, ASE_MT);
2701 - gen_op_mfc0_tcrestart(); 2720 + tcg_gen_helper_0_0(do_mfc0_tcrestart);
2702 rn = "TCRestart"; 2721 rn = "TCRestart";
2703 break; 2722 break;
2704 case 4: 2723 case 4:
2705 check_insn(env, ctx, ASE_MT); 2724 check_insn(env, ctx, ASE_MT);
2706 - gen_op_mfc0_tchalt(); 2725 + tcg_gen_helper_0_0(do_mfc0_tchalt);
2707 rn = "TCHalt"; 2726 rn = "TCHalt";
2708 break; 2727 break;
2709 case 5: 2728 case 5:
2710 check_insn(env, ctx, ASE_MT); 2729 check_insn(env, ctx, ASE_MT);
2711 - gen_op_mfc0_tccontext(); 2730 + tcg_gen_helper_0_0(do_mfc0_tccontext);
2712 rn = "TCContext"; 2731 rn = "TCContext";
2713 break; 2732 break;
2714 case 6: 2733 case 6:
2715 check_insn(env, ctx, ASE_MT); 2734 check_insn(env, ctx, ASE_MT);
2716 - gen_op_mfc0_tcschedule(); 2735 + tcg_gen_helper_0_0(do_mfc0_tcschedule);
2717 rn = "TCSchedule"; 2736 rn = "TCSchedule";
2718 break; 2737 break;
2719 case 7: 2738 case 7:
2720 check_insn(env, ctx, ASE_MT); 2739 check_insn(env, ctx, ASE_MT);
2721 - gen_op_mfc0_tcschefback(); 2740 + tcg_gen_helper_0_0(do_mfc0_tcschefback);
2722 rn = "TCScheFBack"; 2741 rn = "TCScheFBack";
2723 break; 2742 break;
2724 default: 2743 default:
@@ -2744,7 +2763,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2744,7 +2763,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2744 rn = "Context"; 2763 rn = "Context";
2745 break; 2764 break;
2746 case 1: 2765 case 1:
2747 -// gen_op_mfc0_contextconfig(); /* SmartMIPS ASE */ 2766 +// tcg_gen_helper_0_0(do_mfc0_contextconfig); /* SmartMIPS ASE */
2748 rn = "ContextConfig"; 2767 rn = "ContextConfig";
2749 // break; 2768 // break;
2750 default: 2769 default:
@@ -2826,7 +2845,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2826,7 +2845,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2826 case 9: 2845 case 9:
2827 switch (sel) { 2846 switch (sel) {
2828 case 0: 2847 case 0:
2829 - gen_op_mfc0_count(); 2848 + tcg_gen_helper_0_0(do_mfc0_count);
2830 rn = "Count"; 2849 rn = "Count";
2831 break; 2850 break;
2832 /* 6,7 are implementation dependent */ 2851 /* 6,7 are implementation dependent */
@@ -2952,7 +2971,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2952,7 +2971,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2952 case 17: 2971 case 17:
2953 switch (sel) { 2972 switch (sel) {
2954 case 0: 2973 case 0:
2955 - gen_op_mfc0_lladdr(); 2974 + tcg_gen_helper_0_0(do_mfc0_lladdr);
2956 rn = "LLAddr"; 2975 rn = "LLAddr";
2957 break; 2976 break;
2958 default: 2977 default:
@@ -2962,7 +2981,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2962,7 +2981,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2962 case 18: 2981 case 18:
2963 switch (sel) { 2982 switch (sel) {
2964 case 0 ... 7: 2983 case 0 ... 7:
2965 - gen_op_mfc0_watchlo(sel); 2984 + tcg_gen_helper_0_1i(do_mfc0_watchlo, sel);
2966 rn = "WatchLo"; 2985 rn = "WatchLo";
2967 break; 2986 break;
2968 default: 2987 default:
@@ -2972,7 +2991,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -2972,7 +2991,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2972 case 19: 2991 case 19:
2973 switch (sel) { 2992 switch (sel) {
2974 case 0 ...7: 2993 case 0 ...7:
2975 - gen_op_mfc0_watchhi(sel); 2994 + tcg_gen_helper_0_1i(do_mfc0_watchhi, sel);
2976 rn = "WatchHi"; 2995 rn = "WatchHi";
2977 break; 2996 break;
2978 default: 2997 default:
@@ -3011,23 +3030,23 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3011,23 +3030,23 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3011 case 23: 3030 case 23:
3012 switch (sel) { 3031 switch (sel) {
3013 case 0: 3032 case 0:
3014 - gen_op_mfc0_debug(); /* EJTAG support */ 3033 + tcg_gen_helper_0_0(do_mfc0_debug); /* EJTAG support */
3015 rn = "Debug"; 3034 rn = "Debug";
3016 break; 3035 break;
3017 case 1: 3036 case 1:
3018 -// gen_op_mfc0_tracecontrol(); /* PDtrace support */ 3037 +// tcg_gen_helper_0_0(do_mfc0_tracecontrol); /* PDtrace support */
3019 rn = "TraceControl"; 3038 rn = "TraceControl";
3020 // break; 3039 // break;
3021 case 2: 3040 case 2:
3022 -// gen_op_mfc0_tracecontrol2(); /* PDtrace support */ 3041 +// tcg_gen_helper_0_0(do_mfc0_tracecontrol2); /* PDtrace support */
3023 rn = "TraceControl2"; 3042 rn = "TraceControl2";
3024 // break; 3043 // break;
3025 case 3: 3044 case 3:
3026 -// gen_op_mfc0_usertracedata(); /* PDtrace support */ 3045 +// tcg_gen_helper_0_0(do_mfc0_usertracedata); /* PDtrace support */
3027 rn = "UserTraceData"; 3046 rn = "UserTraceData";
3028 // break; 3047 // break;
3029 case 4: 3048 case 4:
3030 -// gen_op_mfc0_debug(); /* PDtrace support */ 3049 +// tcg_gen_helper_0_0(do_mfc0_debug); /* PDtrace support */
3031 rn = "TraceBPC"; 3050 rn = "TraceBPC";
3032 // break; 3051 // break;
3033 default: 3052 default:
@@ -3053,31 +3072,31 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3053,31 +3072,31 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3053 rn = "Performance0"; 3072 rn = "Performance0";
3054 break; 3073 break;
3055 case 1: 3074 case 1:
3056 -// gen_op_mfc0_performance1(); 3075 +// tcg_gen_helper_0_0(do_mfc0_performance1);
3057 rn = "Performance1"; 3076 rn = "Performance1";
3058 // break; 3077 // break;
3059 case 2: 3078 case 2:
3060 -// gen_op_mfc0_performance2(); 3079 +// tcg_gen_helper_0_0(do_mfc0_performance2);
3061 rn = "Performance2"; 3080 rn = "Performance2";
3062 // break; 3081 // break;
3063 case 3: 3082 case 3:
3064 -// gen_op_mfc0_performance3(); 3083 +// tcg_gen_helper_0_0(do_mfc0_performance3);
3065 rn = "Performance3"; 3084 rn = "Performance3";
3066 // break; 3085 // break;
3067 case 4: 3086 case 4:
3068 -// gen_op_mfc0_performance4(); 3087 +// tcg_gen_helper_0_0(do_mfc0_performance4);
3069 rn = "Performance4"; 3088 rn = "Performance4";
3070 // break; 3089 // break;
3071 case 5: 3090 case 5:
3072 -// gen_op_mfc0_performance5(); 3091 +// tcg_gen_helper_0_0(do_mfc0_performance5);
3073 rn = "Performance5"; 3092 rn = "Performance5";
3074 // break; 3093 // break;
3075 case 6: 3094 case 6:
3076 -// gen_op_mfc0_performance6(); 3095 +// tcg_gen_helper_0_0(do_mfc0_performance6);
3077 rn = "Performance6"; 3096 rn = "Performance6";
3078 // break; 3097 // break;
3079 case 7: 3098 case 7:
3080 -// gen_op_mfc0_performance7(); 3099 +// tcg_gen_helper_0_0(do_mfc0_performance7);
3081 rn = "Performance7"; 3100 rn = "Performance7";
3082 // break; 3101 // break;
3083 default: 3102 default:
@@ -3191,12 +3210,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3191,12 +3210,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3191 case 0: 3210 case 0:
3192 switch (sel) { 3211 switch (sel) {
3193 case 0: 3212 case 0:
3194 - gen_op_mtc0_index(); 3213 + tcg_gen_helper_0_0(do_mtc0_index);
3195 rn = "Index"; 3214 rn = "Index";
3196 break; 3215 break;
3197 case 1: 3216 case 1:
3198 check_insn(env, ctx, ASE_MT); 3217 check_insn(env, ctx, ASE_MT);
3199 - gen_op_mtc0_mvpcontrol(); 3218 + tcg_gen_helper_0_0(do_mtc0_mvpcontrol);
3200 rn = "MVPControl"; 3219 rn = "MVPControl";
3201 break; 3220 break;
3202 case 2: 3221 case 2:
@@ -3221,37 +3240,37 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3221,37 +3240,37 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3221 break; 3240 break;
3222 case 1: 3241 case 1:
3223 check_insn(env, ctx, ASE_MT); 3242 check_insn(env, ctx, ASE_MT);
3224 - gen_op_mtc0_vpecontrol(); 3243 + tcg_gen_helper_0_0(do_mtc0_vpecontrol);
3225 rn = "VPEControl"; 3244 rn = "VPEControl";
3226 break; 3245 break;
3227 case 2: 3246 case 2:
3228 check_insn(env, ctx, ASE_MT); 3247 check_insn(env, ctx, ASE_MT);
3229 - gen_op_mtc0_vpeconf0(); 3248 + tcg_gen_helper_0_0(do_mtc0_vpeconf0);
3230 rn = "VPEConf0"; 3249 rn = "VPEConf0";
3231 break; 3250 break;
3232 case 3: 3251 case 3:
3233 check_insn(env, ctx, ASE_MT); 3252 check_insn(env, ctx, ASE_MT);
3234 - gen_op_mtc0_vpeconf1(); 3253 + tcg_gen_helper_0_0(do_mtc0_vpeconf1);
3235 rn = "VPEConf1"; 3254 rn = "VPEConf1";
3236 break; 3255 break;
3237 case 4: 3256 case 4:
3238 check_insn(env, ctx, ASE_MT); 3257 check_insn(env, ctx, ASE_MT);
3239 - gen_op_mtc0_yqmask(); 3258 + tcg_gen_helper_0_0(do_mtc0_yqmask);
3240 rn = "YQMask"; 3259 rn = "YQMask";
3241 break; 3260 break;
3242 case 5: 3261 case 5:
3243 check_insn(env, ctx, ASE_MT); 3262 check_insn(env, ctx, ASE_MT);
3244 - gen_op_mtc0_vpeschedule(); 3263 + gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_VPESchedule));
3245 rn = "VPESchedule"; 3264 rn = "VPESchedule";
3246 break; 3265 break;
3247 case 6: 3266 case 6:
3248 check_insn(env, ctx, ASE_MT); 3267 check_insn(env, ctx, ASE_MT);
3249 - gen_op_mtc0_vpeschefback(); 3268 + gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_VPEScheFBack));
3250 rn = "VPEScheFBack"; 3269 rn = "VPEScheFBack";
3251 break; 3270 break;
3252 case 7: 3271 case 7:
3253 check_insn(env, ctx, ASE_MT); 3272 check_insn(env, ctx, ASE_MT);
3254 - gen_op_mtc0_vpeopt(); 3273 + tcg_gen_helper_0_0(do_mtc0_vpeopt);
3255 rn = "VPEOpt"; 3274 rn = "VPEOpt";
3256 break; 3275 break;
3257 default: 3276 default:
@@ -3261,42 +3280,42 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3261,42 +3280,42 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3261 case 2: 3280 case 2:
3262 switch (sel) { 3281 switch (sel) {
3263 case 0: 3282 case 0:
3264 - gen_op_mtc0_entrylo0(); 3283 + tcg_gen_helper_0_0(do_mtc0_entrylo0);
3265 rn = "EntryLo0"; 3284 rn = "EntryLo0";
3266 break; 3285 break;
3267 case 1: 3286 case 1:
3268 check_insn(env, ctx, ASE_MT); 3287 check_insn(env, ctx, ASE_MT);
3269 - gen_op_mtc0_tcstatus(); 3288 + tcg_gen_helper_0_0(do_mtc0_tcstatus);
3270 rn = "TCStatus"; 3289 rn = "TCStatus";
3271 break; 3290 break;
3272 case 2: 3291 case 2:
3273 check_insn(env, ctx, ASE_MT); 3292 check_insn(env, ctx, ASE_MT);
3274 - gen_op_mtc0_tcbind(); 3293 + tcg_gen_helper_0_0(do_mtc0_tcbind);
3275 rn = "TCBind"; 3294 rn = "TCBind";
3276 break; 3295 break;
3277 case 3: 3296 case 3:
3278 check_insn(env, ctx, ASE_MT); 3297 check_insn(env, ctx, ASE_MT);
3279 - gen_op_mtc0_tcrestart(); 3298 + tcg_gen_helper_0_0(do_mtc0_tcrestart);
3280 rn = "TCRestart"; 3299 rn = "TCRestart";
3281 break; 3300 break;
3282 case 4: 3301 case 4:
3283 check_insn(env, ctx, ASE_MT); 3302 check_insn(env, ctx, ASE_MT);
3284 - gen_op_mtc0_tchalt(); 3303 + tcg_gen_helper_0_0(do_mtc0_tchalt);
3285 rn = "TCHalt"; 3304 rn = "TCHalt";
3286 break; 3305 break;
3287 case 5: 3306 case 5:
3288 check_insn(env, ctx, ASE_MT); 3307 check_insn(env, ctx, ASE_MT);
3289 - gen_op_mtc0_tccontext(); 3308 + tcg_gen_helper_0_0(do_mtc0_tccontext);
3290 rn = "TCContext"; 3309 rn = "TCContext";
3291 break; 3310 break;
3292 case 6: 3311 case 6:
3293 check_insn(env, ctx, ASE_MT); 3312 check_insn(env, ctx, ASE_MT);
3294 - gen_op_mtc0_tcschedule(); 3313 + tcg_gen_helper_0_0(do_mtc0_tcschedule);
3295 rn = "TCSchedule"; 3314 rn = "TCSchedule";
3296 break; 3315 break;
3297 case 7: 3316 case 7:
3298 check_insn(env, ctx, ASE_MT); 3317 check_insn(env, ctx, ASE_MT);
3299 - gen_op_mtc0_tcschefback(); 3318 + tcg_gen_helper_0_0(do_mtc0_tcschefback);
3300 rn = "TCScheFBack"; 3319 rn = "TCScheFBack";
3301 break; 3320 break;
3302 default: 3321 default:
@@ -3306,7 +3325,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3306,7 +3325,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3306 case 3: 3325 case 3:
3307 switch (sel) { 3326 switch (sel) {
3308 case 0: 3327 case 0:
3309 - gen_op_mtc0_entrylo1(); 3328 + tcg_gen_helper_0_0(do_mtc0_entrylo1);
3310 rn = "EntryLo1"; 3329 rn = "EntryLo1";
3311 break; 3330 break;
3312 default: 3331 default:
@@ -3316,11 +3335,11 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3316,11 +3335,11 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3316 case 4: 3335 case 4:
3317 switch (sel) { 3336 switch (sel) {
3318 case 0: 3337 case 0:
3319 - gen_op_mtc0_context(); 3338 + tcg_gen_helper_0_0(do_mtc0_context);
3320 rn = "Context"; 3339 rn = "Context";
3321 break; 3340 break;
3322 case 1: 3341 case 1:
3323 -// gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */ 3342 +// tcg_gen_helper_0_0(do_mtc0_contextconfig); /* SmartMIPS ASE */
3324 rn = "ContextConfig"; 3343 rn = "ContextConfig";
3325 // break; 3344 // break;
3326 default: 3345 default:
@@ -3330,12 +3349,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3330,12 +3349,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3330 case 5: 3349 case 5:
3331 switch (sel) { 3350 switch (sel) {
3332 case 0: 3351 case 0:
3333 - gen_op_mtc0_pagemask(); 3352 + tcg_gen_helper_0_0(do_mtc0_pagemask);
3334 rn = "PageMask"; 3353 rn = "PageMask";
3335 break; 3354 break;
3336 case 1: 3355 case 1:
3337 check_insn(env, ctx, ISA_MIPS32R2); 3356 check_insn(env, ctx, ISA_MIPS32R2);
3338 - gen_op_mtc0_pagegrain(); 3357 + tcg_gen_helper_0_0(do_mtc0_pagegrain);
3339 rn = "PageGrain"; 3358 rn = "PageGrain";
3340 break; 3359 break;
3341 default: 3360 default:
@@ -3345,32 +3364,32 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3345,32 +3364,32 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3345 case 6: 3364 case 6:
3346 switch (sel) { 3365 switch (sel) {
3347 case 0: 3366 case 0:
3348 - gen_op_mtc0_wired(); 3367 + tcg_gen_helper_0_0(do_mtc0_wired);
3349 rn = "Wired"; 3368 rn = "Wired";
3350 break; 3369 break;
3351 case 1: 3370 case 1:
3352 check_insn(env, ctx, ISA_MIPS32R2); 3371 check_insn(env, ctx, ISA_MIPS32R2);
3353 - gen_op_mtc0_srsconf0(); 3372 + tcg_gen_helper_0_0(do_mtc0_srsconf0);
3354 rn = "SRSConf0"; 3373 rn = "SRSConf0";
3355 break; 3374 break;
3356 case 2: 3375 case 2:
3357 check_insn(env, ctx, ISA_MIPS32R2); 3376 check_insn(env, ctx, ISA_MIPS32R2);
3358 - gen_op_mtc0_srsconf1(); 3377 + tcg_gen_helper_0_0(do_mtc0_srsconf1);
3359 rn = "SRSConf1"; 3378 rn = "SRSConf1";
3360 break; 3379 break;
3361 case 3: 3380 case 3:
3362 check_insn(env, ctx, ISA_MIPS32R2); 3381 check_insn(env, ctx, ISA_MIPS32R2);
3363 - gen_op_mtc0_srsconf2(); 3382 + tcg_gen_helper_0_0(do_mtc0_srsconf2);
3364 rn = "SRSConf2"; 3383 rn = "SRSConf2";
3365 break; 3384 break;
3366 case 4: 3385 case 4:
3367 check_insn(env, ctx, ISA_MIPS32R2); 3386 check_insn(env, ctx, ISA_MIPS32R2);
3368 - gen_op_mtc0_srsconf3(); 3387 + tcg_gen_helper_0_0(do_mtc0_srsconf3);
3369 rn = "SRSConf3"; 3388 rn = "SRSConf3";
3370 break; 3389 break;
3371 case 5: 3390 case 5:
3372 check_insn(env, ctx, ISA_MIPS32R2); 3391 check_insn(env, ctx, ISA_MIPS32R2);
3373 - gen_op_mtc0_srsconf4(); 3392 + tcg_gen_helper_0_0(do_mtc0_srsconf4);
3374 rn = "SRSConf4"; 3393 rn = "SRSConf4";
3375 break; 3394 break;
3376 default: 3395 default:
@@ -3381,7 +3400,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3381,7 +3400,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3381 switch (sel) { 3400 switch (sel) {
3382 case 0: 3401 case 0:
3383 check_insn(env, ctx, ISA_MIPS32R2); 3402 check_insn(env, ctx, ISA_MIPS32R2);
3384 - gen_op_mtc0_hwrena(); 3403 + tcg_gen_helper_0_0(do_mtc0_hwrena);
3385 rn = "HWREna"; 3404 rn = "HWREna";
3386 break; 3405 break;
3387 default: 3406 default:
@@ -3395,7 +3414,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3395,7 +3414,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3395 case 9: 3414 case 9:
3396 switch (sel) { 3415 switch (sel) {
3397 case 0: 3416 case 0:
3398 - gen_op_mtc0_count(); 3417 + tcg_gen_helper_0_0(do_mtc0_count);
3399 rn = "Count"; 3418 rn = "Count";
3400 break; 3419 break;
3401 /* 6,7 are implementation dependent */ 3420 /* 6,7 are implementation dependent */
@@ -3408,7 +3427,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3408,7 +3427,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3408 case 10: 3427 case 10:
3409 switch (sel) { 3428 switch (sel) {
3410 case 0: 3429 case 0:
3411 - gen_op_mtc0_entryhi(); 3430 + tcg_gen_helper_0_0(do_mtc0_entryhi);
3412 rn = "EntryHi"; 3431 rn = "EntryHi";
3413 break; 3432 break;
3414 default: 3433 default:
@@ -3418,7 +3437,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3418,7 +3437,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3418 case 11: 3437 case 11:
3419 switch (sel) { 3438 switch (sel) {
3420 case 0: 3439 case 0:
3421 - gen_op_mtc0_compare(); 3440 + tcg_gen_helper_0_0(do_mtc0_compare);
3422 rn = "Compare"; 3441 rn = "Compare";
3423 break; 3442 break;
3424 /* 6,7 are implementation dependent */ 3443 /* 6,7 are implementation dependent */
@@ -3431,7 +3450,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3431,7 +3450,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3431 case 12: 3450 case 12:
3432 switch (sel) { 3451 switch (sel) {
3433 case 0: 3452 case 0:
3434 - gen_op_mtc0_status(); 3453 + tcg_gen_helper_0_0(do_mtc0_status);
3435 /* BS_STOP isn't good enough here, hflags may have changed. */ 3454 /* BS_STOP isn't good enough here, hflags may have changed. */
3436 gen_save_pc(ctx->pc + 4); 3455 gen_save_pc(ctx->pc + 4);
3437 ctx->bstate = BS_EXCP; 3456 ctx->bstate = BS_EXCP;
@@ -3439,21 +3458,21 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3439,21 +3458,21 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3439 break; 3458 break;
3440 case 1: 3459 case 1:
3441 check_insn(env, ctx, ISA_MIPS32R2); 3460 check_insn(env, ctx, ISA_MIPS32R2);
3442 - gen_op_mtc0_intctl(); 3461 + tcg_gen_helper_0_0(do_mtc0_intctl);
3443 /* Stop translation as we may have switched the execution mode */ 3462 /* Stop translation as we may have switched the execution mode */
3444 ctx->bstate = BS_STOP; 3463 ctx->bstate = BS_STOP;
3445 rn = "IntCtl"; 3464 rn = "IntCtl";
3446 break; 3465 break;
3447 case 2: 3466 case 2:
3448 check_insn(env, ctx, ISA_MIPS32R2); 3467 check_insn(env, ctx, ISA_MIPS32R2);
3449 - gen_op_mtc0_srsctl(); 3468 + tcg_gen_helper_0_0(do_mtc0_srsctl);
3450 /* Stop translation as we may have switched the execution mode */ 3469 /* Stop translation as we may have switched the execution mode */
3451 ctx->bstate = BS_STOP; 3470 ctx->bstate = BS_STOP;
3452 rn = "SRSCtl"; 3471 rn = "SRSCtl";
3453 break; 3472 break;
3454 case 3: 3473 case 3:
3455 check_insn(env, ctx, ISA_MIPS32R2); 3474 check_insn(env, ctx, ISA_MIPS32R2);
3456 - gen_op_mtc0_srsmap(); 3475 + gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_SRSMap));
3457 /* Stop translation as we may have switched the execution mode */ 3476 /* Stop translation as we may have switched the execution mode */
3458 ctx->bstate = BS_STOP; 3477 ctx->bstate = BS_STOP;
3459 rn = "SRSMap"; 3478 rn = "SRSMap";
@@ -3465,7 +3484,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3465,7 +3484,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3465 case 13: 3484 case 13:
3466 switch (sel) { 3485 switch (sel) {
3467 case 0: 3486 case 0:
3468 - gen_op_mtc0_cause(); 3487 + tcg_gen_helper_0_0(do_mtc0_cause);
3469 rn = "Cause"; 3488 rn = "Cause";
3470 break; 3489 break;
3471 default: 3490 default:
@@ -3477,7 +3496,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3477,7 +3496,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3477 case 14: 3496 case 14:
3478 switch (sel) { 3497 switch (sel) {
3479 case 0: 3498 case 0:
3480 - gen_op_mtc0_epc(); 3499 + gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_EPC));
3481 rn = "EPC"; 3500 rn = "EPC";
3482 break; 3501 break;
3483 default: 3502 default:
@@ -3492,7 +3511,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3492,7 +3511,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3492 break; 3511 break;
3493 case 1: 3512 case 1:
3494 check_insn(env, ctx, ISA_MIPS32R2); 3513 check_insn(env, ctx, ISA_MIPS32R2);
3495 - gen_op_mtc0_ebase(); 3514 + tcg_gen_helper_0_0(do_mtc0_ebase);
3496 rn = "EBase"; 3515 rn = "EBase";
3497 break; 3516 break;
3498 default: 3517 default:
@@ -3502,7 +3521,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3502,7 +3521,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3502 case 16: 3521 case 16:
3503 switch (sel) { 3522 switch (sel) {
3504 case 0: 3523 case 0:
3505 - gen_op_mtc0_config0(); 3524 + tcg_gen_helper_0_0(do_mtc0_config0);
3506 rn = "Config"; 3525 rn = "Config";
3507 /* Stop translation as we may have switched the execution mode */ 3526 /* Stop translation as we may have switched the execution mode */
3508 ctx->bstate = BS_STOP; 3527 ctx->bstate = BS_STOP;
@@ -3512,7 +3531,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3512,7 +3531,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3512 rn = "Config1"; 3531 rn = "Config1";
3513 break; 3532 break;
3514 case 2: 3533 case 2:
3515 - gen_op_mtc0_config2(); 3534 + tcg_gen_helper_0_0(do_mtc0_config2);
3516 rn = "Config2"; 3535 rn = "Config2";
3517 /* Stop translation as we may have switched the execution mode */ 3536 /* Stop translation as we may have switched the execution mode */
3518 ctx->bstate = BS_STOP; 3537 ctx->bstate = BS_STOP;
@@ -3549,7 +3568,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3549,7 +3568,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3549 case 18: 3568 case 18:
3550 switch (sel) { 3569 switch (sel) {
3551 case 0 ... 7: 3570 case 0 ... 7:
3552 - gen_op_mtc0_watchlo(sel); 3571 + tcg_gen_helper_0_1i(do_mtc0_watchlo, sel);
3553 rn = "WatchLo"; 3572 rn = "WatchLo";
3554 break; 3573 break;
3555 default: 3574 default:
@@ -3559,7 +3578,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3559,7 +3578,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3559 case 19: 3578 case 19:
3560 switch (sel) { 3579 switch (sel) {
3561 case 0 ... 7: 3580 case 0 ... 7:
3562 - gen_op_mtc0_watchhi(sel); 3581 + tcg_gen_helper_0_1i(do_mtc0_watchhi, sel);
3563 rn = "WatchHi"; 3582 rn = "WatchHi";
3564 break; 3583 break;
3565 default: 3584 default:
@@ -3571,7 +3590,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3571,7 +3590,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3571 case 0: 3590 case 0:
3572 #if defined(TARGET_MIPS64) 3591 #if defined(TARGET_MIPS64)
3573 check_insn(env, ctx, ISA_MIPS3); 3592 check_insn(env, ctx, ISA_MIPS3);
3574 - gen_op_mtc0_xcontext(); 3593 + tcg_gen_helper_0_0(do_mtc0_xcontext);
3575 rn = "XContext"; 3594 rn = "XContext";
3576 break; 3595 break;
3577 #endif 3596 #endif
@@ -3583,7 +3602,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3583,7 +3602,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3583 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 3602 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3584 switch (sel) { 3603 switch (sel) {
3585 case 0: 3604 case 0:
3586 - gen_op_mtc0_framemask(); 3605 + tcg_gen_helper_0_0(do_mtc0_framemask);
3587 rn = "Framemask"; 3606 rn = "Framemask";
3588 break; 3607 break;
3589 default: 3608 default:
@@ -3597,20 +3616,20 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3597,20 +3616,20 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3597 case 23: 3616 case 23:
3598 switch (sel) { 3617 switch (sel) {
3599 case 0: 3618 case 0:
3600 - gen_op_mtc0_debug(); /* EJTAG support */ 3619 + tcg_gen_helper_0_0(do_mtc0_debug); /* EJTAG support */
3601 /* BS_STOP isn't good enough here, hflags may have changed. */ 3620 /* BS_STOP isn't good enough here, hflags may have changed. */
3602 gen_save_pc(ctx->pc + 4); 3621 gen_save_pc(ctx->pc + 4);
3603 ctx->bstate = BS_EXCP; 3622 ctx->bstate = BS_EXCP;
3604 rn = "Debug"; 3623 rn = "Debug";
3605 break; 3624 break;
3606 case 1: 3625 case 1:
3607 -// gen_op_mtc0_tracecontrol(); /* PDtrace support */ 3626 +// tcg_gen_helper_0_0(do_mtc0_tracecontrol); /* PDtrace support */
3608 rn = "TraceControl"; 3627 rn = "TraceControl";
3609 /* Stop translation as we may have switched the execution mode */ 3628 /* Stop translation as we may have switched the execution mode */
3610 ctx->bstate = BS_STOP; 3629 ctx->bstate = BS_STOP;
3611 // break; 3630 // break;
3612 case 2: 3631 case 2:
3613 -// gen_op_mtc0_tracecontrol2(); /* PDtrace support */ 3632 +// tcg_gen_helper_0_0(do_mtc0_tracecontrol2); /* PDtrace support */
3614 rn = "TraceControl2"; 3633 rn = "TraceControl2";
3615 /* Stop translation as we may have switched the execution mode */ 3634 /* Stop translation as we may have switched the execution mode */
3616 ctx->bstate = BS_STOP; 3635 ctx->bstate = BS_STOP;
@@ -3618,13 +3637,13 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3618,13 +3637,13 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3618 case 3: 3637 case 3:
3619 /* Stop translation as we may have switched the execution mode */ 3638 /* Stop translation as we may have switched the execution mode */
3620 ctx->bstate = BS_STOP; 3639 ctx->bstate = BS_STOP;
3621 -// gen_op_mtc0_usertracedata(); /* PDtrace support */ 3640 +// tcg_gen_helper_0_0(do_mtc0_usertracedata); /* PDtrace support */
3622 rn = "UserTraceData"; 3641 rn = "UserTraceData";
3623 /* Stop translation as we may have switched the execution mode */ 3642 /* Stop translation as we may have switched the execution mode */
3624 ctx->bstate = BS_STOP; 3643 ctx->bstate = BS_STOP;
3625 // break; 3644 // break;
3626 case 4: 3645 case 4:
3627 -// gen_op_mtc0_debug(); /* PDtrace support */ 3646 +// tcg_gen_helper_0_0(do_mtc0_debug); /* PDtrace support */
3628 /* Stop translation as we may have switched the execution mode */ 3647 /* Stop translation as we may have switched the execution mode */
3629 ctx->bstate = BS_STOP; 3648 ctx->bstate = BS_STOP;
3630 rn = "TraceBPC"; 3649 rn = "TraceBPC";
@@ -3636,7 +3655,8 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3636,7 +3655,8 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3636 case 24: 3655 case 24:
3637 switch (sel) { 3656 switch (sel) {
3638 case 0: 3657 case 0:
3639 - gen_op_mtc0_depc(); /* EJTAG support */ 3658 + /* EJTAG support */
  3659 + gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_DEPC));
3640 rn = "DEPC"; 3660 rn = "DEPC";
3641 break; 3661 break;
3642 default: 3662 default:
@@ -3646,35 +3666,35 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3646,35 +3666,35 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3646 case 25: 3666 case 25:
3647 switch (sel) { 3667 switch (sel) {
3648 case 0: 3668 case 0:
3649 - gen_op_mtc0_performance0(); 3669 + tcg_gen_helper_0_0(do_mtc0_performance0);
3650 rn = "Performance0"; 3670 rn = "Performance0";
3651 break; 3671 break;
3652 case 1: 3672 case 1:
3653 -// gen_op_mtc0_performance1(); 3673 +// tcg_gen_helper_0_0(do_mtc0_performance1);
3654 rn = "Performance1"; 3674 rn = "Performance1";
3655 // break; 3675 // break;
3656 case 2: 3676 case 2:
3657 -// gen_op_mtc0_performance2(); 3677 +// tcg_gen_helper_0_0(do_mtc0_performance2);
3658 rn = "Performance2"; 3678 rn = "Performance2";
3659 // break; 3679 // break;
3660 case 3: 3680 case 3:
3661 -// gen_op_mtc0_performance3(); 3681 +// tcg_gen_helper_0_0(do_mtc0_performance3);
3662 rn = "Performance3"; 3682 rn = "Performance3";
3663 // break; 3683 // break;
3664 case 4: 3684 case 4:
3665 -// gen_op_mtc0_performance4(); 3685 +// tcg_gen_helper_0_0(do_mtc0_performance4);
3666 rn = "Performance4"; 3686 rn = "Performance4";
3667 // break; 3687 // break;
3668 case 5: 3688 case 5:
3669 -// gen_op_mtc0_performance5(); 3689 +// tcg_gen_helper_0_0(do_mtc0_performance5);
3670 rn = "Performance5"; 3690 rn = "Performance5";
3671 // break; 3691 // break;
3672 case 6: 3692 case 6:
3673 -// gen_op_mtc0_performance6(); 3693 +// tcg_gen_helper_0_0(do_mtc0_performance6);
3674 rn = "Performance6"; 3694 rn = "Performance6";
3675 // break; 3695 // break;
3676 case 7: 3696 case 7:
3677 -// gen_op_mtc0_performance7(); 3697 +// tcg_gen_helper_0_0(do_mtc0_performance7);
3678 rn = "Performance7"; 3698 rn = "Performance7";
3679 // break; 3699 // break;
3680 default: 3700 default:
@@ -3701,14 +3721,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3701,14 +3721,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3701 case 2: 3721 case 2:
3702 case 4: 3722 case 4:
3703 case 6: 3723 case 6:
3704 - gen_op_mtc0_taglo(); 3724 + tcg_gen_helper_0_0(do_mtc0_taglo);
3705 rn = "TagLo"; 3725 rn = "TagLo";
3706 break; 3726 break;
3707 case 1: 3727 case 1:
3708 case 3: 3728 case 3:
3709 case 5: 3729 case 5:
3710 case 7: 3730 case 7:
3711 - gen_op_mtc0_datalo(); 3731 + tcg_gen_helper_0_0(do_mtc0_datalo);
3712 rn = "DataLo"; 3732 rn = "DataLo";
3713 break; 3733 break;
3714 default: 3734 default:
@@ -3721,14 +3741,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3721,14 +3741,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3721 case 2: 3741 case 2:
3722 case 4: 3742 case 4:
3723 case 6: 3743 case 6:
3724 - gen_op_mtc0_taghi(); 3744 + tcg_gen_helper_0_0(do_mtc0_taghi);
3725 rn = "TagHi"; 3745 rn = "TagHi";
3726 break; 3746 break;
3727 case 1: 3747 case 1:
3728 case 3: 3748 case 3:
3729 case 5: 3749 case 5:
3730 case 7: 3750 case 7:
3731 - gen_op_mtc0_datahi(); 3751 + tcg_gen_helper_0_0(do_mtc0_datahi);
3732 rn = "DataHi"; 3752 rn = "DataHi";
3733 break; 3753 break;
3734 default: 3754 default:
@@ -3739,7 +3759,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3739,7 +3759,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3739 case 30: 3759 case 30:
3740 switch (sel) { 3760 switch (sel) {
3741 case 0: 3761 case 0:
3742 - gen_op_mtc0_errorepc(); 3762 + gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_ErrorEPC));
3743 rn = "ErrorEPC"; 3763 rn = "ErrorEPC";
3744 break; 3764 break;
3745 default: 3765 default:
@@ -3749,7 +3769,8 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3749,7 +3769,8 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3749 case 31: 3769 case 31:
3750 switch (sel) { 3770 switch (sel) {
3751 case 0: 3771 case 0:
3752 - gen_op_mtc0_desave(); /* EJTAG support */ 3772 + /* EJTAG support */
  3773 + gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_DESAVE));
3753 rn = "DESAVE"; 3774 rn = "DESAVE";
3754 break; 3775 break;
3755 default: 3776 default:
@@ -3796,17 +3817,17 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3796,17 +3817,17 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3796 break; 3817 break;
3797 case 1: 3818 case 1:
3798 check_insn(env, ctx, ASE_MT); 3819 check_insn(env, ctx, ASE_MT);
3799 - gen_op_mfc0_mvpcontrol(); 3820 + tcg_gen_helper_0_0(do_mfc0_mvpcontrol);
3800 rn = "MVPControl"; 3821 rn = "MVPControl";
3801 break; 3822 break;
3802 case 2: 3823 case 2:
3803 check_insn(env, ctx, ASE_MT); 3824 check_insn(env, ctx, ASE_MT);
3804 - gen_op_mfc0_mvpconf0(); 3825 + tcg_gen_helper_0_0(do_mfc0_mvpconf0);
3805 rn = "MVPConf0"; 3826 rn = "MVPConf0";
3806 break; 3827 break;
3807 case 3: 3828 case 3:
3808 check_insn(env, ctx, ASE_MT); 3829 check_insn(env, ctx, ASE_MT);
3809 - gen_op_mfc0_mvpconf1(); 3830 + tcg_gen_helper_0_0(do_mfc0_mvpconf1);
3810 rn = "MVPConf1"; 3831 rn = "MVPConf1";
3811 break; 3832 break;
3812 default: 3833 default:
@@ -3816,7 +3837,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3816,7 +3837,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3816 case 1: 3837 case 1:
3817 switch (sel) { 3838 switch (sel) {
3818 case 0: 3839 case 0:
3819 - gen_op_mfc0_random(); 3840 + tcg_gen_helper_0_0(do_mfc0_random);
3820 rn = "Random"; 3841 rn = "Random";
3821 break; 3842 break;
3822 case 1: 3843 case 1:
@@ -3866,37 +3887,37 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3866,37 +3887,37 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3866 break; 3887 break;
3867 case 1: 3888 case 1:
3868 check_insn(env, ctx, ASE_MT); 3889 check_insn(env, ctx, ASE_MT);
3869 - gen_op_mfc0_tcstatus(); 3890 + tcg_gen_helper_0_0(do_mfc0_tcstatus);
3870 rn = "TCStatus"; 3891 rn = "TCStatus";
3871 break; 3892 break;
3872 case 2: 3893 case 2:
3873 check_insn(env, ctx, ASE_MT); 3894 check_insn(env, ctx, ASE_MT);
3874 - gen_op_mfc0_tcbind(); 3895 + tcg_gen_helper_0_0(do_mfc0_tcbind);
3875 rn = "TCBind"; 3896 rn = "TCBind";
3876 break; 3897 break;
3877 case 3: 3898 case 3:
3878 check_insn(env, ctx, ASE_MT); 3899 check_insn(env, ctx, ASE_MT);
3879 - gen_op_dmfc0_tcrestart(); 3900 + tcg_gen_helper_0_0(do_dmfc0_tcrestart);
3880 rn = "TCRestart"; 3901 rn = "TCRestart";
3881 break; 3902 break;
3882 case 4: 3903 case 4:
3883 check_insn(env, ctx, ASE_MT); 3904 check_insn(env, ctx, ASE_MT);
3884 - gen_op_dmfc0_tchalt(); 3905 + tcg_gen_helper_0_0(do_dmfc0_tchalt);
3885 rn = "TCHalt"; 3906 rn = "TCHalt";
3886 break; 3907 break;
3887 case 5: 3908 case 5:
3888 check_insn(env, ctx, ASE_MT); 3909 check_insn(env, ctx, ASE_MT);
3889 - gen_op_dmfc0_tccontext(); 3910 + tcg_gen_helper_0_0(do_dmfc0_tccontext);
3890 rn = "TCContext"; 3911 rn = "TCContext";
3891 break; 3912 break;
3892 case 6: 3913 case 6:
3893 check_insn(env, ctx, ASE_MT); 3914 check_insn(env, ctx, ASE_MT);
3894 - gen_op_dmfc0_tcschedule(); 3915 + tcg_gen_helper_0_0(do_dmfc0_tcschedule);
3895 rn = "TCSchedule"; 3916 rn = "TCSchedule";
3896 break; 3917 break;
3897 case 7: 3918 case 7:
3898 check_insn(env, ctx, ASE_MT); 3919 check_insn(env, ctx, ASE_MT);
3899 - gen_op_dmfc0_tcschefback(); 3920 + tcg_gen_helper_0_0(do_dmfc0_tcschefback);
3900 rn = "TCScheFBack"; 3921 rn = "TCScheFBack";
3901 break; 3922 break;
3902 default: 3923 default:
@@ -3920,7 +3941,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -3920,7 +3941,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3920 rn = "Context"; 3941 rn = "Context";
3921 break; 3942 break;
3922 case 1: 3943 case 1:
3923 -// gen_op_dmfc0_contextconfig(); /* SmartMIPS ASE */ 3944 +// tcg_gen_helper_0_0(do_dmfc0_contextconfig); /* SmartMIPS ASE */
3924 rn = "ContextConfig"; 3945 rn = "ContextConfig";
3925 // break; 3946 // break;
3926 default: 3947 default:
@@ -4001,7 +4022,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4001,7 +4022,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4001 case 9: 4022 case 9:
4002 switch (sel) { 4023 switch (sel) {
4003 case 0: 4024 case 0:
4004 - gen_op_mfc0_count(); 4025 + tcg_gen_helper_0_0(do_mfc0_count);
4005 rn = "Count"; 4026 rn = "Count";
4006 break; 4027 break;
4007 /* 6,7 are implementation dependent */ 4028 /* 6,7 are implementation dependent */
@@ -4124,7 +4145,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4124,7 +4145,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4124 case 17: 4145 case 17:
4125 switch (sel) { 4146 switch (sel) {
4126 case 0: 4147 case 0:
4127 - gen_op_dmfc0_lladdr(); 4148 + tcg_gen_helper_0_0(do_dmfc0_lladdr);
4128 rn = "LLAddr"; 4149 rn = "LLAddr";
4129 break; 4150 break;
4130 default: 4151 default:
@@ -4134,7 +4155,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4134,7 +4155,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4134 case 18: 4155 case 18:
4135 switch (sel) { 4156 switch (sel) {
4136 case 0 ... 7: 4157 case 0 ... 7:
4137 - gen_op_dmfc0_watchlo(sel); 4158 + tcg_gen_helper_0_1i(do_dmfc0_watchlo, sel);
4138 rn = "WatchLo"; 4159 rn = "WatchLo";
4139 break; 4160 break;
4140 default: 4161 default:
@@ -4144,7 +4165,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4144,7 +4165,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4144 case 19: 4165 case 19:
4145 switch (sel) { 4166 switch (sel) {
4146 case 0 ... 7: 4167 case 0 ... 7:
4147 - gen_op_mfc0_watchhi(sel); 4168 + tcg_gen_helper_0_1i(do_mfc0_watchhi, sel);
4148 rn = "WatchHi"; 4169 rn = "WatchHi";
4149 break; 4170 break;
4150 default: 4171 default:
@@ -4180,23 +4201,23 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4180,23 +4201,23 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4180 case 23: 4201 case 23:
4181 switch (sel) { 4202 switch (sel) {
4182 case 0: 4203 case 0:
4183 - gen_op_mfc0_debug(); /* EJTAG support */ 4204 + tcg_gen_helper_0_0(do_mfc0_debug); /* EJTAG support */
4184 rn = "Debug"; 4205 rn = "Debug";
4185 break; 4206 break;
4186 case 1: 4207 case 1:
4187 -// gen_op_dmfc0_tracecontrol(); /* PDtrace support */ 4208 +// tcg_gen_helper_0_0(do_dmfc0_tracecontrol); /* PDtrace support */
4188 rn = "TraceControl"; 4209 rn = "TraceControl";
4189 // break; 4210 // break;
4190 case 2: 4211 case 2:
4191 -// gen_op_dmfc0_tracecontrol2(); /* PDtrace support */ 4212 +// tcg_gen_helper_0_0(do_dmfc0_tracecontrol2); /* PDtrace support */
4192 rn = "TraceControl2"; 4213 rn = "TraceControl2";
4193 // break; 4214 // break;
4194 case 3: 4215 case 3:
4195 -// gen_op_dmfc0_usertracedata(); /* PDtrace support */ 4216 +// tcg_gen_helper_0_0(do_dmfc0_usertracedata); /* PDtrace support */
4196 rn = "UserTraceData"; 4217 rn = "UserTraceData";
4197 // break; 4218 // break;
4198 case 4: 4219 case 4:
4199 -// gen_op_dmfc0_debug(); /* PDtrace support */ 4220 +// tcg_gen_helper_0_0(do_dmfc0_debug); /* PDtrace support */
4200 rn = "TraceBPC"; 4221 rn = "TraceBPC";
4201 // break; 4222 // break;
4202 default: 4223 default:
@@ -4221,31 +4242,31 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4221,31 +4242,31 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4221 rn = "Performance0"; 4242 rn = "Performance0";
4222 break; 4243 break;
4223 case 1: 4244 case 1:
4224 -// gen_op_dmfc0_performance1(); 4245 +// tcg_gen_helper_0_0(do_dmfc0_performance1);
4225 rn = "Performance1"; 4246 rn = "Performance1";
4226 // break; 4247 // break;
4227 case 2: 4248 case 2:
4228 -// gen_op_dmfc0_performance2(); 4249 +// tcg_gen_helper_0_0(do_dmfc0_performance2);
4229 rn = "Performance2"; 4250 rn = "Performance2";
4230 // break; 4251 // break;
4231 case 3: 4252 case 3:
4232 -// gen_op_dmfc0_performance3(); 4253 +// tcg_gen_helper_0_0(do_dmfc0_performance3);
4233 rn = "Performance3"; 4254 rn = "Performance3";
4234 // break; 4255 // break;
4235 case 4: 4256 case 4:
4236 -// gen_op_dmfc0_performance4(); 4257 +// tcg_gen_helper_0_0(do_dmfc0_performance4);
4237 rn = "Performance4"; 4258 rn = "Performance4";
4238 // break; 4259 // break;
4239 case 5: 4260 case 5:
4240 -// gen_op_dmfc0_performance5(); 4261 +// tcg_gen_helper_0_0(do_dmfc0_performance5);
4241 rn = "Performance5"; 4262 rn = "Performance5";
4242 // break; 4263 // break;
4243 case 6: 4264 case 6:
4244 -// gen_op_dmfc0_performance6(); 4265 +// tcg_gen_helper_0_0(do_dmfc0_performance6);
4245 rn = "Performance6"; 4266 rn = "Performance6";
4246 // break; 4267 // break;
4247 case 7: 4268 case 7:
4248 -// gen_op_dmfc0_performance7(); 4269 +// tcg_gen_helper_0_0(do_dmfc0_performance7);
4249 rn = "Performance7"; 4270 rn = "Performance7";
4250 // break; 4271 // break;
4251 default: 4272 default:
@@ -4358,12 +4379,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4358,12 +4379,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4358 case 0: 4379 case 0:
4359 switch (sel) { 4380 switch (sel) {
4360 case 0: 4381 case 0:
4361 - gen_op_mtc0_index(); 4382 + tcg_gen_helper_0_0(do_mtc0_index);
4362 rn = "Index"; 4383 rn = "Index";
4363 break; 4384 break;
4364 case 1: 4385 case 1:
4365 check_insn(env, ctx, ASE_MT); 4386 check_insn(env, ctx, ASE_MT);
4366 - gen_op_mtc0_mvpcontrol(); 4387 + tcg_gen_helper_0_0(do_mtc0_mvpcontrol);
4367 rn = "MVPControl"; 4388 rn = "MVPControl";
4368 break; 4389 break;
4369 case 2: 4390 case 2:
@@ -4388,37 +4409,37 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4388,37 +4409,37 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4388 break; 4409 break;
4389 case 1: 4410 case 1:
4390 check_insn(env, ctx, ASE_MT); 4411 check_insn(env, ctx, ASE_MT);
4391 - gen_op_mtc0_vpecontrol(); 4412 + tcg_gen_helper_0_0(do_mtc0_vpecontrol);
4392 rn = "VPEControl"; 4413 rn = "VPEControl";
4393 break; 4414 break;
4394 case 2: 4415 case 2:
4395 check_insn(env, ctx, ASE_MT); 4416 check_insn(env, ctx, ASE_MT);
4396 - gen_op_mtc0_vpeconf0(); 4417 + tcg_gen_helper_0_0(do_mtc0_vpeconf0);
4397 rn = "VPEConf0"; 4418 rn = "VPEConf0";
4398 break; 4419 break;
4399 case 3: 4420 case 3:
4400 check_insn(env, ctx, ASE_MT); 4421 check_insn(env, ctx, ASE_MT);
4401 - gen_op_mtc0_vpeconf1(); 4422 + tcg_gen_helper_0_0(do_mtc0_vpeconf1);
4402 rn = "VPEConf1"; 4423 rn = "VPEConf1";
4403 break; 4424 break;
4404 case 4: 4425 case 4:
4405 check_insn(env, ctx, ASE_MT); 4426 check_insn(env, ctx, ASE_MT);
4406 - gen_op_mtc0_yqmask(); 4427 + tcg_gen_helper_0_0(do_mtc0_yqmask);
4407 rn = "YQMask"; 4428 rn = "YQMask";
4408 break; 4429 break;
4409 case 5: 4430 case 5:
4410 check_insn(env, ctx, ASE_MT); 4431 check_insn(env, ctx, ASE_MT);
4411 - gen_op_mtc0_vpeschedule(); 4432 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPESchedule));
4412 rn = "VPESchedule"; 4433 rn = "VPESchedule";
4413 break; 4434 break;
4414 case 6: 4435 case 6:
4415 check_insn(env, ctx, ASE_MT); 4436 check_insn(env, ctx, ASE_MT);
4416 - gen_op_mtc0_vpeschefback(); 4437 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4417 rn = "VPEScheFBack"; 4438 rn = "VPEScheFBack";
4418 break; 4439 break;
4419 case 7: 4440 case 7:
4420 check_insn(env, ctx, ASE_MT); 4441 check_insn(env, ctx, ASE_MT);
4421 - gen_op_mtc0_vpeopt(); 4442 + tcg_gen_helper_0_0(do_mtc0_vpeopt);
4422 rn = "VPEOpt"; 4443 rn = "VPEOpt";
4423 break; 4444 break;
4424 default: 4445 default:
@@ -4428,42 +4449,42 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4428,42 +4449,42 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4428 case 2: 4449 case 2:
4429 switch (sel) { 4450 switch (sel) {
4430 case 0: 4451 case 0:
4431 - gen_op_mtc0_entrylo0(); 4452 + tcg_gen_helper_0_0(do_mtc0_entrylo0);
4432 rn = "EntryLo0"; 4453 rn = "EntryLo0";
4433 break; 4454 break;
4434 case 1: 4455 case 1:
4435 check_insn(env, ctx, ASE_MT); 4456 check_insn(env, ctx, ASE_MT);
4436 - gen_op_mtc0_tcstatus(); 4457 + tcg_gen_helper_0_0(do_mtc0_tcstatus);
4437 rn = "TCStatus"; 4458 rn = "TCStatus";
4438 break; 4459 break;
4439 case 2: 4460 case 2:
4440 check_insn(env, ctx, ASE_MT); 4461 check_insn(env, ctx, ASE_MT);
4441 - gen_op_mtc0_tcbind(); 4462 + tcg_gen_helper_0_0(do_mtc0_tcbind);
4442 rn = "TCBind"; 4463 rn = "TCBind";
4443 break; 4464 break;
4444 case 3: 4465 case 3:
4445 check_insn(env, ctx, ASE_MT); 4466 check_insn(env, ctx, ASE_MT);
4446 - gen_op_mtc0_tcrestart(); 4467 + tcg_gen_helper_0_0(do_mtc0_tcrestart);
4447 rn = "TCRestart"; 4468 rn = "TCRestart";
4448 break; 4469 break;
4449 case 4: 4470 case 4:
4450 check_insn(env, ctx, ASE_MT); 4471 check_insn(env, ctx, ASE_MT);
4451 - gen_op_mtc0_tchalt(); 4472 + tcg_gen_helper_0_0(do_mtc0_tchalt);
4452 rn = "TCHalt"; 4473 rn = "TCHalt";
4453 break; 4474 break;
4454 case 5: 4475 case 5:
4455 check_insn(env, ctx, ASE_MT); 4476 check_insn(env, ctx, ASE_MT);
4456 - gen_op_mtc0_tccontext(); 4477 + tcg_gen_helper_0_0(do_mtc0_tccontext);
4457 rn = "TCContext"; 4478 rn = "TCContext";
4458 break; 4479 break;
4459 case 6: 4480 case 6:
4460 check_insn(env, ctx, ASE_MT); 4481 check_insn(env, ctx, ASE_MT);
4461 - gen_op_mtc0_tcschedule(); 4482 + tcg_gen_helper_0_0(do_mtc0_tcschedule);
4462 rn = "TCSchedule"; 4483 rn = "TCSchedule";
4463 break; 4484 break;
4464 case 7: 4485 case 7:
4465 check_insn(env, ctx, ASE_MT); 4486 check_insn(env, ctx, ASE_MT);
4466 - gen_op_mtc0_tcschefback(); 4487 + tcg_gen_helper_0_0(do_mtc0_tcschefback);
4467 rn = "TCScheFBack"; 4488 rn = "TCScheFBack";
4468 break; 4489 break;
4469 default: 4490 default:
@@ -4473,7 +4494,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4473,7 +4494,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4473 case 3: 4494 case 3:
4474 switch (sel) { 4495 switch (sel) {
4475 case 0: 4496 case 0:
4476 - gen_op_mtc0_entrylo1(); 4497 + tcg_gen_helper_0_0(do_mtc0_entrylo1);
4477 rn = "EntryLo1"; 4498 rn = "EntryLo1";
4478 break; 4499 break;
4479 default: 4500 default:
@@ -4483,11 +4504,11 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4483,11 +4504,11 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4483 case 4: 4504 case 4:
4484 switch (sel) { 4505 switch (sel) {
4485 case 0: 4506 case 0:
4486 - gen_op_mtc0_context(); 4507 + tcg_gen_helper_0_0(do_mtc0_context);
4487 rn = "Context"; 4508 rn = "Context";
4488 break; 4509 break;
4489 case 1: 4510 case 1:
4490 -// gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */ 4511 +// tcg_gen_helper_0_0(do_mtc0_contextconfig); /* SmartMIPS ASE */
4491 rn = "ContextConfig"; 4512 rn = "ContextConfig";
4492 // break; 4513 // break;
4493 default: 4514 default:
@@ -4497,12 +4518,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4497,12 +4518,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4497 case 5: 4518 case 5:
4498 switch (sel) { 4519 switch (sel) {
4499 case 0: 4520 case 0:
4500 - gen_op_mtc0_pagemask(); 4521 + tcg_gen_helper_0_0(do_mtc0_pagemask);
4501 rn = "PageMask"; 4522 rn = "PageMask";
4502 break; 4523 break;
4503 case 1: 4524 case 1:
4504 check_insn(env, ctx, ISA_MIPS32R2); 4525 check_insn(env, ctx, ISA_MIPS32R2);
4505 - gen_op_mtc0_pagegrain(); 4526 + tcg_gen_helper_0_0(do_mtc0_pagegrain);
4506 rn = "PageGrain"; 4527 rn = "PageGrain";
4507 break; 4528 break;
4508 default: 4529 default:
@@ -4512,32 +4533,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4512,32 +4533,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4512 case 6: 4533 case 6:
4513 switch (sel) { 4534 switch (sel) {
4514 case 0: 4535 case 0:
4515 - gen_op_mtc0_wired(); 4536 + tcg_gen_helper_0_0(do_mtc0_wired);
4516 rn = "Wired"; 4537 rn = "Wired";
4517 break; 4538 break;
4518 case 1: 4539 case 1:
4519 check_insn(env, ctx, ISA_MIPS32R2); 4540 check_insn(env, ctx, ISA_MIPS32R2);
4520 - gen_op_mtc0_srsconf0(); 4541 + tcg_gen_helper_0_0(do_mtc0_srsconf0);
4521 rn = "SRSConf0"; 4542 rn = "SRSConf0";
4522 break; 4543 break;
4523 case 2: 4544 case 2:
4524 check_insn(env, ctx, ISA_MIPS32R2); 4545 check_insn(env, ctx, ISA_MIPS32R2);
4525 - gen_op_mtc0_srsconf1(); 4546 + tcg_gen_helper_0_0(do_mtc0_srsconf1);
4526 rn = "SRSConf1"; 4547 rn = "SRSConf1";
4527 break; 4548 break;
4528 case 3: 4549 case 3:
4529 check_insn(env, ctx, ISA_MIPS32R2); 4550 check_insn(env, ctx, ISA_MIPS32R2);
4530 - gen_op_mtc0_srsconf2(); 4551 + tcg_gen_helper_0_0(do_mtc0_srsconf2);
4531 rn = "SRSConf2"; 4552 rn = "SRSConf2";
4532 break; 4553 break;
4533 case 4: 4554 case 4:
4534 check_insn(env, ctx, ISA_MIPS32R2); 4555 check_insn(env, ctx, ISA_MIPS32R2);
4535 - gen_op_mtc0_srsconf3(); 4556 + tcg_gen_helper_0_0(do_mtc0_srsconf3);
4536 rn = "SRSConf3"; 4557 rn = "SRSConf3";
4537 break; 4558 break;
4538 case 5: 4559 case 5:
4539 check_insn(env, ctx, ISA_MIPS32R2); 4560 check_insn(env, ctx, ISA_MIPS32R2);
4540 - gen_op_mtc0_srsconf4(); 4561 + tcg_gen_helper_0_0(do_mtc0_srsconf4);
4541 rn = "SRSConf4"; 4562 rn = "SRSConf4";
4542 break; 4563 break;
4543 default: 4564 default:
@@ -4548,7 +4569,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4548,7 +4569,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4548 switch (sel) { 4569 switch (sel) {
4549 case 0: 4570 case 0:
4550 check_insn(env, ctx, ISA_MIPS32R2); 4571 check_insn(env, ctx, ISA_MIPS32R2);
4551 - gen_op_mtc0_hwrena(); 4572 + tcg_gen_helper_0_0(do_mtc0_hwrena);
4552 rn = "HWREna"; 4573 rn = "HWREna";
4553 break; 4574 break;
4554 default: 4575 default:
@@ -4562,7 +4583,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4562,7 +4583,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4562 case 9: 4583 case 9:
4563 switch (sel) { 4584 switch (sel) {
4564 case 0: 4585 case 0:
4565 - gen_op_mtc0_count(); 4586 + tcg_gen_helper_0_0(do_mtc0_count);
4566 rn = "Count"; 4587 rn = "Count";
4567 break; 4588 break;
4568 /* 6,7 are implementation dependent */ 4589 /* 6,7 are implementation dependent */
@@ -4575,7 +4596,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4575,7 +4596,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4575 case 10: 4596 case 10:
4576 switch (sel) { 4597 switch (sel) {
4577 case 0: 4598 case 0:
4578 - gen_op_mtc0_entryhi(); 4599 + tcg_gen_helper_0_0(do_mtc0_entryhi);
4579 rn = "EntryHi"; 4600 rn = "EntryHi";
4580 break; 4601 break;
4581 default: 4602 default:
@@ -4585,7 +4606,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4585,7 +4606,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4585 case 11: 4606 case 11:
4586 switch (sel) { 4607 switch (sel) {
4587 case 0: 4608 case 0:
4588 - gen_op_mtc0_compare(); 4609 + tcg_gen_helper_0_0(do_mtc0_compare);
4589 rn = "Compare"; 4610 rn = "Compare";
4590 break; 4611 break;
4591 /* 6,7 are implementation dependent */ 4612 /* 6,7 are implementation dependent */
@@ -4598,7 +4619,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4598,7 +4619,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4598 case 12: 4619 case 12:
4599 switch (sel) { 4620 switch (sel) {
4600 case 0: 4621 case 0:
4601 - gen_op_mtc0_status(); 4622 + tcg_gen_helper_0_0(do_mtc0_status);
4602 /* BS_STOP isn't good enough here, hflags may have changed. */ 4623 /* BS_STOP isn't good enough here, hflags may have changed. */
4603 gen_save_pc(ctx->pc + 4); 4624 gen_save_pc(ctx->pc + 4);
4604 ctx->bstate = BS_EXCP; 4625 ctx->bstate = BS_EXCP;
@@ -4606,21 +4627,21 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4606,21 +4627,21 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4606 break; 4627 break;
4607 case 1: 4628 case 1:
4608 check_insn(env, ctx, ISA_MIPS32R2); 4629 check_insn(env, ctx, ISA_MIPS32R2);
4609 - gen_op_mtc0_intctl(); 4630 + tcg_gen_helper_0_0(do_mtc0_intctl);
4610 /* Stop translation as we may have switched the execution mode */ 4631 /* Stop translation as we may have switched the execution mode */
4611 ctx->bstate = BS_STOP; 4632 ctx->bstate = BS_STOP;
4612 rn = "IntCtl"; 4633 rn = "IntCtl";
4613 break; 4634 break;
4614 case 2: 4635 case 2:
4615 check_insn(env, ctx, ISA_MIPS32R2); 4636 check_insn(env, ctx, ISA_MIPS32R2);
4616 - gen_op_mtc0_srsctl(); 4637 + tcg_gen_helper_0_0(do_mtc0_srsctl);
4617 /* Stop translation as we may have switched the execution mode */ 4638 /* Stop translation as we may have switched the execution mode */
4618 ctx->bstate = BS_STOP; 4639 ctx->bstate = BS_STOP;
4619 rn = "SRSCtl"; 4640 rn = "SRSCtl";
4620 break; 4641 break;
4621 case 3: 4642 case 3:
4622 check_insn(env, ctx, ISA_MIPS32R2); 4643 check_insn(env, ctx, ISA_MIPS32R2);
4623 - gen_op_mtc0_srsmap(); 4644 + gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_SRSMap));
4624 /* Stop translation as we may have switched the execution mode */ 4645 /* Stop translation as we may have switched the execution mode */
4625 ctx->bstate = BS_STOP; 4646 ctx->bstate = BS_STOP;
4626 rn = "SRSMap"; 4647 rn = "SRSMap";
@@ -4632,7 +4653,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4632,7 +4653,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4632 case 13: 4653 case 13:
4633 switch (sel) { 4654 switch (sel) {
4634 case 0: 4655 case 0:
4635 - gen_op_mtc0_cause(); 4656 + tcg_gen_helper_0_0(do_mtc0_cause);
4636 rn = "Cause"; 4657 rn = "Cause";
4637 break; 4658 break;
4638 default: 4659 default:
@@ -4644,7 +4665,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4644,7 +4665,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4644 case 14: 4665 case 14:
4645 switch (sel) { 4666 switch (sel) {
4646 case 0: 4667 case 0:
4647 - gen_op_mtc0_epc(); 4668 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EPC));
4648 rn = "EPC"; 4669 rn = "EPC";
4649 break; 4670 break;
4650 default: 4671 default:
@@ -4659,7 +4680,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4659,7 +4680,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4659 break; 4680 break;
4660 case 1: 4681 case 1:
4661 check_insn(env, ctx, ISA_MIPS32R2); 4682 check_insn(env, ctx, ISA_MIPS32R2);
4662 - gen_op_mtc0_ebase(); 4683 + tcg_gen_helper_0_0(do_mtc0_ebase);
4663 rn = "EBase"; 4684 rn = "EBase";
4664 break; 4685 break;
4665 default: 4686 default:
@@ -4669,7 +4690,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4669,7 +4690,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4669 case 16: 4690 case 16:
4670 switch (sel) { 4691 switch (sel) {
4671 case 0: 4692 case 0:
4672 - gen_op_mtc0_config0(); 4693 + tcg_gen_helper_0_0(do_mtc0_config0);
4673 rn = "Config"; 4694 rn = "Config";
4674 /* Stop translation as we may have switched the execution mode */ 4695 /* Stop translation as we may have switched the execution mode */
4675 ctx->bstate = BS_STOP; 4696 ctx->bstate = BS_STOP;
@@ -4679,7 +4700,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4679,7 +4700,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4679 rn = "Config1"; 4700 rn = "Config1";
4680 break; 4701 break;
4681 case 2: 4702 case 2:
4682 - gen_op_mtc0_config2(); 4703 + tcg_gen_helper_0_0(do_mtc0_config2);
4683 rn = "Config2"; 4704 rn = "Config2";
4684 /* Stop translation as we may have switched the execution mode */ 4705 /* Stop translation as we may have switched the execution mode */
4685 ctx->bstate = BS_STOP; 4706 ctx->bstate = BS_STOP;
@@ -4707,7 +4728,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4707,7 +4728,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4707 case 18: 4728 case 18:
4708 switch (sel) { 4729 switch (sel) {
4709 case 0 ... 7: 4730 case 0 ... 7:
4710 - gen_op_mtc0_watchlo(sel); 4731 + tcg_gen_helper_0_1i(do_mtc0_watchlo, sel);
4711 rn = "WatchLo"; 4732 rn = "WatchLo";
4712 break; 4733 break;
4713 default: 4734 default:
@@ -4717,7 +4738,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4717,7 +4738,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4717 case 19: 4738 case 19:
4718 switch (sel) { 4739 switch (sel) {
4719 case 0 ... 7: 4740 case 0 ... 7:
4720 - gen_op_mtc0_watchhi(sel); 4741 + tcg_gen_helper_0_1i(do_mtc0_watchhi, sel);
4721 rn = "WatchHi"; 4742 rn = "WatchHi";
4722 break; 4743 break;
4723 default: 4744 default:
@@ -4728,7 +4749,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4728,7 +4749,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4728 switch (sel) { 4749 switch (sel) {
4729 case 0: 4750 case 0:
4730 check_insn(env, ctx, ISA_MIPS3); 4751 check_insn(env, ctx, ISA_MIPS3);
4731 - gen_op_mtc0_xcontext(); 4752 + tcg_gen_helper_0_0(do_mtc0_xcontext);
4732 rn = "XContext"; 4753 rn = "XContext";
4733 break; 4754 break;
4734 default: 4755 default:
@@ -4739,7 +4760,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4739,7 +4760,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4739 /* Officially reserved, but sel 0 is used for R1x000 framemask */ 4760 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4740 switch (sel) { 4761 switch (sel) {
4741 case 0: 4762 case 0:
4742 - gen_op_mtc0_framemask(); 4763 + tcg_gen_helper_0_0(do_mtc0_framemask);
4743 rn = "Framemask"; 4764 rn = "Framemask";
4744 break; 4765 break;
4745 default: 4766 default:
@@ -4753,32 +4774,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4753,32 +4774,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4753 case 23: 4774 case 23:
4754 switch (sel) { 4775 switch (sel) {
4755 case 0: 4776 case 0:
4756 - gen_op_mtc0_debug(); /* EJTAG support */ 4777 + tcg_gen_helper_0_0(do_mtc0_debug); /* EJTAG support */
4757 /* BS_STOP isn't good enough here, hflags may have changed. */ 4778 /* BS_STOP isn't good enough here, hflags may have changed. */
4758 gen_save_pc(ctx->pc + 4); 4779 gen_save_pc(ctx->pc + 4);
4759 ctx->bstate = BS_EXCP; 4780 ctx->bstate = BS_EXCP;
4760 rn = "Debug"; 4781 rn = "Debug";
4761 break; 4782 break;
4762 case 1: 4783 case 1:
4763 -// gen_op_mtc0_tracecontrol(); /* PDtrace support */ 4784 +// tcg_gen_helper_0_0(do_mtc0_tracecontrol); /* PDtrace support */
4764 /* Stop translation as we may have switched the execution mode */ 4785 /* Stop translation as we may have switched the execution mode */
4765 ctx->bstate = BS_STOP; 4786 ctx->bstate = BS_STOP;
4766 rn = "TraceControl"; 4787 rn = "TraceControl";
4767 // break; 4788 // break;
4768 case 2: 4789 case 2:
4769 -// gen_op_mtc0_tracecontrol2(); /* PDtrace support */ 4790 +// tcg_gen_helper_0_0(do_mtc0_tracecontrol2); /* PDtrace support */
4770 /* Stop translation as we may have switched the execution mode */ 4791 /* Stop translation as we may have switched the execution mode */
4771 ctx->bstate = BS_STOP; 4792 ctx->bstate = BS_STOP;
4772 rn = "TraceControl2"; 4793 rn = "TraceControl2";
4773 // break; 4794 // break;
4774 case 3: 4795 case 3:
4775 -// gen_op_mtc0_usertracedata(); /* PDtrace support */ 4796 +// tcg_gen_helper_0_0(do_mtc0_usertracedata); /* PDtrace support */
4776 /* Stop translation as we may have switched the execution mode */ 4797 /* Stop translation as we may have switched the execution mode */
4777 ctx->bstate = BS_STOP; 4798 ctx->bstate = BS_STOP;
4778 rn = "UserTraceData"; 4799 rn = "UserTraceData";
4779 // break; 4800 // break;
4780 case 4: 4801 case 4:
4781 -// gen_op_mtc0_debug(); /* PDtrace support */ 4802 +// tcg_gen_helper_0_0(do_mtc0_debug); /* PDtrace support */
4782 /* Stop translation as we may have switched the execution mode */ 4803 /* Stop translation as we may have switched the execution mode */
4783 ctx->bstate = BS_STOP; 4804 ctx->bstate = BS_STOP;
4784 rn = "TraceBPC"; 4805 rn = "TraceBPC";
@@ -4790,7 +4811,8 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4790,7 +4811,8 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4790 case 24: 4811 case 24:
4791 switch (sel) { 4812 switch (sel) {
4792 case 0: 4813 case 0:
4793 - gen_op_mtc0_depc(); /* EJTAG support */ 4814 + /* EJTAG support */
  4815 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_DEPC));
4794 rn = "DEPC"; 4816 rn = "DEPC";
4795 break; 4817 break;
4796 default: 4818 default:
@@ -4800,35 +4822,35 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4800,35 +4822,35 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4800 case 25: 4822 case 25:
4801 switch (sel) { 4823 switch (sel) {
4802 case 0: 4824 case 0:
4803 - gen_op_mtc0_performance0(); 4825 + tcg_gen_helper_0_0(do_mtc0_performance0);
4804 rn = "Performance0"; 4826 rn = "Performance0";
4805 break; 4827 break;
4806 case 1: 4828 case 1:
4807 -// gen_op_mtc0_performance1(); 4829 +// tcg_gen_helper_0_0(do_mtc0_performance1);
4808 rn = "Performance1"; 4830 rn = "Performance1";
4809 // break; 4831 // break;
4810 case 2: 4832 case 2:
4811 -// gen_op_mtc0_performance2(); 4833 +// tcg_gen_helper_0_0(do_mtc0_performance2);
4812 rn = "Performance2"; 4834 rn = "Performance2";
4813 // break; 4835 // break;
4814 case 3: 4836 case 3:
4815 -// gen_op_mtc0_performance3(); 4837 +// tcg_gen_helper_0_0(do_mtc0_performance3);
4816 rn = "Performance3"; 4838 rn = "Performance3";
4817 // break; 4839 // break;
4818 case 4: 4840 case 4:
4819 -// gen_op_mtc0_performance4(); 4841 +// tcg_gen_helper_0_0(do_mtc0_performance4);
4820 rn = "Performance4"; 4842 rn = "Performance4";
4821 // break; 4843 // break;
4822 case 5: 4844 case 5:
4823 -// gen_op_mtc0_performance5(); 4845 +// tcg_gen_helper_0_0(do_mtc0_performance5);
4824 rn = "Performance5"; 4846 rn = "Performance5";
4825 // break; 4847 // break;
4826 case 6: 4848 case 6:
4827 -// gen_op_mtc0_performance6(); 4849 +// tcg_gen_helper_0_0(do_mtc0_performance6);
4828 rn = "Performance6"; 4850 rn = "Performance6";
4829 // break; 4851 // break;
4830 case 7: 4852 case 7:
4831 -// gen_op_mtc0_performance7(); 4853 +// tcg_gen_helper_0_0(do_mtc0_performance7);
4832 rn = "Performance7"; 4854 rn = "Performance7";
4833 // break; 4855 // break;
4834 default: 4856 default:
@@ -4855,14 +4877,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4855,14 +4877,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4855 case 2: 4877 case 2:
4856 case 4: 4878 case 4:
4857 case 6: 4879 case 6:
4858 - gen_op_mtc0_taglo(); 4880 + tcg_gen_helper_0_0(do_mtc0_taglo);
4859 rn = "TagLo"; 4881 rn = "TagLo";
4860 break; 4882 break;
4861 case 1: 4883 case 1:
4862 case 3: 4884 case 3:
4863 case 5: 4885 case 5:
4864 case 7: 4886 case 7:
4865 - gen_op_mtc0_datalo(); 4887 + tcg_gen_helper_0_0(do_mtc0_datalo);
4866 rn = "DataLo"; 4888 rn = "DataLo";
4867 break; 4889 break;
4868 default: 4890 default:
@@ -4875,14 +4897,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4875,14 +4897,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4875 case 2: 4897 case 2:
4876 case 4: 4898 case 4:
4877 case 6: 4899 case 6:
4878 - gen_op_mtc0_taghi(); 4900 + tcg_gen_helper_0_0(do_mtc0_taghi);
4879 rn = "TagHi"; 4901 rn = "TagHi";
4880 break; 4902 break;
4881 case 1: 4903 case 1:
4882 case 3: 4904 case 3:
4883 case 5: 4905 case 5:
4884 case 7: 4906 case 7:
4885 - gen_op_mtc0_datahi(); 4907 + tcg_gen_helper_0_0(do_mtc0_datahi);
4886 rn = "DataHi"; 4908 rn = "DataHi";
4887 break; 4909 break;
4888 default: 4910 default:
@@ -4893,7 +4915,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4893,7 +4915,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4893 case 30: 4915 case 30:
4894 switch (sel) { 4916 switch (sel) {
4895 case 0: 4917 case 0:
4896 - gen_op_mtc0_errorepc(); 4918 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_ErrorEPC));
4897 rn = "ErrorEPC"; 4919 rn = "ErrorEPC";
4898 break; 4920 break;
4899 default: 4921 default:
@@ -4903,7 +4925,8 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) @@ -4903,7 +4925,8 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4903 case 31: 4925 case 31:
4904 switch (sel) { 4926 switch (sel) {
4905 case 0: 4927 case 0:
4906 - gen_op_mtc0_desave(); /* EJTAG support */ 4928 + /* EJTAG support */
  4929 + gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_DESAVE));
4907 rn = "DESAVE"; 4930 rn = "DESAVE";
4908 break; 4931 break;
4909 default: 4932 default:
@@ -4951,25 +4974,25 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, @@ -4951,25 +4974,25 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
4951 case 2: 4974 case 2:
4952 switch (sel) { 4975 switch (sel) {
4953 case 1: 4976 case 1:
4954 - gen_op_mftc0_tcstatus(); 4977 + tcg_gen_helper_0_0(do_mftc0_tcstatus);
4955 break; 4978 break;
4956 case 2: 4979 case 2:
4957 - gen_op_mftc0_tcbind(); 4980 + tcg_gen_helper_0_0(do_mftc0_tcbind);
4958 break; 4981 break;
4959 case 3: 4982 case 3:
4960 - gen_op_mftc0_tcrestart(); 4983 + tcg_gen_helper_0_0(do_mftc0_tcrestart);
4961 break; 4984 break;
4962 case 4: 4985 case 4:
4963 - gen_op_mftc0_tchalt(); 4986 + tcg_gen_helper_0_0(do_mftc0_tchalt);
4964 break; 4987 break;
4965 case 5: 4988 case 5:
4966 - gen_op_mftc0_tccontext(); 4989 + tcg_gen_helper_0_0(do_mftc0_tccontext);
4967 break; 4990 break;
4968 case 6: 4991 case 6:
4969 - gen_op_mftc0_tcschedule(); 4992 + tcg_gen_helper_0_0(do_mftc0_tcschedule);
4970 break; 4993 break;
4971 case 7: 4994 case 7:
4972 - gen_op_mftc0_tcschefback(); 4995 + tcg_gen_helper_0_0(do_mftc0_tcschefback);
4973 break; 4996 break;
4974 default: 4997 default:
4975 gen_mfc0(env, ctx, rt, sel); 4998 gen_mfc0(env, ctx, rt, sel);
@@ -4979,7 +5002,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, @@ -4979,7 +5002,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
4979 case 10: 5002 case 10:
4980 switch (sel) { 5003 switch (sel) {
4981 case 0: 5004 case 0:
4982 - gen_op_mftc0_entryhi(); 5005 + tcg_gen_helper_0_0(do_mftc0_entryhi);
4983 break; 5006 break;
4984 default: 5007 default:
4985 gen_mfc0(env, ctx, rt, sel); 5008 gen_mfc0(env, ctx, rt, sel);
@@ -4988,7 +5011,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, @@ -4988,7 +5011,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
4988 case 12: 5011 case 12:
4989 switch (sel) { 5012 switch (sel) {
4990 case 0: 5013 case 0:
4991 - gen_op_mftc0_status(); 5014 + tcg_gen_helper_0_0(do_mftc0_status);
4992 break; 5015 break;
4993 default: 5016 default:
4994 gen_mfc0(env, ctx, rt, sel); 5017 gen_mfc0(env, ctx, rt, sel);
@@ -4997,7 +5020,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, @@ -4997,7 +5020,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
4997 case 23: 5020 case 23:
4998 switch (sel) { 5021 switch (sel) {
4999 case 0: 5022 case 0:
5000 - gen_op_mftc0_debug(); 5023 + tcg_gen_helper_0_0(do_mftc0_debug);
5001 break; 5024 break;
5002 default: 5025 default:
5003 gen_mfc0(env, ctx, rt, sel); 5026 gen_mfc0(env, ctx, rt, sel);
@@ -5010,49 +5033,49 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, @@ -5010,49 +5033,49 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
5010 } else switch (sel) { 5033 } else switch (sel) {
5011 /* GPR registers. */ 5034 /* GPR registers. */
5012 case 0: 5035 case 0:
5013 - gen_op_mftgpr(rt); 5036 + tcg_gen_helper_0_1i(do_mftgpr, rt);
5014 break; 5037 break;
5015 /* Auxiliary CPU registers */ 5038 /* Auxiliary CPU registers */
5016 case 1: 5039 case 1:
5017 switch (rt) { 5040 switch (rt) {
5018 case 0: 5041 case 0:
5019 - gen_op_mftlo(0); 5042 + tcg_gen_helper_0_1i(do_mftlo, 0);
5020 break; 5043 break;
5021 case 1: 5044 case 1:
5022 - gen_op_mfthi(0); 5045 + tcg_gen_helper_0_1i(do_mfthi, 0);
5023 break; 5046 break;
5024 case 2: 5047 case 2:
5025 - gen_op_mftacx(0); 5048 + tcg_gen_helper_0_1i(do_mftacx, 0);
5026 break; 5049 break;
5027 case 4: 5050 case 4:
5028 - gen_op_mftlo(1); 5051 + tcg_gen_helper_0_1i(do_mftlo, 1);
5029 break; 5052 break;
5030 case 5: 5053 case 5:
5031 - gen_op_mfthi(1); 5054 + tcg_gen_helper_0_1i(do_mfthi, 1);
5032 break; 5055 break;
5033 case 6: 5056 case 6:
5034 - gen_op_mftacx(1); 5057 + tcg_gen_helper_0_1i(do_mftacx, 1);
5035 break; 5058 break;
5036 case 8: 5059 case 8:
5037 - gen_op_mftlo(2); 5060 + tcg_gen_helper_0_1i(do_mftlo, 2);
5038 break; 5061 break;
5039 case 9: 5062 case 9:
5040 - gen_op_mfthi(2); 5063 + tcg_gen_helper_0_1i(do_mfthi, 2);
5041 break; 5064 break;
5042 case 10: 5065 case 10:
5043 - gen_op_mftacx(2); 5066 + tcg_gen_helper_0_1i(do_mftacx, 2);
5044 break; 5067 break;
5045 case 12: 5068 case 12:
5046 - gen_op_mftlo(3); 5069 + tcg_gen_helper_0_1i(do_mftlo, 3);
5047 break; 5070 break;
5048 case 13: 5071 case 13:
5049 - gen_op_mfthi(3); 5072 + tcg_gen_helper_0_1i(do_mfthi, 3);
5050 break; 5073 break;
5051 case 14: 5074 case 14:
5052 - gen_op_mftacx(3); 5075 + tcg_gen_helper_0_1i(do_mftacx, 3);
5053 break; 5076 break;
5054 case 16: 5077 case 16:
5055 - gen_op_mftdsp(); 5078 + tcg_gen_helper_0_0(do_mftdsp);
5056 break; 5079 break;
5057 default: 5080 default:
5058 goto die; 5081 goto die;
@@ -5071,7 +5094,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, @@ -5071,7 +5094,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
5071 break; 5094 break;
5072 case 3: 5095 case 3:
5073 /* XXX: For now we support only a single FPU context. */ 5096 /* XXX: For now we support only a single FPU context. */
5074 - gen_op_cfc1(rt); 5097 + tcg_gen_helper_0_1i(do_cfc1, rt);
5075 break; 5098 break;
5076 /* COP2: Not implemented. */ 5099 /* COP2: Not implemented. */
5077 case 4: 5100 case 4:
@@ -5115,25 +5138,25 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, @@ -5115,25 +5138,25 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
5115 case 2: 5138 case 2:
5116 switch (sel) { 5139 switch (sel) {
5117 case 1: 5140 case 1:
5118 - gen_op_mttc0_tcstatus(); 5141 + tcg_gen_helper_0_0(do_mttc0_tcstatus);
5119 break; 5142 break;
5120 case 2: 5143 case 2:
5121 - gen_op_mttc0_tcbind(); 5144 + tcg_gen_helper_0_0(do_mttc0_tcbind);
5122 break; 5145 break;
5123 case 3: 5146 case 3:
5124 - gen_op_mttc0_tcrestart(); 5147 + tcg_gen_helper_0_0(do_mttc0_tcrestart);
5125 break; 5148 break;
5126 case 4: 5149 case 4:
5127 - gen_op_mttc0_tchalt(); 5150 + tcg_gen_helper_0_0(do_mttc0_tchalt);
5128 break; 5151 break;
5129 case 5: 5152 case 5:
5130 - gen_op_mttc0_tccontext(); 5153 + tcg_gen_helper_0_0(do_mttc0_tccontext);
5131 break; 5154 break;
5132 case 6: 5155 case 6:
5133 - gen_op_mttc0_tcschedule(); 5156 + tcg_gen_helper_0_0(do_mttc0_tcschedule);
5134 break; 5157 break;
5135 case 7: 5158 case 7:
5136 - gen_op_mttc0_tcschefback(); 5159 + tcg_gen_helper_0_0(do_mttc0_tcschefback);
5137 break; 5160 break;
5138 default: 5161 default:
5139 gen_mtc0(env, ctx, rd, sel); 5162 gen_mtc0(env, ctx, rd, sel);
@@ -5143,7 +5166,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, @@ -5143,7 +5166,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
5143 case 10: 5166 case 10:
5144 switch (sel) { 5167 switch (sel) {
5145 case 0: 5168 case 0:
5146 - gen_op_mttc0_entryhi(); 5169 + tcg_gen_helper_0_0(do_mttc0_entryhi);
5147 break; 5170 break;
5148 default: 5171 default:
5149 gen_mtc0(env, ctx, rd, sel); 5172 gen_mtc0(env, ctx, rd, sel);
@@ -5152,7 +5175,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, @@ -5152,7 +5175,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
5152 case 12: 5175 case 12:
5153 switch (sel) { 5176 switch (sel) {
5154 case 0: 5177 case 0:
5155 - gen_op_mttc0_status(); 5178 + tcg_gen_helper_0_0(do_mttc0_status);
5156 break; 5179 break;
5157 default: 5180 default:
5158 gen_mtc0(env, ctx, rd, sel); 5181 gen_mtc0(env, ctx, rd, sel);
@@ -5161,7 +5184,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, @@ -5161,7 +5184,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
5161 case 23: 5184 case 23:
5162 switch (sel) { 5185 switch (sel) {
5163 case 0: 5186 case 0:
5164 - gen_op_mttc0_debug(); 5187 + tcg_gen_helper_0_0(do_mttc0_debug);
5165 break; 5188 break;
5166 default: 5189 default:
5167 gen_mtc0(env, ctx, rd, sel); 5190 gen_mtc0(env, ctx, rd, sel);
@@ -5174,49 +5197,49 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, @@ -5174,49 +5197,49 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
5174 } else switch (sel) { 5197 } else switch (sel) {
5175 /* GPR registers. */ 5198 /* GPR registers. */
5176 case 0: 5199 case 0:
5177 - gen_op_mttgpr(rd); 5200 + tcg_gen_helper_0_1i(do_mttgpr, rd);
5178 break; 5201 break;
5179 /* Auxiliary CPU registers */ 5202 /* Auxiliary CPU registers */
5180 case 1: 5203 case 1:
5181 switch (rd) { 5204 switch (rd) {
5182 case 0: 5205 case 0:
5183 - gen_op_mttlo(0); 5206 + tcg_gen_helper_0_1i(do_mttlo, 0);
5184 break; 5207 break;
5185 case 1: 5208 case 1:
5186 - gen_op_mtthi(0); 5209 + tcg_gen_helper_0_1i(do_mtthi, 0);
5187 break; 5210 break;
5188 case 2: 5211 case 2:
5189 - gen_op_mttacx(0); 5212 + tcg_gen_helper_0_1i(do_mttacx, 0);
5190 break; 5213 break;
5191 case 4: 5214 case 4:
5192 - gen_op_mttlo(1); 5215 + tcg_gen_helper_0_1i(do_mttlo, 1);
5193 break; 5216 break;
5194 case 5: 5217 case 5:
5195 - gen_op_mtthi(1); 5218 + tcg_gen_helper_0_1i(do_mtthi, 1);
5196 break; 5219 break;
5197 case 6: 5220 case 6:
5198 - gen_op_mttacx(1); 5221 + tcg_gen_helper_0_1i(do_mttacx, 1);
5199 break; 5222 break;
5200 case 8: 5223 case 8:
5201 - gen_op_mttlo(2); 5224 + tcg_gen_helper_0_1i(do_mttlo, 2);
5202 break; 5225 break;
5203 case 9: 5226 case 9:
5204 - gen_op_mtthi(2); 5227 + tcg_gen_helper_0_1i(do_mtthi, 2);
5205 break; 5228 break;
5206 case 10: 5229 case 10:
5207 - gen_op_mttacx(2); 5230 + tcg_gen_helper_0_1i(do_mttacx, 2);
5208 break; 5231 break;
5209 case 12: 5232 case 12:
5210 - gen_op_mttlo(3); 5233 + tcg_gen_helper_0_1i(do_mttlo, 3);
5211 break; 5234 break;
5212 case 13: 5235 case 13:
5213 - gen_op_mtthi(3); 5236 + tcg_gen_helper_0_1i(do_mtthi, 3);
5214 break; 5237 break;
5215 case 14: 5238 case 14:
5216 - gen_op_mttacx(3); 5239 + tcg_gen_helper_0_1i(do_mttacx, 3);
5217 break; 5240 break;
5218 case 16: 5241 case 16:
5219 - gen_op_mttdsp(); 5242 + tcg_gen_helper_0_0(do_mttdsp);
5220 break; 5243 break;
5221 default: 5244 default:
5222 goto die; 5245 goto die;
@@ -5235,7 +5258,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, @@ -5235,7 +5258,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
5235 break; 5258 break;
5236 case 3: 5259 case 3:
5237 /* XXX: For now we support only a single FPU context. */ 5260 /* XXX: For now we support only a single FPU context. */
5238 - gen_op_ctc1(rd); 5261 + tcg_gen_helper_0_1i(do_ctc1, rd);
5239 break; 5262 break;
5240 /* COP2: Not implemented. */ 5263 /* COP2: Not implemented. */
5241 case 4: 5264 case 4:
@@ -5380,6 +5403,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int @@ -5380,6 +5403,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5380 } 5403 }
5381 MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd); 5404 MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd);
5382 } 5405 }
  5406 +#endif /* !CONFIG_USER_ONLY */
5383 5407
5384 /* CP1 Branches (before delay slot) */ 5408 /* CP1 Branches (before delay slot) */
5385 static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op, 5409 static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
@@ -5464,13 +5488,13 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) @@ -5464,13 +5488,13 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5464 opn = "mtc1"; 5488 opn = "mtc1";
5465 break; 5489 break;
5466 case OPC_CFC1: 5490 case OPC_CFC1:
5467 - gen_op_cfc1(fs); 5491 + tcg_gen_helper_0_1i(do_cfc1, fs);
5468 gen_store_gpr(cpu_T[0], rt); 5492 gen_store_gpr(cpu_T[0], rt);
5469 opn = "cfc1"; 5493 opn = "cfc1";
5470 break; 5494 break;
5471 case OPC_CTC1: 5495 case OPC_CTC1:
5472 gen_load_gpr(cpu_T[0], rt); 5496 gen_load_gpr(cpu_T[0], rt);
5473 - gen_op_ctc1(fs); 5497 + tcg_gen_helper_0_1i(do_ctc1, fs);
5474 opn = "ctc1"; 5498 opn = "ctc1";
5475 break; 5499 break;
5476 case OPC_DMFC1: 5500 case OPC_DMFC1:
@@ -6846,12 +6870,12 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -6846,12 +6870,12 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6846 check_insn(env, ctx, ASE_MT); 6870 check_insn(env, ctx, ASE_MT);
6847 gen_load_gpr(cpu_T[0], rt); 6871 gen_load_gpr(cpu_T[0], rt);
6848 gen_load_gpr(cpu_T[1], rs); 6872 gen_load_gpr(cpu_T[1], rs);
6849 - gen_op_fork(); 6873 + tcg_gen_helper_0_0(do_fork);
6850 break; 6874 break;
6851 case OPC_YIELD: 6875 case OPC_YIELD:
6852 check_insn(env, ctx, ASE_MT); 6876 check_insn(env, ctx, ASE_MT);
6853 gen_load_gpr(cpu_T[0], rs); 6877 gen_load_gpr(cpu_T[0], rs);
6854 - gen_op_yield(); 6878 + tcg_gen_helper_0_0(do_yield);
6855 gen_store_gpr(cpu_T[0], rd); 6879 gen_store_gpr(cpu_T[0], rd);
6856 break; 6880 break;
6857 #if defined(TARGET_MIPS64) 6881 #if defined(TARGET_MIPS64)
@@ -6921,29 +6945,33 @@ static void decode_opc (CPUState *env, DisasContext *ctx) @@ -6921,29 +6945,33 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6921 case OPC_DMFC0: 6945 case OPC_DMFC0:
6922 case OPC_DMTC0: 6946 case OPC_DMTC0:
6923 #endif 6947 #endif
  6948 +#ifndef CONFIG_USER_ONLY
6924 gen_cp0(env, ctx, op1, rt, rd); 6949 gen_cp0(env, ctx, op1, rt, rd);
  6950 +#endif
6925 break; 6951 break;
6926 case OPC_C0_FIRST ... OPC_C0_LAST: 6952 case OPC_C0_FIRST ... OPC_C0_LAST:
  6953 +#ifndef CONFIG_USER_ONLY
6927 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd); 6954 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
  6955 +#endif
6928 break; 6956 break;
6929 case OPC_MFMC0: 6957 case OPC_MFMC0:
6930 op2 = MASK_MFMC0(ctx->opcode); 6958 op2 = MASK_MFMC0(ctx->opcode);
6931 switch (op2) { 6959 switch (op2) {
6932 case OPC_DMT: 6960 case OPC_DMT:
6933 check_insn(env, ctx, ASE_MT); 6961 check_insn(env, ctx, ASE_MT);
6934 - gen_op_dmt(); 6962 + tcg_gen_helper_0_0(do_dmt);
6935 break; 6963 break;
6936 case OPC_EMT: 6964 case OPC_EMT:
6937 check_insn(env, ctx, ASE_MT); 6965 check_insn(env, ctx, ASE_MT);
6938 - gen_op_emt(); 6966 + tcg_gen_helper_0_0(do_emt);
6939 break; 6967 break;
6940 case OPC_DVPE: 6968 case OPC_DVPE:
6941 check_insn(env, ctx, ASE_MT); 6969 check_insn(env, ctx, ASE_MT);
6942 - gen_op_dvpe(); 6970 + tcg_gen_helper_0_0(do_dvpe);
6943 break; 6971 break;
6944 case OPC_EVPE: 6972 case OPC_EVPE:
6945 check_insn(env, ctx, ASE_MT); 6973 check_insn(env, ctx, ASE_MT);
6946 - gen_op_evpe(); 6974 + tcg_gen_helper_0_0(do_evpe);
6947 break; 6975 break;
6948 case OPC_DI: 6976 case OPC_DI:
6949 check_insn(env, ctx, ISA_MIPS32R2); 6977 check_insn(env, ctx, ISA_MIPS32R2);