gwj / at91sam9263 · Commits

Commit f1aa63203d53945faa708c821c9d4491e5cc8a27

Authored by ths
1 parent 176a4f29

Switch remaining CP0 instructions to TCG or helper functions. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4708 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 5 changed files with 1179 additions and 1236 deletions
target-mips/exec.h
  View file @f1aa632
... ... @@ -48,28 +48,6 @@ register target_ulong T1 asm(AREG2);
48 48 #include "softmmu_exec.h"
49 49 #endif /* !defined(CONFIG_USER_ONLY) */
50 50  
51   -#if defined(TARGET_MIPS64)
52   -#if TARGET_LONG_BITS > HOST_LONG_BITS
53   -void do_dsll (void);
54   -void do_dsll32 (void);
55   -void do_dsra (void);
56   -void do_dsra32 (void);
57   -void do_dsrl (void);
58   -void do_dsrl32 (void);
59   -void do_drotr (void);
60   -void do_drotr32 (void);
61   -void do_dsllv (void);
62   -void do_dsrav (void);
63   -void do_dsrlv (void);
64   -void do_drotrv (void);
65   -void do_dclo (void);
66   -void do_dclz (void);
67   -#endif
68   -#endif
69   -
70   -#if HOST_LONG_BITS < 64
71   -void do_div (void);
72   -#endif
73 51 #if TARGET_LONG_BITS > HOST_LONG_BITS
74 52 void do_mult (void);
75 53 void do_multu (void);
... ... @@ -92,15 +70,7 @@ void do_mulhiu (void);
92 70 void do_mulshi (void);
93 71 void do_mulshiu (void);
94 72 #endif
95   -#if defined(TARGET_MIPS64)
96   -void do_ddiv (void);
97   -#if TARGET_LONG_BITS > HOST_LONG_BITS
98   -void do_ddivu (void);
99   -#endif
100   -#endif
101   -void do_mfc0_random(void);
102   -void do_mfc0_count(void);
103   -void do_mtc0_entryhi(uint32_t in);
  73 +
104 74 void do_mtc0_status_debug(uint32_t old, uint32_t val);
105 75 void do_mtc0_status_irqraise_debug(void);
106 76 void dump_fpu(CPUState *env);
... ... @@ -133,9 +103,6 @@ void cpu_mips_update_irq (CPUState *env);
133 103 void cpu_mips_clock_init (CPUState *env);
134 104 void cpu_mips_tlb_flush (CPUState *env, int flush_global);
135 105  
136   -void do_cfc1 (int reg);
137   -void do_ctc1 (int reg);
138   -
139 106 #define FOP_PROTO(op) \
140 107 void do_float_ ## op ## _s(void); \
141 108 void do_float_ ## op ## _d(void);
... ...
target-mips/helper.h
  View file @f1aa632
... ... @@ -12,3 +12,121 @@ DEF_HELPER(void, do_clz, (void))
12 12 DEF_HELPER(void, do_dclo, (void))
13 13 DEF_HELPER(void, do_dclz, (void))
14 14 #endif
  15 +
  16 +/* CP0 helpers */
  17 +#ifndef CONFIG_USER_ONLY
  18 +DEF_HELPER(void, do_mfc0_mvpcontrol, (void))
  19 +DEF_HELPER(void, do_mfc0_mvpconf0, (void))
  20 +DEF_HELPER(void, do_mfc0_mvpconf1, (void))
  21 +DEF_HELPER(void, do_mfc0_random, (void))
  22 +DEF_HELPER(void, do_mfc0_tcstatus, (void))
  23 +DEF_HELPER(void, do_mftc0_tcstatus, (void))
  24 +DEF_HELPER(void, do_mfc0_tcbind, (void))
  25 +DEF_HELPER(void, do_mftc0_tcbind, (void))
  26 +DEF_HELPER(void, do_mfc0_tcrestart, (void))
  27 +DEF_HELPER(void, do_mftc0_tcrestart, (void))
  28 +DEF_HELPER(void, do_mfc0_tchalt, (void))
  29 +DEF_HELPER(void, do_mftc0_tchalt, (void))
  30 +DEF_HELPER(void, do_mfc0_tccontext, (void))
  31 +DEF_HELPER(void, do_mftc0_tccontext, (void))
  32 +DEF_HELPER(void, do_mfc0_tcschedule, (void))
  33 +DEF_HELPER(void, do_mftc0_tcschedule, (void))
  34 +DEF_HELPER(void, do_mfc0_tcschefback, (void))
  35 +DEF_HELPER(void, do_mftc0_tcschefback, (void))
  36 +DEF_HELPER(void, do_mfc0_count, (void))
  37 +DEF_HELPER(void, do_mftc0_entryhi, (void))
  38 +DEF_HELPER(void, do_mftc0_status, (void))
  39 +DEF_HELPER(void, do_mfc0_lladdr, (void))
  40 +DEF_HELPER(void, do_mfc0_watchlo, (uint32_t sel))
  41 +DEF_HELPER(void, do_mfc0_watchhi, (uint32_t sel))
  42 +DEF_HELPER(void, do_mfc0_debug, (void))
  43 +DEF_HELPER(void, do_mftc0_debug, (void))
  44 +#ifdef TARGET_MIPS64
  45 +DEF_HELPER(void, do_dmfc0_tcrestart, (void))
  46 +DEF_HELPER(void, do_dmfc0_tchalt, (void))
  47 +DEF_HELPER(void, do_dmfc0_tccontext, (void))
  48 +DEF_HELPER(void, do_dmfc0_tcschedule, (void))
  49 +DEF_HELPER(void, do_dmfc0_tcschefback, (void))
  50 +DEF_HELPER(void, do_dmfc0_lladdr, (void))
  51 +DEF_HELPER(void, do_dmfc0_watchlo, (uint32_t sel))
  52 +#endif /* TARGET_MIPS64 */
  53 +
  54 +DEF_HELPER(void, do_mtc0_index, (void))
  55 +DEF_HELPER(void, do_mtc0_mvpcontrol, (void))
  56 +DEF_HELPER(void, do_mtc0_vpecontrol, (void))
  57 +DEF_HELPER(void, do_mtc0_vpeconf0, (void))
  58 +DEF_HELPER(void, do_mtc0_vpeconf1, (void))
  59 +DEF_HELPER(void, do_mtc0_yqmask, (void))
  60 +DEF_HELPER(void, do_mtc0_vpeopt, (void))
  61 +DEF_HELPER(void, do_mtc0_entrylo0, (void))
  62 +DEF_HELPER(void, do_mtc0_tcstatus, (void))
  63 +DEF_HELPER(void, do_mttc0_tcstatus, (void))
  64 +DEF_HELPER(void, do_mtc0_tcbind, (void))
  65 +DEF_HELPER(void, do_mttc0_tcbind, (void))
  66 +DEF_HELPER(void, do_mtc0_tcrestart, (void))
  67 +DEF_HELPER(void, do_mttc0_tcrestart, (void))
  68 +DEF_HELPER(void, do_mtc0_tchalt, (void))
  69 +DEF_HELPER(void, do_mttc0_tchalt, (void))
  70 +DEF_HELPER(void, do_mtc0_tccontext, (void))
  71 +DEF_HELPER(void, do_mttc0_tccontext, (void))
  72 +DEF_HELPER(void, do_mtc0_tcschedule, (void))
  73 +DEF_HELPER(void, do_mttc0_tcschedule, (void))
  74 +DEF_HELPER(void, do_mtc0_tcschefback, (void))
  75 +DEF_HELPER(void, do_mttc0_tcschefback, (void))
  76 +DEF_HELPER(void, do_mtc0_entrylo1, (void))
  77 +DEF_HELPER(void, do_mtc0_context, (void))
  78 +DEF_HELPER(void, do_mtc0_pagemask, (void))
  79 +DEF_HELPER(void, do_mtc0_pagegrain, (void))
  80 +DEF_HELPER(void, do_mtc0_wired, (void))
  81 +DEF_HELPER(void, do_mtc0_srsconf0, (void))
  82 +DEF_HELPER(void, do_mtc0_srsconf1, (void))
  83 +DEF_HELPER(void, do_mtc0_srsconf2, (void))
  84 +DEF_HELPER(void, do_mtc0_srsconf3, (void))
  85 +DEF_HELPER(void, do_mtc0_srsconf4, (void))
  86 +DEF_HELPER(void, do_mtc0_hwrena, (void))
  87 +DEF_HELPER(void, do_mtc0_count, (void))
  88 +DEF_HELPER(void, do_mtc0_entryhi, (void))
  89 +DEF_HELPER(void, do_mttc0_entryhi, (void))
  90 +DEF_HELPER(void, do_mtc0_compare, (void))
  91 +DEF_HELPER(void, do_mtc0_status, (void))
  92 +DEF_HELPER(void, do_mttc0_status, (void))
  93 +DEF_HELPER(void, do_mtc0_intctl, (void))
  94 +DEF_HELPER(void, do_mtc0_srsctl, (void))
  95 +DEF_HELPER(void, do_mtc0_cause, (void))
  96 +DEF_HELPER(void, do_mtc0_ebase, (void))
  97 +DEF_HELPER(void, do_mtc0_config0, (void))
  98 +DEF_HELPER(void, do_mtc0_config2, (void))
  99 +DEF_HELPER(void, do_mtc0_watchlo, (uint32_t sel))
  100 +DEF_HELPER(void, do_mtc0_watchhi, (uint32_t sel))
  101 +DEF_HELPER(void, do_mtc0_xcontext, (void))
  102 +DEF_HELPER(void, do_mtc0_framemask, (void))
  103 +DEF_HELPER(void, do_mtc0_debug, (void))
  104 +DEF_HELPER(void, do_mttc0_debug, (void))
  105 +DEF_HELPER(void, do_mtc0_performance0, (void))
  106 +DEF_HELPER(void, do_mtc0_taglo, (void))
  107 +DEF_HELPER(void, do_mtc0_datalo, (void))
  108 +DEF_HELPER(void, do_mtc0_taghi, (void))
  109 +DEF_HELPER(void, do_mtc0_datahi, (void))
  110 +#endif /* !CONFIG_USER_ONLY */
  111 +
  112 +/* MIPS MT functions */
  113 +DEF_HELPER(void, do_mftgpr, (uint32_t sel))
  114 +DEF_HELPER(void, do_mftlo, (uint32_t sel))
  115 +DEF_HELPER(void, do_mfthi, (uint32_t sel))
  116 +DEF_HELPER(void, do_mftacx, (uint32_t sel))
  117 +DEF_HELPER(void, do_mftdsp, (void))
  118 +DEF_HELPER(void, do_mttgpr, (uint32_t sel))
  119 +DEF_HELPER(void, do_mttlo, (uint32_t sel))
  120 +DEF_HELPER(void, do_mtthi, (uint32_t sel))
  121 +DEF_HELPER(void, do_mttacx, (uint32_t sel))
  122 +DEF_HELPER(void, do_mttdsp, (void))
  123 +DEF_HELPER(void, do_dmt, (void))
  124 +DEF_HELPER(void, do_emt, (void))
  125 +DEF_HELPER(void, do_dvpe, (void))
  126 +DEF_HELPER(void, do_evpe, (void))
  127 +DEF_HELPER(void, do_fork, (void))
  128 +DEF_HELPER(void, do_yield, (void))
  129 +
  130 +/* CP1 functions */
  131 +DEF_HELPER(void, do_cfc1, (uint32_t reg))
  132 +DEF_HELPER(void, do_ctc1, (uint32_t reg))
... ...
target-mips/op.c
  View file @f1aa632
... ... @@ -460,946 +460,6 @@ void op_dmultu (void)
460 460 }
461 461 #endif
462 462  
463   -/* CP0 functions */
464   -void op_mfc0_mvpcontrol (void)
465   -{
466   - T0 = env->mvp->CP0_MVPControl;
467   - FORCE_RET();
468   -}
469   -
470   -void op_mfc0_mvpconf0 (void)
471   -{
472   - T0 = env->mvp->CP0_MVPConf0;
473   - FORCE_RET();
474   -}
475   -
476   -void op_mfc0_mvpconf1 (void)
477   -{
478   - T0 = env->mvp->CP0_MVPConf1;
479   - FORCE_RET();
480   -}
481   -
482   -void op_mfc0_random (void)
483   -{
484   - CALL_FROM_TB0(do_mfc0_random);
485   - FORCE_RET();
486   -}
487   -
488   -void op_mfc0_tcstatus (void)
489   -{
490   - T0 = env->CP0_TCStatus[env->current_tc];
491   - FORCE_RET();
492   -}
493   -
494   -void op_mftc0_tcstatus(void)
495   -{
496   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
497   -
498   - T0 = env->CP0_TCStatus[other_tc];
499   - FORCE_RET();
500   -}
501   -
502   -void op_mfc0_tcbind (void)
503   -{
504   - T0 = env->CP0_TCBind[env->current_tc];
505   - FORCE_RET();
506   -}
507   -
508   -void op_mftc0_tcbind(void)
509   -{
510   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
511   -
512   - T0 = env->CP0_TCBind[other_tc];
513   - FORCE_RET();
514   -}
515   -
516   -void op_mfc0_tcrestart (void)
517   -{
518   - T0 = env->PC[env->current_tc];
519   - FORCE_RET();
520   -}
521   -
522   -void op_mftc0_tcrestart(void)
523   -{
524   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
525   -
526   - T0 = env->PC[other_tc];
527   - FORCE_RET();
528   -}
529   -
530   -void op_mfc0_tchalt (void)
531   -{
532   - T0 = env->CP0_TCHalt[env->current_tc];
533   - FORCE_RET();
534   -}
535   -
536   -void op_mftc0_tchalt(void)
537   -{
538   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
539   -
540   - T0 = env->CP0_TCHalt[other_tc];
541   - FORCE_RET();
542   -}
543   -
544   -void op_mfc0_tccontext (void)
545   -{
546   - T0 = env->CP0_TCContext[env->current_tc];
547   - FORCE_RET();
548   -}
549   -
550   -void op_mftc0_tccontext(void)
551   -{
552   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
553   -
554   - T0 = env->CP0_TCContext[other_tc];
555   - FORCE_RET();
556   -}
557   -
558   -void op_mfc0_tcschedule (void)
559   -{
560   - T0 = env->CP0_TCSchedule[env->current_tc];
561   - FORCE_RET();
562   -}
563   -
564   -void op_mftc0_tcschedule(void)
565   -{
566   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
567   -
568   - T0 = env->CP0_TCSchedule[other_tc];
569   - FORCE_RET();
570   -}
571   -
572   -void op_mfc0_tcschefback (void)
573   -{
574   - T0 = env->CP0_TCScheFBack[env->current_tc];
575   - FORCE_RET();
576   -}
577   -
578   -void op_mftc0_tcschefback(void)
579   -{
580   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
581   -
582   - T0 = env->CP0_TCScheFBack[other_tc];
583   - FORCE_RET();
584   -}
585   -
586   -void op_mfc0_count (void)
587   -{
588   - CALL_FROM_TB0(do_mfc0_count);
589   - FORCE_RET();
590   -}
591   -
592   -void op_mftc0_entryhi(void)
593   -{
594   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
595   -
596   - T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);
597   - FORCE_RET();
598   -}
599   -
600   -void op_mftc0_status(void)
601   -{
602   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
603   - uint32_t tcstatus = env->CP0_TCStatus[other_tc];
604   -
605   - T0 = env->CP0_Status & ~0xf1000018;
606   - T0 |= tcstatus & (0xf << CP0TCSt_TCU0);
607   - T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
608   - T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
609   - FORCE_RET();
610   -}
611   -
612   -void op_mfc0_lladdr (void)
613   -{
614   - T0 = (int32_t)env->CP0_LLAddr >> 4;
615   - FORCE_RET();
616   -}
617   -
618   -void op_mfc0_watchlo (void)
619   -{
620   - T0 = (int32_t)env->CP0_WatchLo[PARAM1];
621   - FORCE_RET();
622   -}
623   -
624   -void op_mfc0_watchhi (void)
625   -{
626   - T0 = env->CP0_WatchHi[PARAM1];
627   - FORCE_RET();
628   -}
629   -
630   -void op_mfc0_debug (void)
631   -{
632   - T0 = env->CP0_Debug;
633   - if (env->hflags & MIPS_HFLAG_DM)
634   - T0 |= 1 << CP0DB_DM;
635   - FORCE_RET();
636   -}
637   -
638   -void op_mftc0_debug(void)
639   -{
640   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
641   -
642   - /* XXX: Might be wrong, check with EJTAG spec. */
643   - T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
644   - (env->CP0_Debug_tcstatus[other_tc] &
645   - ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
646   - FORCE_RET();
647   -}
648   -
649   -void op_mtc0_index (void)
650   -{
651   - int num = 1;
652   - unsigned int tmp = env->tlb->nb_tlb;
653   -
654   - do {
655   - tmp >>= 1;
656   - num <<= 1;
657   - } while (tmp);
658   - env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (num - 1));
659   - FORCE_RET();
660   -}
661   -
662   -void op_mtc0_mvpcontrol (void)
663   -{
664   - uint32_t mask = 0;
665   - uint32_t newval;
666   -
667   - if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
668   - mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
669   - (1 << CP0MVPCo_EVP);
670   - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
671   - mask |= (1 << CP0MVPCo_STLB);
672   - newval = (env->mvp->CP0_MVPControl & ~mask) | (T0 & mask);
673   -
674   - // TODO: Enable/disable shared TLB, enable/disable VPEs.
675   -
676   - env->mvp->CP0_MVPControl = newval;
677   - FORCE_RET();
678   -}
679   -
680   -void op_mtc0_vpecontrol (void)
681   -{
682   - uint32_t mask;
683   - uint32_t newval;
684   -
685   - mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
686   - (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
687   - newval = (env->CP0_VPEControl & ~mask) | (T0 & mask);
688   -
689   - /* Yield scheduler intercept not implemented. */
690   - /* Gating storage scheduler intercept not implemented. */
691   -
692   - // TODO: Enable/disable TCs.
693   -
694   - env->CP0_VPEControl = newval;
695   - FORCE_RET();
696   -}
697   -
698   -void op_mtc0_vpeconf0 (void)
699   -{
700   - uint32_t mask = 0;
701   - uint32_t newval;
702   -
703   - if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
704   - if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
705   - mask |= (0xff << CP0VPEC0_XTC);
706   - mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
707   - }
708   - newval = (env->CP0_VPEConf0 & ~mask) | (T0 & mask);
709   -
710   - // TODO: TC exclusive handling due to ERL/EXL.
711   -
712   - env->CP0_VPEConf0 = newval;
713   - FORCE_RET();
714   -}
715   -
716   -void op_mtc0_vpeconf1 (void)
717   -{
718   - uint32_t mask = 0;
719   - uint32_t newval;
720   -
721   - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
722   - mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
723   - (0xff << CP0VPEC1_NCP1);
724   - newval = (env->CP0_VPEConf1 & ~mask) | (T0 & mask);
725   -
726   - /* UDI not implemented. */
727   - /* CP2 not implemented. */
728   -
729   - // TODO: Handle FPU (CP1) binding.
730   -
731   - env->CP0_VPEConf1 = newval;
732   - FORCE_RET();
733   -}
734   -
735   -void op_mtc0_yqmask (void)
736   -{
737   - /* Yield qualifier inputs not implemented. */
738   - env->CP0_YQMask = 0x00000000;
739   - FORCE_RET();
740   -}
741   -
742   -void op_mtc0_vpeschedule (void)
743   -{
744   - env->CP0_VPESchedule = T0;
745   - FORCE_RET();
746   -}
747   -
748   -void op_mtc0_vpeschefback (void)
749   -{
750   - env->CP0_VPEScheFBack = T0;
751   - FORCE_RET();
752   -}
753   -
754   -void op_mtc0_vpeopt (void)
755   -{
756   - env->CP0_VPEOpt = T0 & 0x0000ffff;
757   - FORCE_RET();
758   -}
759   -
760   -void op_mtc0_entrylo0 (void)
761   -{
762   - /* Large physaddr (PABITS) not implemented */
763   - /* 1k pages not implemented */
764   - env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
765   - FORCE_RET();
766   -}
767   -
768   -void op_mtc0_tcstatus (void)
769   -{
770   - uint32_t mask = env->CP0_TCStatus_rw_bitmask;
771   - uint32_t newval;
772   -
773   - newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (T0 & mask);
774   -
775   - // TODO: Sync with CP0_Status.
776   -
777   - env->CP0_TCStatus[env->current_tc] = newval;
778   - FORCE_RET();
779   -}
780   -
781   -void op_mttc0_tcstatus (void)
782   -{
783   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
784   -
785   - // TODO: Sync with CP0_Status.
786   -
787   - env->CP0_TCStatus[other_tc] = T0;
788   - FORCE_RET();
789   -}
790   -
791   -void op_mtc0_tcbind (void)
792   -{
793   - uint32_t mask = (1 << CP0TCBd_TBE);
794   - uint32_t newval;
795   -
796   - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
797   - mask |= (1 << CP0TCBd_CurVPE);
798   - newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (T0 & mask);
799   - env->CP0_TCBind[env->current_tc] = newval;
800   - FORCE_RET();
801   -}
802   -
803   -void op_mttc0_tcbind (void)
804   -{
805   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
806   - uint32_t mask = (1 << CP0TCBd_TBE);
807   - uint32_t newval;
808   -
809   - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
810   - mask |= (1 << CP0TCBd_CurVPE);
811   - newval = (env->CP0_TCBind[other_tc] & ~mask) | (T0 & mask);
812   - env->CP0_TCBind[other_tc] = newval;
813   - FORCE_RET();
814   -}
815   -
816   -void op_mtc0_tcrestart (void)
817   -{
818   - env->PC[env->current_tc] = T0;
819   - env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS);
820   - env->CP0_LLAddr = 0ULL;
821   - /* MIPS16 not implemented. */
822   - FORCE_RET();
823   -}
824   -
825   -void op_mttc0_tcrestart (void)
826   -{
827   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
828   -
829   - env->PC[other_tc] = T0;
830   - env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS);
831   - env->CP0_LLAddr = 0ULL;
832   - /* MIPS16 not implemented. */
833   - FORCE_RET();
834   -}
835   -
836   -void op_mtc0_tchalt (void)
837   -{
838   - env->CP0_TCHalt[env->current_tc] = T0 & 0x1;
839   -
840   - // TODO: Halt TC / Restart (if allocated+active) TC.
841   -
842   - FORCE_RET();
843   -}
844   -
845   -void op_mttc0_tchalt (void)
846   -{
847   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
848   -
849   - // TODO: Halt TC / Restart (if allocated+active) TC.
850   -
851   - env->CP0_TCHalt[other_tc] = T0;
852   - FORCE_RET();
853   -}
854   -
855   -void op_mtc0_tccontext (void)
856   -{
857   - env->CP0_TCContext[env->current_tc] = T0;
858   - FORCE_RET();
859   -}
860   -
861   -void op_mttc0_tccontext (void)
862   -{
863   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
864   -
865   - env->CP0_TCContext[other_tc] = T0;
866   - FORCE_RET();
867   -}
868   -
869   -void op_mtc0_tcschedule (void)
870   -{
871   - env->CP0_TCSchedule[env->current_tc] = T0;
872   - FORCE_RET();
873   -}
874   -
875   -void op_mttc0_tcschedule (void)
876   -{
877   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
878   -
879   - env->CP0_TCSchedule[other_tc] = T0;
880   - FORCE_RET();
881   -}
882   -
883   -void op_mtc0_tcschefback (void)
884   -{
885   - env->CP0_TCScheFBack[env->current_tc] = T0;
886   - FORCE_RET();
887   -}
888   -
889   -void op_mttc0_tcschefback (void)
890   -{
891   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
892   -
893   - env->CP0_TCScheFBack[other_tc] = T0;
894   - FORCE_RET();
895   -}
896   -
897   -void op_mtc0_entrylo1 (void)
898   -{
899   - /* Large physaddr (PABITS) not implemented */
900   - /* 1k pages not implemented */
901   - env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
902   - FORCE_RET();
903   -}
904   -
905   -void op_mtc0_context (void)
906   -{
907   - env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
908   - FORCE_RET();
909   -}
910   -
911   -void op_mtc0_pagemask (void)
912   -{
913   - /* 1k pages not implemented */
914   - env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
915   - FORCE_RET();
916   -}
917   -
918   -void op_mtc0_pagegrain (void)
919   -{
920   - /* SmartMIPS not implemented */
921   - /* Large physaddr (PABITS) not implemented */
922   - /* 1k pages not implemented */
923   - env->CP0_PageGrain = 0;
924   - FORCE_RET();
925   -}
926   -
927   -void op_mtc0_wired (void)
928   -{
929   - env->CP0_Wired = T0 % env->tlb->nb_tlb;
930   - FORCE_RET();
931   -}
932   -
933   -void op_mtc0_srsconf0 (void)
934   -{
935   - env->CP0_SRSConf0 |= T0 & env->CP0_SRSConf0_rw_bitmask;
936   - FORCE_RET();
937   -}
938   -
939   -void op_mtc0_srsconf1 (void)
940   -{
941   - env->CP0_SRSConf1 |= T0 & env->CP0_SRSConf1_rw_bitmask;
942   - FORCE_RET();
943   -}
944   -
945   -void op_mtc0_srsconf2 (void)
946   -{
947   - env->CP0_SRSConf2 |= T0 & env->CP0_SRSConf2_rw_bitmask;
948   - FORCE_RET();
949   -}
950   -
951   -void op_mtc0_srsconf3 (void)
952   -{
953   - env->CP0_SRSConf3 |= T0 & env->CP0_SRSConf3_rw_bitmask;
954   - FORCE_RET();
955   -}
956   -
957   -void op_mtc0_srsconf4 (void)
958   -{
959   - env->CP0_SRSConf4 |= T0 & env->CP0_SRSConf4_rw_bitmask;
960   - FORCE_RET();
961   -}
962   -
963   -void op_mtc0_hwrena (void)
964   -{
965   - env->CP0_HWREna = T0 & 0x0000000F;
966   - FORCE_RET();
967   -}
968   -
969   -void op_mtc0_count (void)
970   -{
971   - CALL_FROM_TB2(cpu_mips_store_count, env, T0);
972   - FORCE_RET();
973   -}
974   -
975   -void op_mtc0_entryhi (void)
976   -{
977   - target_ulong old, val;
978   -
979   - /* 1k pages not implemented */
980   - val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
981   -#if defined(TARGET_MIPS64)
982   - val &= env->SEGMask;
983   -#endif
984   - old = env->CP0_EntryHi;
985   - env->CP0_EntryHi = val;
986   - if (env->CP0_Config3 & (1 << CP0C3_MT)) {
987   - uint32_t tcst = env->CP0_TCStatus[env->current_tc] & ~0xff;
988   - env->CP0_TCStatus[env->current_tc] = tcst | (val & 0xff);
989   - }
990   - /* If the ASID changes, flush qemu's TLB. */
991   - if ((old & 0xFF) != (val & 0xFF))
992   - CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
993   - FORCE_RET();
994   -}
995   -
996   -void op_mttc0_entryhi(void)
997   -{
998   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
999   -
1000   - env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (T0 & ~0xff);
1001   - env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (T0 & 0xff);
1002   - FORCE_RET();
1003   -}
1004   -
1005   -void op_mtc0_compare (void)
1006   -{
1007   - CALL_FROM_TB2(cpu_mips_store_compare, env, T0);
1008   - FORCE_RET();
1009   -}
1010   -
1011   -void op_mtc0_status (void)
1012   -{
1013   - uint32_t val, old;
1014   - uint32_t mask = env->CP0_Status_rw_bitmask;
1015   -
1016   - val = T0 & mask;
1017   - old = env->CP0_Status;
1018   - env->CP0_Status = (env->CP0_Status & ~mask) | val;
1019   - CALL_FROM_TB1(compute_hflags, env);
1020   - if (loglevel & CPU_LOG_EXEC)
1021   - CALL_FROM_TB2(do_mtc0_status_debug, old, val);
1022   - CALL_FROM_TB1(cpu_mips_update_irq, env);
1023   - FORCE_RET();
1024   -}
1025   -
1026   -void op_mttc0_status(void)
1027   -{
1028   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1029   - uint32_t tcstatus = env->CP0_TCStatus[other_tc];
1030   -
1031   - env->CP0_Status = T0 & ~0xf1000018;
1032   - tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (T0 & (0xf << CP0St_CU0));
1033   - tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((T0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
1034   - tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((T0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
1035   - env->CP0_TCStatus[other_tc] = tcstatus;
1036   - FORCE_RET();
1037   -}
1038   -
1039   -void op_mtc0_intctl (void)
1040   -{
1041   - /* vectored interrupts not implemented, no performance counters. */
1042   - env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (T0 & 0x000002e0);
1043   - FORCE_RET();
1044   -}
1045   -
1046   -void op_mtc0_srsctl (void)
1047   -{
1048   - uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1049   - env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (T0 & mask);
1050   - FORCE_RET();
1051   -}
1052   -
1053   -void op_mtc0_srsmap (void)
1054   -{
1055   - env->CP0_SRSMap = T0;
1056   - FORCE_RET();
1057   -}
1058   -
1059   -void op_mtc0_cause (void)
1060   -{
1061   - uint32_t mask = 0x00C00300;
1062   - uint32_t old = env->CP0_Cause;
1063   -
1064   - if (env->insn_flags & ISA_MIPS32R2)
1065   - mask |= 1 << CP0Ca_DC;
1066   -
1067   - env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);
1068   -
1069   - if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
1070   - if (env->CP0_Cause & (1 << CP0Ca_DC))
1071   - CALL_FROM_TB1(cpu_mips_stop_count, env);
1072   - else
1073   - CALL_FROM_TB1(cpu_mips_start_count, env);
1074   - }
1075   -
1076   - /* Handle the software interrupt as an hardware one, as they
1077   - are very similar */
1078   - if (T0 & CP0Ca_IP_mask) {
1079   - CALL_FROM_TB1(cpu_mips_update_irq, env);
1080   - }
1081   - FORCE_RET();
1082   -}
1083   -
1084   -void op_mtc0_epc (void)
1085   -{
1086   - env->CP0_EPC = T0;
1087   - FORCE_RET();
1088   -}
1089   -
1090   -void op_mtc0_ebase (void)
1091   -{
1092   - /* vectored interrupts not implemented */
1093   - /* Multi-CPU not implemented */
1094   - env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
1095   - FORCE_RET();
1096   -}
1097   -
1098   -void op_mtc0_config0 (void)
1099   -{
1100   - env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007);
1101   - FORCE_RET();
1102   -}
1103   -
1104   -void op_mtc0_config2 (void)
1105   -{
1106   - /* tertiary/secondary caches not implemented */
1107   - env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1108   - FORCE_RET();
1109   -}
1110   -
1111   -void op_mtc0_watchlo (void)
1112   -{
1113   - /* Watch exceptions for instructions, data loads, data stores
1114   - not implemented. */
1115   - env->CP0_WatchLo[PARAM1] = (T0 & ~0x7);
1116   - FORCE_RET();
1117   -}
1118   -
1119   -void op_mtc0_watchhi (void)
1120   -{
1121   - env->CP0_WatchHi[PARAM1] = (T0 & 0x40FF0FF8);
1122   - env->CP0_WatchHi[PARAM1] &= ~(env->CP0_WatchHi[PARAM1] & T0 & 0x7);
1123   - FORCE_RET();
1124   -}
1125   -
1126   -void op_mtc0_xcontext (void)
1127   -{
1128   - target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1129   - env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask);
1130   - FORCE_RET();
1131   -}
1132   -
1133   -void op_mtc0_framemask (void)
1134   -{
1135   - env->CP0_Framemask = T0; /* XXX */
1136   - FORCE_RET();
1137   -}
1138   -
1139   -void op_mtc0_debug (void)
1140   -{
1141   - env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
1142   - if (T0 & (1 << CP0DB_DM))
1143   - env->hflags |= MIPS_HFLAG_DM;
1144   - else
1145   - env->hflags &= ~MIPS_HFLAG_DM;
1146   - FORCE_RET();
1147   -}
1148   -
1149   -void op_mttc0_debug(void)
1150   -{
1151   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1152   -
1153   - /* XXX: Might be wrong, check with EJTAG spec. */
1154   - env->CP0_Debug_tcstatus[other_tc] = T0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1155   - env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1156   - (T0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1157   - FORCE_RET();
1158   -}
1159   -
1160   -void op_mtc0_depc (void)
1161   -{
1162   - env->CP0_DEPC = T0;
1163   - FORCE_RET();
1164   -}
1165   -
1166   -void op_mtc0_performance0 (void)
1167   -{
1168   - env->CP0_Performance0 = T0 & 0x000007ff;
1169   - FORCE_RET();
1170   -}
1171   -
1172   -void op_mtc0_taglo (void)
1173   -{
1174   - env->CP0_TagLo = T0 & 0xFFFFFCF6;
1175   - FORCE_RET();
1176   -}
1177   -
1178   -void op_mtc0_datalo (void)
1179   -{
1180   - env->CP0_DataLo = T0; /* XXX */
1181   - FORCE_RET();
1182   -}
1183   -
1184   -void op_mtc0_taghi (void)
1185   -{
1186   - env->CP0_TagHi = T0; /* XXX */
1187   - FORCE_RET();
1188   -}
1189   -
1190   -void op_mtc0_datahi (void)
1191   -{
1192   - env->CP0_DataHi = T0; /* XXX */
1193   - FORCE_RET();
1194   -}
1195   -
1196   -void op_mtc0_errorepc (void)
1197   -{
1198   - env->CP0_ErrorEPC = T0;
1199   - FORCE_RET();
1200   -}
1201   -
1202   -void op_mtc0_desave (void)
1203   -{
1204   - env->CP0_DESAVE = T0;
1205   - FORCE_RET();
1206   -}
1207   -
1208   -#if defined(TARGET_MIPS64)
1209   -void op_dmfc0_tcrestart (void)
1210   -{
1211   - T0 = env->PC[env->current_tc];
1212   - FORCE_RET();
1213   -}
1214   -
1215   -void op_dmfc0_tchalt (void)
1216   -{
1217   - T0 = env->CP0_TCHalt[env->current_tc];
1218   - FORCE_RET();
1219   -}
1220   -
1221   -void op_dmfc0_tccontext (void)
1222   -{
1223   - T0 = env->CP0_TCContext[env->current_tc];
1224   - FORCE_RET();
1225   -}
1226   -
1227   -void op_dmfc0_tcschedule (void)
1228   -{
1229   - T0 = env->CP0_TCSchedule[env->current_tc];
1230   - FORCE_RET();
1231   -}
1232   -
1233   -void op_dmfc0_tcschefback (void)
1234   -{
1235   - T0 = env->CP0_TCScheFBack[env->current_tc];
1236   - FORCE_RET();
1237   -}
1238   -
1239   -void op_dmfc0_lladdr (void)
1240   -{
1241   - T0 = env->CP0_LLAddr >> 4;
1242   - FORCE_RET();
1243   -}
1244   -
1245   -void op_dmfc0_watchlo (void)
1246   -{
1247   - T0 = env->CP0_WatchLo[PARAM1];
1248   - FORCE_RET();
1249   -}
1250   -#endif /* TARGET_MIPS64 */
1251   -
1252   -/* MIPS MT functions */
1253   -void op_mftgpr(void)
1254   -{
1255   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1256   -
1257   - T0 = env->gpr[other_tc][PARAM1];
1258   - FORCE_RET();
1259   -}
1260   -
1261   -void op_mftlo(void)
1262   -{
1263   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1264   -
1265   - T0 = env->LO[other_tc][PARAM1];
1266   - FORCE_RET();
1267   -}
1268   -
1269   -void op_mfthi(void)
1270   -{
1271   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1272   -
1273   - T0 = env->HI[other_tc][PARAM1];
1274   - FORCE_RET();
1275   -}
1276   -
1277   -void op_mftacx(void)
1278   -{
1279   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1280   -
1281   - T0 = env->ACX[other_tc][PARAM1];
1282   - FORCE_RET();
1283   -}
1284   -
1285   -void op_mftdsp(void)
1286   -{
1287   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1288   -
1289   - T0 = env->DSPControl[other_tc];
1290   - FORCE_RET();
1291   -}
1292   -
1293   -void op_mttgpr(void)
1294   -{
1295   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1296   -
1297   - T0 = env->gpr[other_tc][PARAM1];
1298   - FORCE_RET();
1299   -}
1300   -
1301   -void op_mttlo(void)
1302   -{
1303   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1304   -
1305   - T0 = env->LO[other_tc][PARAM1];
1306   - FORCE_RET();
1307   -}
1308   -
1309   -void op_mtthi(void)
1310   -{
1311   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1312   -
1313   - T0 = env->HI[other_tc][PARAM1];
1314   - FORCE_RET();
1315   -}
1316   -
1317   -void op_mttacx(void)
1318   -{
1319   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1320   -
1321   - T0 = env->ACX[other_tc][PARAM1];
1322   - FORCE_RET();
1323   -}
1324   -
1325   -void op_mttdsp(void)
1326   -{
1327   - int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1328   -
1329   - T0 = env->DSPControl[other_tc];
1330   - FORCE_RET();
1331   -}
1332   -
1333   -
1334   -void op_dmt(void)
1335   -{
1336   - // TODO
1337   - T0 = 0;
1338   - // rt = T0
1339   - FORCE_RET();
1340   -}
1341   -
1342   -void op_emt(void)
1343   -{
1344   - // TODO
1345   - T0 = 0;
1346   - // rt = T0
1347   - FORCE_RET();
1348   -}
1349   -
1350   -void op_dvpe(void)
1351   -{
1352   - // TODO
1353   - T0 = 0;
1354   - // rt = T0
1355   - FORCE_RET();
1356   -}
1357   -
1358   -void op_evpe(void)
1359   -{
1360   - // TODO
1361   - T0 = 0;
1362   - // rt = T0
1363   - FORCE_RET();
1364   -}
1365   -
1366   -void op_fork(void)
1367   -{
1368   - // T0 = rt, T1 = rs
1369   - T0 = 0;
1370   - // TODO: store to TC register
1371   - FORCE_RET();
1372   -}
1373   -
1374   -void op_yield(void)
1375   -{
1376   - if (T0 < 0) {
1377   - /* No scheduling policy implemented. */
1378   - if (T0 != -2) {
1379   - if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1380   - env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) {
1381   - env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1382   - env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1383   - CALL_FROM_TB1(do_raise_exception, EXCP_THREAD);
1384   - }
1385   - }
1386   - } else if (T0 == 0) {
1387   - if (0 /* TODO: TC underflow */) {
1388   - env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1389   - CALL_FROM_TB1(do_raise_exception, EXCP_THREAD);
1390   - } else {
1391   - // TODO: Deallocate TC
1392   - }
1393   - } else if (T0 > 0) {
1394   - /* Yield qualifier inputs not implemented. */
1395   - env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1396   - env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1397   - CALL_FROM_TB1(do_raise_exception, EXCP_THREAD);
1398   - }
1399   - T0 = env->CP0_YQMask;
1400   - FORCE_RET();
1401   -}
1402   -
1403 463 /* CP1 functions */
1404 464 #if 0
1405 465 # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
... ... @@ -1407,20 +467,6 @@ void op_yield(void)
1407 467 # define DEBUG_FPU_STATE() do { } while(0)
1408 468 #endif
1409 469  
1410   -void op_cfc1 (void)
1411   -{
1412   - CALL_FROM_TB1(do_cfc1, PARAM1);
1413   - DEBUG_FPU_STATE();
1414   - FORCE_RET();
1415   -}
1416   -
1417   -void op_ctc1 (void)
1418   -{
1419   - CALL_FROM_TB1(do_ctc1, PARAM1);
1420   - DEBUG_FPU_STATE();
1421   - FORCE_RET();
1422   -}
1423   -
1424 470 void op_mfc1 (void)
1425 471 {
1426 472 T0 = (int32_t)WT0;
... ...
target-mips/op_helper.c
  View file @f1aa632
... ... @@ -306,7 +306,7 @@ void do_mulshiu (void)
306 306 }
307 307 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
308 308  
309   -#if defined(CONFIG_USER_ONLY)
  309 +#ifdef CONFIG_USER_ONLY
310 310 void do_mfc0_random (void)
311 311 {
312 312 cpu_abort(env, "mfc0 random\n");
... ... @@ -360,16 +360,662 @@ void cpu_mips_tlb_flush (CPUState *env, int flush_global)
360 360 #else
361 361  
362 362 /* CP0 helpers */
  363 +void do_mfc0_mvpcontrol (void)
  364 +{
  365 + T0 = env->mvp->CP0_MVPControl;
  366 +}
  367 +
  368 +void do_mfc0_mvpconf0 (void)
  369 +{
  370 + T0 = env->mvp->CP0_MVPConf0;
  371 +}
  372 +
  373 +void do_mfc0_mvpconf1 (void)
  374 +{
  375 + T0 = env->mvp->CP0_MVPConf1;
  376 +}
  377 +
363 378 void do_mfc0_random (void)
364 379 {
365 380 T0 = (int32_t)cpu_mips_get_random(env);
366 381 }
367 382  
  383 +void do_mfc0_tcstatus (void)
  384 +{
  385 + T0 = env->CP0_TCStatus[env->current_tc];
  386 +}
  387 +
  388 +void do_mftc0_tcstatus(void)
  389 +{
  390 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  391 +
  392 + T0 = env->CP0_TCStatus[other_tc];
  393 +}
  394 +
  395 +void do_mfc0_tcbind (void)
  396 +{
  397 + T0 = env->CP0_TCBind[env->current_tc];
  398 +}
  399 +
  400 +void do_mftc0_tcbind(void)
  401 +{
  402 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  403 +
  404 + T0 = env->CP0_TCBind[other_tc];
  405 +}
  406 +
  407 +void do_mfc0_tcrestart (void)
  408 +{
  409 + T0 = env->PC[env->current_tc];
  410 +}
  411 +
  412 +void do_mftc0_tcrestart(void)
  413 +{
  414 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  415 +
  416 + T0 = env->PC[other_tc];
  417 +}
  418 +
  419 +void do_mfc0_tchalt (void)
  420 +{
  421 + T0 = env->CP0_TCHalt[env->current_tc];
  422 +}
  423 +
  424 +void do_mftc0_tchalt(void)
  425 +{
  426 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  427 +
  428 + T0 = env->CP0_TCHalt[other_tc];
  429 +}
  430 +
  431 +void do_mfc0_tccontext (void)
  432 +{
  433 + T0 = env->CP0_TCContext[env->current_tc];
  434 +}
  435 +
  436 +void do_mftc0_tccontext(void)
  437 +{
  438 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  439 +
  440 + T0 = env->CP0_TCContext[other_tc];
  441 +}
  442 +
  443 +void do_mfc0_tcschedule (void)
  444 +{
  445 + T0 = env->CP0_TCSchedule[env->current_tc];
  446 +}
  447 +
  448 +void do_mftc0_tcschedule(void)
  449 +{
  450 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  451 +
  452 + T0 = env->CP0_TCSchedule[other_tc];
  453 +}
  454 +
  455 +void do_mfc0_tcschefback (void)
  456 +{
  457 + T0 = env->CP0_TCScheFBack[env->current_tc];
  458 +}
  459 +
  460 +void do_mftc0_tcschefback(void)
  461 +{
  462 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  463 +
  464 + T0 = env->CP0_TCScheFBack[other_tc];
  465 +}
  466 +
368 467 void do_mfc0_count (void)
369 468 {
370 469 T0 = (int32_t)cpu_mips_get_count(env);
371 470 }
372 471  
  472 +void do_mftc0_entryhi(void)
  473 +{
  474 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  475 +
  476 + T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);
  477 +}
  478 +
  479 +void do_mftc0_status(void)
  480 +{
  481 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  482 + uint32_t tcstatus = env->CP0_TCStatus[other_tc];
  483 +
  484 + T0 = env->CP0_Status & ~0xf1000018;
  485 + T0 |= tcstatus & (0xf << CP0TCSt_TCU0);
  486 + T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
  487 + T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
  488 +}
  489 +
  490 +void do_mfc0_lladdr (void)
  491 +{
  492 + T0 = (int32_t)env->CP0_LLAddr >> 4;
  493 +}
  494 +
  495 +void do_mfc0_watchlo (uint32_t sel)
  496 +{
  497 + T0 = (int32_t)env->CP0_WatchLo[sel];
  498 +}
  499 +
  500 +void do_mfc0_watchhi (uint32_t sel)
  501 +{
  502 + T0 = env->CP0_WatchHi[sel];
  503 +}
  504 +
  505 +void do_mfc0_debug (void)
  506 +{
  507 + T0 = env->CP0_Debug;
  508 + if (env->hflags & MIPS_HFLAG_DM)
  509 + T0 |= 1 << CP0DB_DM;
  510 +}
  511 +
  512 +void do_mftc0_debug(void)
  513 +{
  514 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  515 +
  516 + /* XXX: Might be wrong, check with EJTAG spec. */
  517 + T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
  518 + (env->CP0_Debug_tcstatus[other_tc] &
  519 + ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
  520 +}
  521 +
  522 +#if defined(TARGET_MIPS64)
  523 +void do_dmfc0_tcrestart (void)
  524 +{
  525 + T0 = env->PC[env->current_tc];
  526 +}
  527 +
  528 +void do_dmfc0_tchalt (void)
  529 +{
  530 + T0 = env->CP0_TCHalt[env->current_tc];
  531 +}
  532 +
  533 +void do_dmfc0_tccontext (void)
  534 +{
  535 + T0 = env->CP0_TCContext[env->current_tc];
  536 +}
  537 +
  538 +void do_dmfc0_tcschedule (void)
  539 +{
  540 + T0 = env->CP0_TCSchedule[env->current_tc];
  541 +}
  542 +
  543 +void do_dmfc0_tcschefback (void)
  544 +{
  545 + T0 = env->CP0_TCScheFBack[env->current_tc];
  546 +}
  547 +
  548 +void do_dmfc0_lladdr (void)
  549 +{
  550 + T0 = env->CP0_LLAddr >> 4;
  551 +}
  552 +
  553 +void do_dmfc0_watchlo (uint32_t sel)
  554 +{
  555 + T0 = env->CP0_WatchLo[sel];
  556 +}
  557 +#endif /* TARGET_MIPS64 */
  558 +
  559 +void do_mtc0_index (void)
  560 +{
  561 + int num = 1;
  562 + unsigned int tmp = env->tlb->nb_tlb;
  563 +
  564 + do {
  565 + tmp >>= 1;
  566 + num <<= 1;
  567 + } while (tmp);
  568 + env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (num - 1));
  569 +}
  570 +
  571 +void do_mtc0_mvpcontrol (void)
  572 +{
  573 + uint32_t mask = 0;
  574 + uint32_t newval;
  575 +
  576 + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
  577 + mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
  578 + (1 << CP0MVPCo_EVP);
  579 + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
  580 + mask |= (1 << CP0MVPCo_STLB);
  581 + newval = (env->mvp->CP0_MVPControl & ~mask) | (T0 & mask);
  582 +
  583 + // TODO: Enable/disable shared TLB, enable/disable VPEs.
  584 +
  585 + env->mvp->CP0_MVPControl = newval;
  586 +}
  587 +
  588 +void do_mtc0_vpecontrol (void)
  589 +{
  590 + uint32_t mask;
  591 + uint32_t newval;
  592 +
  593 + mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
  594 + (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
  595 + newval = (env->CP0_VPEControl & ~mask) | (T0 & mask);
  596 +
  597 + /* Yield scheduler intercept not implemented. */
  598 + /* Gating storage scheduler intercept not implemented. */
  599 +
  600 + // TODO: Enable/disable TCs.
  601 +
  602 + env->CP0_VPEControl = newval;
  603 +}
  604 +
  605 +void do_mtc0_vpeconf0 (void)
  606 +{
  607 + uint32_t mask = 0;
  608 + uint32_t newval;
  609 +
  610 + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
  611 + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
  612 + mask |= (0xff << CP0VPEC0_XTC);
  613 + mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
  614 + }
  615 + newval = (env->CP0_VPEConf0 & ~mask) | (T0 & mask);
  616 +
  617 + // TODO: TC exclusive handling due to ERL/EXL.
  618 +
  619 + env->CP0_VPEConf0 = newval;
  620 +}
  621 +
  622 +void do_mtc0_vpeconf1 (void)
  623 +{
  624 + uint32_t mask = 0;
  625 + uint32_t newval;
  626 +
  627 + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
  628 + mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
  629 + (0xff << CP0VPEC1_NCP1);
  630 + newval = (env->CP0_VPEConf1 & ~mask) | (T0 & mask);
  631 +
  632 + /* UDI not implemented. */
  633 + /* CP2 not implemented. */
  634 +
  635 + // TODO: Handle FPU (CP1) binding.
  636 +
  637 + env->CP0_VPEConf1 = newval;
  638 +}
  639 +
  640 +void do_mtc0_yqmask (void)
  641 +{
  642 + /* Yield qualifier inputs not implemented. */
  643 + env->CP0_YQMask = 0x00000000;
  644 +}
  645 +
  646 +void do_mtc0_vpeopt (void)
  647 +{
  648 + env->CP0_VPEOpt = T0 & 0x0000ffff;
  649 +}
  650 +
  651 +void do_mtc0_entrylo0 (void)
  652 +{
  653 + /* Large physaddr (PABITS) not implemented */
  654 + /* 1k pages not implemented */
  655 + env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
  656 +}
  657 +
  658 +void do_mtc0_tcstatus (void)
  659 +{
  660 + uint32_t mask = env->CP0_TCStatus_rw_bitmask;
  661 + uint32_t newval;
  662 +
  663 + newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (T0 & mask);
  664 +
  665 + // TODO: Sync with CP0_Status.
  666 +
  667 + env->CP0_TCStatus[env->current_tc] = newval;
  668 +}
  669 +
  670 +void do_mttc0_tcstatus (void)
  671 +{
  672 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  673 +
  674 + // TODO: Sync with CP0_Status.
  675 +
  676 + env->CP0_TCStatus[other_tc] = T0;
  677 +}
  678 +
  679 +void do_mtc0_tcbind (void)
  680 +{
  681 + uint32_t mask = (1 << CP0TCBd_TBE);
  682 + uint32_t newval;
  683 +
  684 + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
  685 + mask |= (1 << CP0TCBd_CurVPE);
  686 + newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (T0 & mask);
  687 + env->CP0_TCBind[env->current_tc] = newval;
  688 +}
  689 +
  690 +void do_mttc0_tcbind (void)
  691 +{
  692 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  693 + uint32_t mask = (1 << CP0TCBd_TBE);
  694 + uint32_t newval;
  695 +
  696 + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
  697 + mask |= (1 << CP0TCBd_CurVPE);
  698 + newval = (env->CP0_TCBind[other_tc] & ~mask) | (T0 & mask);
  699 + env->CP0_TCBind[other_tc] = newval;
  700 +}
  701 +
  702 +void do_mtc0_tcrestart (void)
  703 +{
  704 + env->PC[env->current_tc] = T0;
  705 + env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS);
  706 + env->CP0_LLAddr = 0ULL;
  707 + /* MIPS16 not implemented. */
  708 +}
  709 +
  710 +void do_mttc0_tcrestart (void)
  711 +{
  712 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  713 +
  714 + env->PC[other_tc] = T0;
  715 + env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS);
  716 + env->CP0_LLAddr = 0ULL;
  717 + /* MIPS16 not implemented. */
  718 +}
  719 +
  720 +void do_mtc0_tchalt (void)
  721 +{
  722 + env->CP0_TCHalt[env->current_tc] = T0 & 0x1;
  723 +
  724 + // TODO: Halt TC / Restart (if allocated+active) TC.
  725 +}
  726 +
  727 +void do_mttc0_tchalt (void)
  728 +{
  729 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  730 +
  731 + // TODO: Halt TC / Restart (if allocated+active) TC.
  732 +
  733 + env->CP0_TCHalt[other_tc] = T0;
  734 +}
  735 +
  736 +void do_mtc0_tccontext (void)
  737 +{
  738 + env->CP0_TCContext[env->current_tc] = T0;
  739 +}
  740 +
  741 +void do_mttc0_tccontext (void)
  742 +{
  743 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  744 +
  745 + env->CP0_TCContext[other_tc] = T0;
  746 +}
  747 +
  748 +void do_mtc0_tcschedule (void)
  749 +{
  750 + env->CP0_TCSchedule[env->current_tc] = T0;
  751 +}
  752 +
  753 +void do_mttc0_tcschedule (void)
  754 +{
  755 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  756 +
  757 + env->CP0_TCSchedule[other_tc] = T0;
  758 +}
  759 +
  760 +void do_mtc0_tcschefback (void)
  761 +{
  762 + env->CP0_TCScheFBack[env->current_tc] = T0;
  763 +}
  764 +
  765 +void do_mttc0_tcschefback (void)
  766 +{
  767 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  768 +
  769 + env->CP0_TCScheFBack[other_tc] = T0;
  770 +}
  771 +
  772 +void do_mtc0_entrylo1 (void)
  773 +{
  774 + /* Large physaddr (PABITS) not implemented */
  775 + /* 1k pages not implemented */
  776 + env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
  777 +}
  778 +
  779 +void do_mtc0_context (void)
  780 +{
  781 + env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
  782 +}
  783 +
  784 +void do_mtc0_pagemask (void)
  785 +{
  786 + /* 1k pages not implemented */
  787 + env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
  788 +}
  789 +
  790 +void do_mtc0_pagegrain (void)
  791 +{
  792 + /* SmartMIPS not implemented */
  793 + /* Large physaddr (PABITS) not implemented */
  794 + /* 1k pages not implemented */
  795 + env->CP0_PageGrain = 0;
  796 +}
  797 +
  798 +void do_mtc0_wired (void)
  799 +{
  800 + env->CP0_Wired = T0 % env->tlb->nb_tlb;
  801 +}
  802 +
  803 +void do_mtc0_srsconf0 (void)
  804 +{
  805 + env->CP0_SRSConf0 |= T0 & env->CP0_SRSConf0_rw_bitmask;
  806 +}
  807 +
  808 +void do_mtc0_srsconf1 (void)
  809 +{
  810 + env->CP0_SRSConf1 |= T0 & env->CP0_SRSConf1_rw_bitmask;
  811 +}
  812 +
  813 +void do_mtc0_srsconf2 (void)
  814 +{
  815 + env->CP0_SRSConf2 |= T0 & env->CP0_SRSConf2_rw_bitmask;
  816 +}
  817 +
  818 +void do_mtc0_srsconf3 (void)
  819 +{
  820 + env->CP0_SRSConf3 |= T0 & env->CP0_SRSConf3_rw_bitmask;
  821 +}
  822 +
  823 +void do_mtc0_srsconf4 (void)
  824 +{
  825 + env->CP0_SRSConf4 |= T0 & env->CP0_SRSConf4_rw_bitmask;
  826 +}
  827 +
  828 +void do_mtc0_hwrena (void)
  829 +{
  830 + env->CP0_HWREna = T0 & 0x0000000F;
  831 +}
  832 +
  833 +void do_mtc0_count (void)
  834 +{
  835 + cpu_mips_store_count(env, T0);
  836 +}
  837 +
  838 +void do_mtc0_entryhi (void)
  839 +{
  840 + target_ulong old, val;
  841 +
  842 + /* 1k pages not implemented */
  843 + val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
  844 +#if defined(TARGET_MIPS64)
  845 + val &= env->SEGMask;
  846 +#endif
  847 + old = env->CP0_EntryHi;
  848 + env->CP0_EntryHi = val;
  849 + if (env->CP0_Config3 & (1 << CP0C3_MT)) {
  850 + uint32_t tcst = env->CP0_TCStatus[env->current_tc] & ~0xff;
  851 + env->CP0_TCStatus[env->current_tc] = tcst | (val & 0xff);
  852 + }
  853 + /* If the ASID changes, flush qemu's TLB. */
  854 + if ((old & 0xFF) != (val & 0xFF))
  855 + cpu_mips_tlb_flush(env, 1);
  856 +}
  857 +
  858 +void do_mttc0_entryhi(void)
  859 +{
  860 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  861 +
  862 + env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (T0 & ~0xff);
  863 + env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (T0 & 0xff);
  864 +}
  865 +
  866 +void do_mtc0_compare (void)
  867 +{
  868 + cpu_mips_store_compare(env, T0);
  869 +}
  870 +
  871 +void do_mtc0_status (void)
  872 +{
  873 + uint32_t val, old;
  874 + uint32_t mask = env->CP0_Status_rw_bitmask;
  875 +
  876 + val = T0 & mask;
  877 + old = env->CP0_Status;
  878 + env->CP0_Status = (env->CP0_Status & ~mask) | val;
  879 + compute_hflags(env);
  880 + if (loglevel & CPU_LOG_EXEC)
  881 + do_mtc0_status_debug(old, val);
  882 + cpu_mips_update_irq(env);
  883 +}
  884 +
  885 +void do_mttc0_status(void)
  886 +{
  887 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  888 + uint32_t tcstatus = env->CP0_TCStatus[other_tc];
  889 +
  890 + env->CP0_Status = T0 & ~0xf1000018;
  891 + tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (T0 & (0xf << CP0St_CU0));
  892 + tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((T0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
  893 + tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((T0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
  894 + env->CP0_TCStatus[other_tc] = tcstatus;
  895 +}
  896 +
  897 +void do_mtc0_intctl (void)
  898 +{
  899 + /* vectored interrupts not implemented, no performance counters. */
  900 + env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (T0 & 0x000002e0);
  901 +}
  902 +
  903 +void do_mtc0_srsctl (void)
  904 +{
  905 + uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
  906 + env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (T0 & mask);
  907 +}
  908 +
  909 +void do_mtc0_cause (void)
  910 +{
  911 + uint32_t mask = 0x00C00300;
  912 + uint32_t old = env->CP0_Cause;
  913 +
  914 + if (env->insn_flags & ISA_MIPS32R2)
  915 + mask |= 1 << CP0Ca_DC;
  916 +
  917 + env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);
  918 +
  919 + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
  920 + if (env->CP0_Cause & (1 << CP0Ca_DC))
  921 + cpu_mips_stop_count(env);
  922 + else
  923 + cpu_mips_start_count(env);
  924 + }
  925 +
  926 + /* Handle the software interrupt as an hardware one, as they
  927 + are very similar */
  928 + if (T0 & CP0Ca_IP_mask) {
  929 + cpu_mips_update_irq(env);
  930 + }
  931 +}
  932 +
  933 +void do_mtc0_ebase (void)
  934 +{
  935 + /* vectored interrupts not implemented */
  936 + /* Multi-CPU not implemented */
  937 + env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
  938 +}
  939 +
  940 +void do_mtc0_config0 (void)
  941 +{
  942 + env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007);
  943 +}
  944 +
  945 +void do_mtc0_config2 (void)
  946 +{
  947 + /* tertiary/secondary caches not implemented */
  948 + env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
  949 +}
  950 +
  951 +void do_mtc0_watchlo (uint32_t sel)
  952 +{
  953 + /* Watch exceptions for instructions, data loads, data stores
  954 + not implemented. */
  955 + env->CP0_WatchLo[sel] = (T0 & ~0x7);
  956 +}
  957 +
  958 +void do_mtc0_watchhi (uint32_t sel)
  959 +{
  960 + env->CP0_WatchHi[sel] = (T0 & 0x40FF0FF8);
  961 + env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & T0 & 0x7);
  962 +}
  963 +
  964 +void do_mtc0_xcontext (void)
  965 +{
  966 + target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
  967 + env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask);
  968 +}
  969 +
  970 +void do_mtc0_framemask (void)
  971 +{
  972 + env->CP0_Framemask = T0; /* XXX */
  973 +}
  974 +
  975 +void do_mtc0_debug (void)
  976 +{
  977 + env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
  978 + if (T0 & (1 << CP0DB_DM))
  979 + env->hflags |= MIPS_HFLAG_DM;
  980 + else
  981 + env->hflags &= ~MIPS_HFLAG_DM;
  982 +}
  983 +
  984 +void do_mttc0_debug(void)
  985 +{
  986 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  987 +
  988 + /* XXX: Might be wrong, check with EJTAG spec. */
  989 + env->CP0_Debug_tcstatus[other_tc] = T0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
  990 + env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
  991 + (T0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
  992 +}
  993 +
  994 +void do_mtc0_performance0 (void)
  995 +{
  996 + env->CP0_Performance0 = T0 & 0x000007ff;
  997 +}
  998 +
  999 +void do_mtc0_taglo (void)
  1000 +{
  1001 + env->CP0_TagLo = T0 & 0xFFFFFCF6;
  1002 +}
  1003 +
  1004 +void do_mtc0_datalo (void)
  1005 +{
  1006 + env->CP0_DataLo = T0; /* XXX */
  1007 +}
  1008 +
  1009 +void do_mtc0_taghi (void)
  1010 +{
  1011 + env->CP0_TagHi = T0; /* XXX */
  1012 +}
  1013 +
  1014 +void do_mtc0_datahi (void)
  1015 +{
  1016 + env->CP0_DataHi = T0; /* XXX */
  1017 +}
  1018 +
373 1019 void do_mtc0_status_debug(uint32_t old, uint32_t val)
374 1020 {
375 1021 fprintf(logfile, "Status %08x (%08x) => %08x (%08x) Cause %08x",
... ... @@ -388,7 +1034,144 @@ void do_mtc0_status_irqraise_debug(void)
388 1034 {
389 1035 fprintf(logfile, "Raise pending IRQs\n");
390 1036 }
  1037 +#endif /* !CONFIG_USER_ONLY */
  1038 +
  1039 +/* MIPS MT functions */
  1040 +void do_mftgpr(uint32_t sel)
  1041 +{
  1042 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1043 +
  1044 + T0 = env->gpr[other_tc][sel];
  1045 +}
  1046 +
  1047 +void do_mftlo(uint32_t sel)
  1048 +{
  1049 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1050 +
  1051 + T0 = env->LO[other_tc][sel];
  1052 +}
  1053 +
  1054 +void do_mfthi(uint32_t sel)
  1055 +{
  1056 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1057 +
  1058 + T0 = env->HI[other_tc][sel];
  1059 +}
  1060 +
  1061 +void do_mftacx(uint32_t sel)
  1062 +{
  1063 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1064 +
  1065 + T0 = env->ACX[other_tc][sel];
  1066 +}
  1067 +
  1068 +void do_mftdsp(void)
  1069 +{
  1070 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1071 +
  1072 + T0 = env->DSPControl[other_tc];
  1073 +}
391 1074  
  1075 +void do_mttgpr(uint32_t sel)
  1076 +{
  1077 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1078 +
  1079 + T0 = env->gpr[other_tc][sel];
  1080 +}
  1081 +
  1082 +void do_mttlo(uint32_t sel)
  1083 +{
  1084 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1085 +
  1086 + T0 = env->LO[other_tc][sel];
  1087 +}
  1088 +
  1089 +void do_mtthi(uint32_t sel)
  1090 +{
  1091 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1092 +
  1093 + T0 = env->HI[other_tc][sel];
  1094 +}
  1095 +
  1096 +void do_mttacx(uint32_t sel)
  1097 +{
  1098 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1099 +
  1100 + T0 = env->ACX[other_tc][sel];
  1101 +}
  1102 +
  1103 +void do_mttdsp(void)
  1104 +{
  1105 + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
  1106 +
  1107 + T0 = env->DSPControl[other_tc];
  1108 +}
  1109 +
  1110 +/* MIPS MT functions */
  1111 +void do_dmt(void)
  1112 +{
  1113 + // TODO
  1114 + T0 = 0;
  1115 + // rt = T0
  1116 +}
  1117 +
  1118 +void do_emt(void)
  1119 +{
  1120 + // TODO
  1121 + T0 = 0;
  1122 + // rt = T0
  1123 +}
  1124 +
  1125 +void do_dvpe(void)
  1126 +{
  1127 + // TODO
  1128 + T0 = 0;
  1129 + // rt = T0
  1130 +}
  1131 +
  1132 +void do_evpe(void)
  1133 +{
  1134 + // TODO
  1135 + T0 = 0;
  1136 + // rt = T0
  1137 +}
  1138 +
  1139 +void do_fork(void)
  1140 +{
  1141 + // T0 = rt, T1 = rs
  1142 + T0 = 0;
  1143 + // TODO: store to TC register
  1144 +}
  1145 +
  1146 +void do_yield(void)
  1147 +{
  1148 + if (T0 < 0) {
  1149 + /* No scheduling policy implemented. */
  1150 + if (T0 != -2) {
  1151 + if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
  1152 + env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) {
  1153 + env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
  1154 + env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
  1155 + do_raise_exception(EXCP_THREAD);
  1156 + }
  1157 + }
  1158 + } else if (T0 == 0) {
  1159 + if (0 /* TODO: TC underflow */) {
  1160 + env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
  1161 + do_raise_exception(EXCP_THREAD);
  1162 + } else {
  1163 + // TODO: Deallocate TC
  1164 + }
  1165 + } else if (T0 > 0) {
  1166 + /* Yield qualifier inputs not implemented. */
  1167 + env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
  1168 + env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
  1169 + do_raise_exception(EXCP_THREAD);
  1170 + }
  1171 + T0 = env->CP0_YQMask;
  1172 +}
  1173 +
  1174 +/* CP1 functions */
392 1175 void fpu_handle_exception(void)
393 1176 {
394 1177 #ifdef CONFIG_SOFTFLOAT
... ... @@ -426,6 +1209,7 @@ void fpu_handle_exception(void)
426 1209 #endif
427 1210 }
428 1211  
  1212 +#ifndef CONFIG_USER_ONLY
429 1213 /* TLB management */
430 1214 void cpu_mips_tlb_flush (CPUState *env, int flush_global)
431 1215 {
... ... @@ -679,7 +1463,7 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
679 1463 else
680 1464 do_raise_exception(EXCP_DBE);
681 1465 }
682   -#endif
  1466 +#endif /* !CONFIG_USER_ONLY */
683 1467  
684 1468 /* Complex FPU operations which may need stack space. */
685 1469  
... ... @@ -703,7 +1487,7 @@ unsigned int ieee_rm[] = {
703 1487 #define RESTORE_ROUNDING_MODE \
704 1488 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
705 1489  
706   -void do_cfc1 (int reg)
  1490 +void do_cfc1 (uint32_t reg)
707 1491 {
708 1492 switch (reg) {
709 1493 case 0:
... ... @@ -724,7 +1508,7 @@ void do_cfc1 (int reg)
724 1508 }
725 1509 }
726 1510  
727   -void do_ctc1 (int reg)
  1511 +void do_ctc1 (uint32_t reg)
728 1512 {
729 1513 switch(reg) {
730 1514 case 25:
... ...
target-mips/translate.c
  View file @f1aa632
... ... @@ -2583,6 +2583,7 @@ fail:
2583 2583 }
2584 2584  
2585 2585 /* CP0 (MMU and control) */
  2586 +#ifndef CONFIG_USER_ONLY
2586 2587 static inline void gen_mfc0_load32 (TCGv t, target_ulong off)
2587 2588 {
2588 2589 TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
... ... @@ -2601,6 +2602,24 @@ static inline void gen_mfc0_load64 (TCGv t, target_ulong off)
2601 2602 tcg_temp_free(r_tmp);
2602 2603 }
2603 2604  
  2605 +static inline void gen_mtc0_store32 (TCGv t, target_ulong off)
  2606 +{
  2607 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
  2608 +
  2609 + tcg_gen_trunc_tl_i32(r_tmp, t);
  2610 + tcg_gen_st_i32(r_tmp, cpu_env, off);
  2611 + tcg_temp_free(r_tmp);
  2612 +}
  2613 +
  2614 +static inline void gen_mtc0_store64 (TCGv t, target_ulong off)
  2615 +{
  2616 + TCGv r_tmp = tcg_temp_new(TCG_TYPE_I64);
  2617 +
  2618 + tcg_gen_ext_tl_i64(r_tmp, t);
  2619 + tcg_gen_st_i64(r_tmp, cpu_env, off);
  2620 + tcg_temp_free(r_tmp);
  2621 +}
  2622 +
2604 2623 static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2605 2624 {
2606 2625 const char *rn = "invalid";
... ... @@ -2617,17 +2636,17 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2617 2636 break;
2618 2637 case 1:
2619 2638 check_insn(env, ctx, ASE_MT);
2620   - gen_op_mfc0_mvpcontrol();
  2639 + tcg_gen_helper_0_0(do_mfc0_mvpcontrol);
2621 2640 rn = "MVPControl";
2622 2641 break;
2623 2642 case 2:
2624 2643 check_insn(env, ctx, ASE_MT);
2625   - gen_op_mfc0_mvpconf0();
  2644 + tcg_gen_helper_0_0(do_mfc0_mvpconf0);
2626 2645 rn = "MVPConf0";
2627 2646 break;
2628 2647 case 3:
2629 2648 check_insn(env, ctx, ASE_MT);
2630   - gen_op_mfc0_mvpconf1();
  2649 + tcg_gen_helper_0_0(do_mfc0_mvpconf1);
2631 2650 rn = "MVPConf1";
2632 2651 break;
2633 2652 default:
... ... @@ -2637,7 +2656,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2637 2656 case 1:
2638 2657 switch (sel) {
2639 2658 case 0:
2640   - gen_op_mfc0_random();
  2659 + tcg_gen_helper_0_0(do_mfc0_random);
2641 2660 rn = "Random";
2642 2661 break;
2643 2662 case 1:
... ... @@ -2688,37 +2707,37 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2688 2707 break;
2689 2708 case 1:
2690 2709 check_insn(env, ctx, ASE_MT);
2691   - gen_op_mfc0_tcstatus();
  2710 + tcg_gen_helper_0_0(do_mfc0_tcstatus);
2692 2711 rn = "TCStatus";
2693 2712 break;
2694 2713 case 2:
2695 2714 check_insn(env, ctx, ASE_MT);
2696   - gen_op_mfc0_tcbind();
  2715 + tcg_gen_helper_0_0(do_mfc0_tcbind);
2697 2716 rn = "TCBind";
2698 2717 break;
2699 2718 case 3:
2700 2719 check_insn(env, ctx, ASE_MT);
2701   - gen_op_mfc0_tcrestart();
  2720 + tcg_gen_helper_0_0(do_mfc0_tcrestart);
2702 2721 rn = "TCRestart";
2703 2722 break;
2704 2723 case 4:
2705 2724 check_insn(env, ctx, ASE_MT);
2706   - gen_op_mfc0_tchalt();
  2725 + tcg_gen_helper_0_0(do_mfc0_tchalt);
2707 2726 rn = "TCHalt";
2708 2727 break;
2709 2728 case 5:
2710 2729 check_insn(env, ctx, ASE_MT);
2711   - gen_op_mfc0_tccontext();
  2730 + tcg_gen_helper_0_0(do_mfc0_tccontext);
2712 2731 rn = "TCContext";
2713 2732 break;
2714 2733 case 6:
2715 2734 check_insn(env, ctx, ASE_MT);
2716   - gen_op_mfc0_tcschedule();
  2735 + tcg_gen_helper_0_0(do_mfc0_tcschedule);
2717 2736 rn = "TCSchedule";
2718 2737 break;
2719 2738 case 7:
2720 2739 check_insn(env, ctx, ASE_MT);
2721   - gen_op_mfc0_tcschefback();
  2740 + tcg_gen_helper_0_0(do_mfc0_tcschefback);
2722 2741 rn = "TCScheFBack";
2723 2742 break;
2724 2743 default:
... ... @@ -2744,7 +2763,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2744 2763 rn = "Context";
2745 2764 break;
2746 2765 case 1:
2747   -// gen_op_mfc0_contextconfig(); /* SmartMIPS ASE */
  2766 +// tcg_gen_helper_0_0(do_mfc0_contextconfig); /* SmartMIPS ASE */
2748 2767 rn = "ContextConfig";
2749 2768 // break;
2750 2769 default:
... ... @@ -2826,7 +2845,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2826 2845 case 9:
2827 2846 switch (sel) {
2828 2847 case 0:
2829   - gen_op_mfc0_count();
  2848 + tcg_gen_helper_0_0(do_mfc0_count);
2830 2849 rn = "Count";
2831 2850 break;
2832 2851 /* 6,7 are implementation dependent */
... ... @@ -2952,7 +2971,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2952 2971 case 17:
2953 2972 switch (sel) {
2954 2973 case 0:
2955   - gen_op_mfc0_lladdr();
  2974 + tcg_gen_helper_0_0(do_mfc0_lladdr);
2956 2975 rn = "LLAddr";
2957 2976 break;
2958 2977 default:
... ... @@ -2962,7 +2981,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2962 2981 case 18:
2963 2982 switch (sel) {
2964 2983 case 0 ... 7:
2965   - gen_op_mfc0_watchlo(sel);
  2984 + tcg_gen_helper_0_1i(do_mfc0_watchlo, sel);
2966 2985 rn = "WatchLo";
2967 2986 break;
2968 2987 default:
... ... @@ -2972,7 +2991,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
2972 2991 case 19:
2973 2992 switch (sel) {
2974 2993 case 0 ...7:
2975   - gen_op_mfc0_watchhi(sel);
  2994 + tcg_gen_helper_0_1i(do_mfc0_watchhi, sel);
2976 2995 rn = "WatchHi";
2977 2996 break;
2978 2997 default:
... ... @@ -3011,23 +3030,23 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3011 3030 case 23:
3012 3031 switch (sel) {
3013 3032 case 0:
3014   - gen_op_mfc0_debug(); /* EJTAG support */
  3033 + tcg_gen_helper_0_0(do_mfc0_debug); /* EJTAG support */
3015 3034 rn = "Debug";
3016 3035 break;
3017 3036 case 1:
3018   -// gen_op_mfc0_tracecontrol(); /* PDtrace support */
  3037 +// tcg_gen_helper_0_0(do_mfc0_tracecontrol); /* PDtrace support */
3019 3038 rn = "TraceControl";
3020 3039 // break;
3021 3040 case 2:
3022   -// gen_op_mfc0_tracecontrol2(); /* PDtrace support */
  3041 +// tcg_gen_helper_0_0(do_mfc0_tracecontrol2); /* PDtrace support */
3023 3042 rn = "TraceControl2";
3024 3043 // break;
3025 3044 case 3:
3026   -// gen_op_mfc0_usertracedata(); /* PDtrace support */
  3045 +// tcg_gen_helper_0_0(do_mfc0_usertracedata); /* PDtrace support */
3027 3046 rn = "UserTraceData";
3028 3047 // break;
3029 3048 case 4:
3030   -// gen_op_mfc0_debug(); /* PDtrace support */
  3049 +// tcg_gen_helper_0_0(do_mfc0_debug); /* PDtrace support */
3031 3050 rn = "TraceBPC";
3032 3051 // break;
3033 3052 default:
... ... @@ -3053,31 +3072,31 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3053 3072 rn = "Performance0";
3054 3073 break;
3055 3074 case 1:
3056   -// gen_op_mfc0_performance1();
  3075 +// tcg_gen_helper_0_0(do_mfc0_performance1);
3057 3076 rn = "Performance1";
3058 3077 // break;
3059 3078 case 2:
3060   -// gen_op_mfc0_performance2();
  3079 +// tcg_gen_helper_0_0(do_mfc0_performance2);
3061 3080 rn = "Performance2";
3062 3081 // break;
3063 3082 case 3:
3064   -// gen_op_mfc0_performance3();
  3083 +// tcg_gen_helper_0_0(do_mfc0_performance3);
3065 3084 rn = "Performance3";
3066 3085 // break;
3067 3086 case 4:
3068   -// gen_op_mfc0_performance4();
  3087 +// tcg_gen_helper_0_0(do_mfc0_performance4);
3069 3088 rn = "Performance4";
3070 3089 // break;
3071 3090 case 5:
3072   -// gen_op_mfc0_performance5();
  3091 +// tcg_gen_helper_0_0(do_mfc0_performance5);
3073 3092 rn = "Performance5";
3074 3093 // break;
3075 3094 case 6:
3076   -// gen_op_mfc0_performance6();
  3095 +// tcg_gen_helper_0_0(do_mfc0_performance6);
3077 3096 rn = "Performance6";
3078 3097 // break;
3079 3098 case 7:
3080   -// gen_op_mfc0_performance7();
  3099 +// tcg_gen_helper_0_0(do_mfc0_performance7);
3081 3100 rn = "Performance7";
3082 3101 // break;
3083 3102 default:
... ... @@ -3191,12 +3210,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3191 3210 case 0:
3192 3211 switch (sel) {
3193 3212 case 0:
3194   - gen_op_mtc0_index();
  3213 + tcg_gen_helper_0_0(do_mtc0_index);
3195 3214 rn = "Index";
3196 3215 break;
3197 3216 case 1:
3198 3217 check_insn(env, ctx, ASE_MT);
3199   - gen_op_mtc0_mvpcontrol();
  3218 + tcg_gen_helper_0_0(do_mtc0_mvpcontrol);
3200 3219 rn = "MVPControl";
3201 3220 break;
3202 3221 case 2:
... ... @@ -3221,37 +3240,37 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3221 3240 break;
3222 3241 case 1:
3223 3242 check_insn(env, ctx, ASE_MT);
3224   - gen_op_mtc0_vpecontrol();
  3243 + tcg_gen_helper_0_0(do_mtc0_vpecontrol);
3225 3244 rn = "VPEControl";
3226 3245 break;
3227 3246 case 2:
3228 3247 check_insn(env, ctx, ASE_MT);
3229   - gen_op_mtc0_vpeconf0();
  3248 + tcg_gen_helper_0_0(do_mtc0_vpeconf0);
3230 3249 rn = "VPEConf0";
3231 3250 break;
3232 3251 case 3:
3233 3252 check_insn(env, ctx, ASE_MT);
3234   - gen_op_mtc0_vpeconf1();
  3253 + tcg_gen_helper_0_0(do_mtc0_vpeconf1);
3235 3254 rn = "VPEConf1";
3236 3255 break;
3237 3256 case 4:
3238 3257 check_insn(env, ctx, ASE_MT);
3239   - gen_op_mtc0_yqmask();
  3258 + tcg_gen_helper_0_0(do_mtc0_yqmask);
3240 3259 rn = "YQMask";
3241 3260 break;
3242 3261 case 5:
3243 3262 check_insn(env, ctx, ASE_MT);
3244   - gen_op_mtc0_vpeschedule();
  3263 + gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_VPESchedule));
3245 3264 rn = "VPESchedule";
3246 3265 break;
3247 3266 case 6:
3248 3267 check_insn(env, ctx, ASE_MT);
3249   - gen_op_mtc0_vpeschefback();
  3268 + gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_VPEScheFBack));
3250 3269 rn = "VPEScheFBack";
3251 3270 break;
3252 3271 case 7:
3253 3272 check_insn(env, ctx, ASE_MT);
3254   - gen_op_mtc0_vpeopt();
  3273 + tcg_gen_helper_0_0(do_mtc0_vpeopt);
3255 3274 rn = "VPEOpt";
3256 3275 break;
3257 3276 default:
... ... @@ -3261,42 +3280,42 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3261 3280 case 2:
3262 3281 switch (sel) {
3263 3282 case 0:
3264   - gen_op_mtc0_entrylo0();
  3283 + tcg_gen_helper_0_0(do_mtc0_entrylo0);
3265 3284 rn = "EntryLo0";
3266 3285 break;
3267 3286 case 1:
3268 3287 check_insn(env, ctx, ASE_MT);
3269   - gen_op_mtc0_tcstatus();
  3288 + tcg_gen_helper_0_0(do_mtc0_tcstatus);
3270 3289 rn = "TCStatus";
3271 3290 break;
3272 3291 case 2:
3273 3292 check_insn(env, ctx, ASE_MT);
3274   - gen_op_mtc0_tcbind();
  3293 + tcg_gen_helper_0_0(do_mtc0_tcbind);
3275 3294 rn = "TCBind";
3276 3295 break;
3277 3296 case 3:
3278 3297 check_insn(env, ctx, ASE_MT);
3279   - gen_op_mtc0_tcrestart();
  3298 + tcg_gen_helper_0_0(do_mtc0_tcrestart);
3280 3299 rn = "TCRestart";
3281 3300 break;
3282 3301 case 4:
3283 3302 check_insn(env, ctx, ASE_MT);
3284   - gen_op_mtc0_tchalt();
  3303 + tcg_gen_helper_0_0(do_mtc0_tchalt);
3285 3304 rn = "TCHalt";
3286 3305 break;
3287 3306 case 5:
3288 3307 check_insn(env, ctx, ASE_MT);
3289   - gen_op_mtc0_tccontext();
  3308 + tcg_gen_helper_0_0(do_mtc0_tccontext);
3290 3309 rn = "TCContext";
3291 3310 break;
3292 3311 case 6:
3293 3312 check_insn(env, ctx, ASE_MT);
3294   - gen_op_mtc0_tcschedule();
  3313 + tcg_gen_helper_0_0(do_mtc0_tcschedule);
3295 3314 rn = "TCSchedule";
3296 3315 break;
3297 3316 case 7:
3298 3317 check_insn(env, ctx, ASE_MT);
3299   - gen_op_mtc0_tcschefback();
  3318 + tcg_gen_helper_0_0(do_mtc0_tcschefback);
3300 3319 rn = "TCScheFBack";
3301 3320 break;
3302 3321 default:
... ... @@ -3306,7 +3325,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3306 3325 case 3:
3307 3326 switch (sel) {
3308 3327 case 0:
3309   - gen_op_mtc0_entrylo1();
  3328 + tcg_gen_helper_0_0(do_mtc0_entrylo1);
3310 3329 rn = "EntryLo1";
3311 3330 break;
3312 3331 default:
... ... @@ -3316,11 +3335,11 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3316 3335 case 4:
3317 3336 switch (sel) {
3318 3337 case 0:
3319   - gen_op_mtc0_context();
  3338 + tcg_gen_helper_0_0(do_mtc0_context);
3320 3339 rn = "Context";
3321 3340 break;
3322 3341 case 1:
3323   -// gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
  3342 +// tcg_gen_helper_0_0(do_mtc0_contextconfig); /* SmartMIPS ASE */
3324 3343 rn = "ContextConfig";
3325 3344 // break;
3326 3345 default:
... ... @@ -3330,12 +3349,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3330 3349 case 5:
3331 3350 switch (sel) {
3332 3351 case 0:
3333   - gen_op_mtc0_pagemask();
  3352 + tcg_gen_helper_0_0(do_mtc0_pagemask);
3334 3353 rn = "PageMask";
3335 3354 break;
3336 3355 case 1:
3337 3356 check_insn(env, ctx, ISA_MIPS32R2);
3338   - gen_op_mtc0_pagegrain();
  3357 + tcg_gen_helper_0_0(do_mtc0_pagegrain);
3339 3358 rn = "PageGrain";
3340 3359 break;
3341 3360 default:
... ... @@ -3345,32 +3364,32 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3345 3364 case 6:
3346 3365 switch (sel) {
3347 3366 case 0:
3348   - gen_op_mtc0_wired();
  3367 + tcg_gen_helper_0_0(do_mtc0_wired);
3349 3368 rn = "Wired";
3350 3369 break;
3351 3370 case 1:
3352 3371 check_insn(env, ctx, ISA_MIPS32R2);
3353   - gen_op_mtc0_srsconf0();
  3372 + tcg_gen_helper_0_0(do_mtc0_srsconf0);
3354 3373 rn = "SRSConf0";
3355 3374 break;
3356 3375 case 2:
3357 3376 check_insn(env, ctx, ISA_MIPS32R2);
3358   - gen_op_mtc0_srsconf1();
  3377 + tcg_gen_helper_0_0(do_mtc0_srsconf1);
3359 3378 rn = "SRSConf1";
3360 3379 break;
3361 3380 case 3:
3362 3381 check_insn(env, ctx, ISA_MIPS32R2);
3363   - gen_op_mtc0_srsconf2();
  3382 + tcg_gen_helper_0_0(do_mtc0_srsconf2);
3364 3383 rn = "SRSConf2";
3365 3384 break;
3366 3385 case 4:
3367 3386 check_insn(env, ctx, ISA_MIPS32R2);
3368   - gen_op_mtc0_srsconf3();
  3387 + tcg_gen_helper_0_0(do_mtc0_srsconf3);
3369 3388 rn = "SRSConf3";
3370 3389 break;
3371 3390 case 5:
3372 3391 check_insn(env, ctx, ISA_MIPS32R2);
3373   - gen_op_mtc0_srsconf4();
  3392 + tcg_gen_helper_0_0(do_mtc0_srsconf4);
3374 3393 rn = "SRSConf4";
3375 3394 break;
3376 3395 default:
... ... @@ -3381,7 +3400,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3381 3400 switch (sel) {
3382 3401 case 0:
3383 3402 check_insn(env, ctx, ISA_MIPS32R2);
3384   - gen_op_mtc0_hwrena();
  3403 + tcg_gen_helper_0_0(do_mtc0_hwrena);
3385 3404 rn = "HWREna";
3386 3405 break;
3387 3406 default:
... ... @@ -3395,7 +3414,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3395 3414 case 9:
3396 3415 switch (sel) {
3397 3416 case 0:
3398   - gen_op_mtc0_count();
  3417 + tcg_gen_helper_0_0(do_mtc0_count);
3399 3418 rn = "Count";
3400 3419 break;
3401 3420 /* 6,7 are implementation dependent */
... ... @@ -3408,7 +3427,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3408 3427 case 10:
3409 3428 switch (sel) {
3410 3429 case 0:
3411   - gen_op_mtc0_entryhi();
  3430 + tcg_gen_helper_0_0(do_mtc0_entryhi);
3412 3431 rn = "EntryHi";
3413 3432 break;
3414 3433 default:
... ... @@ -3418,7 +3437,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3418 3437 case 11:
3419 3438 switch (sel) {
3420 3439 case 0:
3421   - gen_op_mtc0_compare();
  3440 + tcg_gen_helper_0_0(do_mtc0_compare);
3422 3441 rn = "Compare";
3423 3442 break;
3424 3443 /* 6,7 are implementation dependent */
... ... @@ -3431,7 +3450,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3431 3450 case 12:
3432 3451 switch (sel) {
3433 3452 case 0:
3434   - gen_op_mtc0_status();
  3453 + tcg_gen_helper_0_0(do_mtc0_status);
3435 3454 /* BS_STOP isn't good enough here, hflags may have changed. */
3436 3455 gen_save_pc(ctx->pc + 4);
3437 3456 ctx->bstate = BS_EXCP;
... ... @@ -3439,21 +3458,21 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3439 3458 break;
3440 3459 case 1:
3441 3460 check_insn(env, ctx, ISA_MIPS32R2);
3442   - gen_op_mtc0_intctl();
  3461 + tcg_gen_helper_0_0(do_mtc0_intctl);
3443 3462 /* Stop translation as we may have switched the execution mode */
3444 3463 ctx->bstate = BS_STOP;
3445 3464 rn = "IntCtl";
3446 3465 break;
3447 3466 case 2:
3448 3467 check_insn(env, ctx, ISA_MIPS32R2);
3449   - gen_op_mtc0_srsctl();
  3468 + tcg_gen_helper_0_0(do_mtc0_srsctl);
3450 3469 /* Stop translation as we may have switched the execution mode */
3451 3470 ctx->bstate = BS_STOP;
3452 3471 rn = "SRSCtl";
3453 3472 break;
3454 3473 case 3:
3455 3474 check_insn(env, ctx, ISA_MIPS32R2);
3456   - gen_op_mtc0_srsmap();
  3475 + gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_SRSMap));
3457 3476 /* Stop translation as we may have switched the execution mode */
3458 3477 ctx->bstate = BS_STOP;
3459 3478 rn = "SRSMap";
... ... @@ -3465,7 +3484,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3465 3484 case 13:
3466 3485 switch (sel) {
3467 3486 case 0:
3468   - gen_op_mtc0_cause();
  3487 + tcg_gen_helper_0_0(do_mtc0_cause);
3469 3488 rn = "Cause";
3470 3489 break;
3471 3490 default:
... ... @@ -3477,7 +3496,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3477 3496 case 14:
3478 3497 switch (sel) {
3479 3498 case 0:
3480   - gen_op_mtc0_epc();
  3499 + gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_EPC));
3481 3500 rn = "EPC";
3482 3501 break;
3483 3502 default:
... ... @@ -3492,7 +3511,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3492 3511 break;
3493 3512 case 1:
3494 3513 check_insn(env, ctx, ISA_MIPS32R2);
3495   - gen_op_mtc0_ebase();
  3514 + tcg_gen_helper_0_0(do_mtc0_ebase);
3496 3515 rn = "EBase";
3497 3516 break;
3498 3517 default:
... ... @@ -3502,7 +3521,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3502 3521 case 16:
3503 3522 switch (sel) {
3504 3523 case 0:
3505   - gen_op_mtc0_config0();
  3524 + tcg_gen_helper_0_0(do_mtc0_config0);
3506 3525 rn = "Config";
3507 3526 /* Stop translation as we may have switched the execution mode */
3508 3527 ctx->bstate = BS_STOP;
... ... @@ -3512,7 +3531,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3512 3531 rn = "Config1";
3513 3532 break;
3514 3533 case 2:
3515   - gen_op_mtc0_config2();
  3534 + tcg_gen_helper_0_0(do_mtc0_config2);
3516 3535 rn = "Config2";
3517 3536 /* Stop translation as we may have switched the execution mode */
3518 3537 ctx->bstate = BS_STOP;
... ... @@ -3549,7 +3568,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3549 3568 case 18:
3550 3569 switch (sel) {
3551 3570 case 0 ... 7:
3552   - gen_op_mtc0_watchlo(sel);
  3571 + tcg_gen_helper_0_1i(do_mtc0_watchlo, sel);
3553 3572 rn = "WatchLo";
3554 3573 break;
3555 3574 default:
... ... @@ -3559,7 +3578,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3559 3578 case 19:
3560 3579 switch (sel) {
3561 3580 case 0 ... 7:
3562   - gen_op_mtc0_watchhi(sel);
  3581 + tcg_gen_helper_0_1i(do_mtc0_watchhi, sel);
3563 3582 rn = "WatchHi";
3564 3583 break;
3565 3584 default:
... ... @@ -3571,7 +3590,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3571 3590 case 0:
3572 3591 #if defined(TARGET_MIPS64)
3573 3592 check_insn(env, ctx, ISA_MIPS3);
3574   - gen_op_mtc0_xcontext();
  3593 + tcg_gen_helper_0_0(do_mtc0_xcontext);
3575 3594 rn = "XContext";
3576 3595 break;
3577 3596 #endif
... ... @@ -3583,7 +3602,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3583 3602 /* Officially reserved, but sel 0 is used for R1x000 framemask */
3584 3603 switch (sel) {
3585 3604 case 0:
3586   - gen_op_mtc0_framemask();
  3605 + tcg_gen_helper_0_0(do_mtc0_framemask);
3587 3606 rn = "Framemask";
3588 3607 break;
3589 3608 default:
... ... @@ -3597,20 +3616,20 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3597 3616 case 23:
3598 3617 switch (sel) {
3599 3618 case 0:
3600   - gen_op_mtc0_debug(); /* EJTAG support */
  3619 + tcg_gen_helper_0_0(do_mtc0_debug); /* EJTAG support */
3601 3620 /* BS_STOP isn't good enough here, hflags may have changed. */
3602 3621 gen_save_pc(ctx->pc + 4);
3603 3622 ctx->bstate = BS_EXCP;
3604 3623 rn = "Debug";
3605 3624 break;
3606 3625 case 1:
3607   -// gen_op_mtc0_tracecontrol(); /* PDtrace support */
  3626 +// tcg_gen_helper_0_0(do_mtc0_tracecontrol); /* PDtrace support */
3608 3627 rn = "TraceControl";
3609 3628 /* Stop translation as we may have switched the execution mode */
3610 3629 ctx->bstate = BS_STOP;
3611 3630 // break;
3612 3631 case 2:
3613   -// gen_op_mtc0_tracecontrol2(); /* PDtrace support */
  3632 +// tcg_gen_helper_0_0(do_mtc0_tracecontrol2); /* PDtrace support */
3614 3633 rn = "TraceControl2";
3615 3634 /* Stop translation as we may have switched the execution mode */
3616 3635 ctx->bstate = BS_STOP;
... ... @@ -3618,13 +3637,13 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3618 3637 case 3:
3619 3638 /* Stop translation as we may have switched the execution mode */
3620 3639 ctx->bstate = BS_STOP;
3621   -// gen_op_mtc0_usertracedata(); /* PDtrace support */
  3640 +// tcg_gen_helper_0_0(do_mtc0_usertracedata); /* PDtrace support */
3622 3641 rn = "UserTraceData";
3623 3642 /* Stop translation as we may have switched the execution mode */
3624 3643 ctx->bstate = BS_STOP;
3625 3644 // break;
3626 3645 case 4:
3627   -// gen_op_mtc0_debug(); /* PDtrace support */
  3646 +// tcg_gen_helper_0_0(do_mtc0_debug); /* PDtrace support */
3628 3647 /* Stop translation as we may have switched the execution mode */
3629 3648 ctx->bstate = BS_STOP;
3630 3649 rn = "TraceBPC";
... ... @@ -3636,7 +3655,8 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3636 3655 case 24:
3637 3656 switch (sel) {
3638 3657 case 0:
3639   - gen_op_mtc0_depc(); /* EJTAG support */
  3658 + /* EJTAG support */
  3659 + gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_DEPC));
3640 3660 rn = "DEPC";
3641 3661 break;
3642 3662 default:
... ... @@ -3646,35 +3666,35 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3646 3666 case 25:
3647 3667 switch (sel) {
3648 3668 case 0:
3649   - gen_op_mtc0_performance0();
  3669 + tcg_gen_helper_0_0(do_mtc0_performance0);
3650 3670 rn = "Performance0";
3651 3671 break;
3652 3672 case 1:
3653   -// gen_op_mtc0_performance1();
  3673 +// tcg_gen_helper_0_0(do_mtc0_performance1);
3654 3674 rn = "Performance1";
3655 3675 // break;
3656 3676 case 2:
3657   -// gen_op_mtc0_performance2();
  3677 +// tcg_gen_helper_0_0(do_mtc0_performance2);
3658 3678 rn = "Performance2";
3659 3679 // break;
3660 3680 case 3:
3661   -// gen_op_mtc0_performance3();
  3681 +// tcg_gen_helper_0_0(do_mtc0_performance3);
3662 3682 rn = "Performance3";
3663 3683 // break;
3664 3684 case 4:
3665   -// gen_op_mtc0_performance4();
  3685 +// tcg_gen_helper_0_0(do_mtc0_performance4);
3666 3686 rn = "Performance4";
3667 3687 // break;
3668 3688 case 5:
3669   -// gen_op_mtc0_performance5();
  3689 +// tcg_gen_helper_0_0(do_mtc0_performance5);
3670 3690 rn = "Performance5";
3671 3691 // break;
3672 3692 case 6:
3673   -// gen_op_mtc0_performance6();
  3693 +// tcg_gen_helper_0_0(do_mtc0_performance6);
3674 3694 rn = "Performance6";
3675 3695 // break;
3676 3696 case 7:
3677   -// gen_op_mtc0_performance7();
  3697 +// tcg_gen_helper_0_0(do_mtc0_performance7);
3678 3698 rn = "Performance7";
3679 3699 // break;
3680 3700 default:
... ... @@ -3701,14 +3721,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3701 3721 case 2:
3702 3722 case 4:
3703 3723 case 6:
3704   - gen_op_mtc0_taglo();
  3724 + tcg_gen_helper_0_0(do_mtc0_taglo);
3705 3725 rn = "TagLo";
3706 3726 break;
3707 3727 case 1:
3708 3728 case 3:
3709 3729 case 5:
3710 3730 case 7:
3711   - gen_op_mtc0_datalo();
  3731 + tcg_gen_helper_0_0(do_mtc0_datalo);
3712 3732 rn = "DataLo";
3713 3733 break;
3714 3734 default:
... ... @@ -3721,14 +3741,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3721 3741 case 2:
3722 3742 case 4:
3723 3743 case 6:
3724   - gen_op_mtc0_taghi();
  3744 + tcg_gen_helper_0_0(do_mtc0_taghi);
3725 3745 rn = "TagHi";
3726 3746 break;
3727 3747 case 1:
3728 3748 case 3:
3729 3749 case 5:
3730 3750 case 7:
3731   - gen_op_mtc0_datahi();
  3751 + tcg_gen_helper_0_0(do_mtc0_datahi);
3732 3752 rn = "DataHi";
3733 3753 break;
3734 3754 default:
... ... @@ -3739,7 +3759,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3739 3759 case 30:
3740 3760 switch (sel) {
3741 3761 case 0:
3742   - gen_op_mtc0_errorepc();
  3762 + gen_mtc0_store64(cpu_T[0], offsetof(CPUState, CP0_ErrorEPC));
3743 3763 rn = "ErrorEPC";
3744 3764 break;
3745 3765 default:
... ... @@ -3749,7 +3769,8 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3749 3769 case 31:
3750 3770 switch (sel) {
3751 3771 case 0:
3752   - gen_op_mtc0_desave(); /* EJTAG support */
  3772 + /* EJTAG support */
  3773 + gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_DESAVE));
3753 3774 rn = "DESAVE";
3754 3775 break;
3755 3776 default:
... ... @@ -3796,17 +3817,17 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3796 3817 break;
3797 3818 case 1:
3798 3819 check_insn(env, ctx, ASE_MT);
3799   - gen_op_mfc0_mvpcontrol();
  3820 + tcg_gen_helper_0_0(do_mfc0_mvpcontrol);
3800 3821 rn = "MVPControl";
3801 3822 break;
3802 3823 case 2:
3803 3824 check_insn(env, ctx, ASE_MT);
3804   - gen_op_mfc0_mvpconf0();
  3825 + tcg_gen_helper_0_0(do_mfc0_mvpconf0);
3805 3826 rn = "MVPConf0";
3806 3827 break;
3807 3828 case 3:
3808 3829 check_insn(env, ctx, ASE_MT);
3809   - gen_op_mfc0_mvpconf1();
  3830 + tcg_gen_helper_0_0(do_mfc0_mvpconf1);
3810 3831 rn = "MVPConf1";
3811 3832 break;
3812 3833 default:
... ... @@ -3816,7 +3837,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3816 3837 case 1:
3817 3838 switch (sel) {
3818 3839 case 0:
3819   - gen_op_mfc0_random();
  3840 + tcg_gen_helper_0_0(do_mfc0_random);
3820 3841 rn = "Random";
3821 3842 break;
3822 3843 case 1:
... ... @@ -3866,37 +3887,37 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3866 3887 break;
3867 3888 case 1:
3868 3889 check_insn(env, ctx, ASE_MT);
3869   - gen_op_mfc0_tcstatus();
  3890 + tcg_gen_helper_0_0(do_mfc0_tcstatus);
3870 3891 rn = "TCStatus";
3871 3892 break;
3872 3893 case 2:
3873 3894 check_insn(env, ctx, ASE_MT);
3874   - gen_op_mfc0_tcbind();
  3895 + tcg_gen_helper_0_0(do_mfc0_tcbind);
3875 3896 rn = "TCBind";
3876 3897 break;
3877 3898 case 3:
3878 3899 check_insn(env, ctx, ASE_MT);
3879   - gen_op_dmfc0_tcrestart();
  3900 + tcg_gen_helper_0_0(do_dmfc0_tcrestart);
3880 3901 rn = "TCRestart";
3881 3902 break;
3882 3903 case 4:
3883 3904 check_insn(env, ctx, ASE_MT);
3884   - gen_op_dmfc0_tchalt();
  3905 + tcg_gen_helper_0_0(do_dmfc0_tchalt);
3885 3906 rn = "TCHalt";
3886 3907 break;
3887 3908 case 5:
3888 3909 check_insn(env, ctx, ASE_MT);
3889   - gen_op_dmfc0_tccontext();
  3910 + tcg_gen_helper_0_0(do_dmfc0_tccontext);
3890 3911 rn = "TCContext";
3891 3912 break;
3892 3913 case 6:
3893 3914 check_insn(env, ctx, ASE_MT);
3894   - gen_op_dmfc0_tcschedule();
  3915 + tcg_gen_helper_0_0(do_dmfc0_tcschedule);
3895 3916 rn = "TCSchedule";
3896 3917 break;
3897 3918 case 7:
3898 3919 check_insn(env, ctx, ASE_MT);
3899   - gen_op_dmfc0_tcschefback();
  3920 + tcg_gen_helper_0_0(do_dmfc0_tcschefback);
3900 3921 rn = "TCScheFBack";
3901 3922 break;
3902 3923 default:
... ... @@ -3920,7 +3941,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
3920 3941 rn = "Context";
3921 3942 break;
3922 3943 case 1:
3923   -// gen_op_dmfc0_contextconfig(); /* SmartMIPS ASE */
  3944 +// tcg_gen_helper_0_0(do_dmfc0_contextconfig); /* SmartMIPS ASE */
3924 3945 rn = "ContextConfig";
3925 3946 // break;
3926 3947 default:
... ... @@ -4001,7 +4022,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4001 4022 case 9:
4002 4023 switch (sel) {
4003 4024 case 0:
4004   - gen_op_mfc0_count();
  4025 + tcg_gen_helper_0_0(do_mfc0_count);
4005 4026 rn = "Count";
4006 4027 break;
4007 4028 /* 6,7 are implementation dependent */
... ... @@ -4124,7 +4145,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4124 4145 case 17:
4125 4146 switch (sel) {
4126 4147 case 0:
4127   - gen_op_dmfc0_lladdr();
  4148 + tcg_gen_helper_0_0(do_dmfc0_lladdr);
4128 4149 rn = "LLAddr";
4129 4150 break;
4130 4151 default:
... ... @@ -4134,7 +4155,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4134 4155 case 18:
4135 4156 switch (sel) {
4136 4157 case 0 ... 7:
4137   - gen_op_dmfc0_watchlo(sel);
  4158 + tcg_gen_helper_0_1i(do_dmfc0_watchlo, sel);
4138 4159 rn = "WatchLo";
4139 4160 break;
4140 4161 default:
... ... @@ -4144,7 +4165,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4144 4165 case 19:
4145 4166 switch (sel) {
4146 4167 case 0 ... 7:
4147   - gen_op_mfc0_watchhi(sel);
  4168 + tcg_gen_helper_0_1i(do_mfc0_watchhi, sel);
4148 4169 rn = "WatchHi";
4149 4170 break;
4150 4171 default:
... ... @@ -4180,23 +4201,23 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4180 4201 case 23:
4181 4202 switch (sel) {
4182 4203 case 0:
4183   - gen_op_mfc0_debug(); /* EJTAG support */
  4204 + tcg_gen_helper_0_0(do_mfc0_debug); /* EJTAG support */
4184 4205 rn = "Debug";
4185 4206 break;
4186 4207 case 1:
4187   -// gen_op_dmfc0_tracecontrol(); /* PDtrace support */
  4208 +// tcg_gen_helper_0_0(do_dmfc0_tracecontrol); /* PDtrace support */
4188 4209 rn = "TraceControl";
4189 4210 // break;
4190 4211 case 2:
4191   -// gen_op_dmfc0_tracecontrol2(); /* PDtrace support */
  4212 +// tcg_gen_helper_0_0(do_dmfc0_tracecontrol2); /* PDtrace support */
4192 4213 rn = "TraceControl2";
4193 4214 // break;
4194 4215 case 3:
4195   -// gen_op_dmfc0_usertracedata(); /* PDtrace support */
  4216 +// tcg_gen_helper_0_0(do_dmfc0_usertracedata); /* PDtrace support */
4196 4217 rn = "UserTraceData";
4197 4218 // break;
4198 4219 case 4:
4199   -// gen_op_dmfc0_debug(); /* PDtrace support */
  4220 +// tcg_gen_helper_0_0(do_dmfc0_debug); /* PDtrace support */
4200 4221 rn = "TraceBPC";
4201 4222 // break;
4202 4223 default:
... ... @@ -4221,31 +4242,31 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4221 4242 rn = "Performance0";
4222 4243 break;
4223 4244 case 1:
4224   -// gen_op_dmfc0_performance1();
  4245 +// tcg_gen_helper_0_0(do_dmfc0_performance1);
4225 4246 rn = "Performance1";
4226 4247 // break;
4227 4248 case 2:
4228   -// gen_op_dmfc0_performance2();
  4249 +// tcg_gen_helper_0_0(do_dmfc0_performance2);
4229 4250 rn = "Performance2";
4230 4251 // break;
4231 4252 case 3:
4232   -// gen_op_dmfc0_performance3();
  4253 +// tcg_gen_helper_0_0(do_dmfc0_performance3);
4233 4254 rn = "Performance3";
4234 4255 // break;
4235 4256 case 4:
4236   -// gen_op_dmfc0_performance4();
  4257 +// tcg_gen_helper_0_0(do_dmfc0_performance4);
4237 4258 rn = "Performance4";
4238 4259 // break;
4239 4260 case 5:
4240   -// gen_op_dmfc0_performance5();
  4261 +// tcg_gen_helper_0_0(do_dmfc0_performance5);
4241 4262 rn = "Performance5";
4242 4263 // break;
4243 4264 case 6:
4244   -// gen_op_dmfc0_performance6();
  4265 +// tcg_gen_helper_0_0(do_dmfc0_performance6);
4245 4266 rn = "Performance6";
4246 4267 // break;
4247 4268 case 7:
4248   -// gen_op_dmfc0_performance7();
  4269 +// tcg_gen_helper_0_0(do_dmfc0_performance7);
4249 4270 rn = "Performance7";
4250 4271 // break;
4251 4272 default:
... ... @@ -4358,12 +4379,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4358 4379 case 0:
4359 4380 switch (sel) {
4360 4381 case 0:
4361   - gen_op_mtc0_index();
  4382 + tcg_gen_helper_0_0(do_mtc0_index);
4362 4383 rn = "Index";
4363 4384 break;
4364 4385 case 1:
4365 4386 check_insn(env, ctx, ASE_MT);
4366   - gen_op_mtc0_mvpcontrol();
  4387 + tcg_gen_helper_0_0(do_mtc0_mvpcontrol);
4367 4388 rn = "MVPControl";
4368 4389 break;
4369 4390 case 2:
... ... @@ -4388,37 +4409,37 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4388 4409 break;
4389 4410 case 1:
4390 4411 check_insn(env, ctx, ASE_MT);
4391   - gen_op_mtc0_vpecontrol();
  4412 + tcg_gen_helper_0_0(do_mtc0_vpecontrol);
4392 4413 rn = "VPEControl";
4393 4414 break;
4394 4415 case 2:
4395 4416 check_insn(env, ctx, ASE_MT);
4396   - gen_op_mtc0_vpeconf0();
  4417 + tcg_gen_helper_0_0(do_mtc0_vpeconf0);
4397 4418 rn = "VPEConf0";
4398 4419 break;
4399 4420 case 3:
4400 4421 check_insn(env, ctx, ASE_MT);
4401   - gen_op_mtc0_vpeconf1();
  4422 + tcg_gen_helper_0_0(do_mtc0_vpeconf1);
4402 4423 rn = "VPEConf1";
4403 4424 break;
4404 4425 case 4:
4405 4426 check_insn(env, ctx, ASE_MT);
4406   - gen_op_mtc0_yqmask();
  4427 + tcg_gen_helper_0_0(do_mtc0_yqmask);
4407 4428 rn = "YQMask";
4408 4429 break;
4409 4430 case 5:
4410 4431 check_insn(env, ctx, ASE_MT);
4411   - gen_op_mtc0_vpeschedule();
  4432 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPESchedule));
4412 4433 rn = "VPESchedule";
4413 4434 break;
4414 4435 case 6:
4415 4436 check_insn(env, ctx, ASE_MT);
4416   - gen_op_mtc0_vpeschefback();
  4437 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_VPEScheFBack));
4417 4438 rn = "VPEScheFBack";
4418 4439 break;
4419 4440 case 7:
4420 4441 check_insn(env, ctx, ASE_MT);
4421   - gen_op_mtc0_vpeopt();
  4442 + tcg_gen_helper_0_0(do_mtc0_vpeopt);
4422 4443 rn = "VPEOpt";
4423 4444 break;
4424 4445 default:
... ... @@ -4428,42 +4449,42 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4428 4449 case 2:
4429 4450 switch (sel) {
4430 4451 case 0:
4431   - gen_op_mtc0_entrylo0();
  4452 + tcg_gen_helper_0_0(do_mtc0_entrylo0);
4432 4453 rn = "EntryLo0";
4433 4454 break;
4434 4455 case 1:
4435 4456 check_insn(env, ctx, ASE_MT);
4436   - gen_op_mtc0_tcstatus();
  4457 + tcg_gen_helper_0_0(do_mtc0_tcstatus);
4437 4458 rn = "TCStatus";
4438 4459 break;
4439 4460 case 2:
4440 4461 check_insn(env, ctx, ASE_MT);
4441   - gen_op_mtc0_tcbind();
  4462 + tcg_gen_helper_0_0(do_mtc0_tcbind);
4442 4463 rn = "TCBind";
4443 4464 break;
4444 4465 case 3:
4445 4466 check_insn(env, ctx, ASE_MT);
4446   - gen_op_mtc0_tcrestart();
  4467 + tcg_gen_helper_0_0(do_mtc0_tcrestart);
4447 4468 rn = "TCRestart";
4448 4469 break;
4449 4470 case 4:
4450 4471 check_insn(env, ctx, ASE_MT);
4451   - gen_op_mtc0_tchalt();
  4472 + tcg_gen_helper_0_0(do_mtc0_tchalt);
4452 4473 rn = "TCHalt";
4453 4474 break;
4454 4475 case 5:
4455 4476 check_insn(env, ctx, ASE_MT);
4456   - gen_op_mtc0_tccontext();
  4477 + tcg_gen_helper_0_0(do_mtc0_tccontext);
4457 4478 rn = "TCContext";
4458 4479 break;
4459 4480 case 6:
4460 4481 check_insn(env, ctx, ASE_MT);
4461   - gen_op_mtc0_tcschedule();
  4482 + tcg_gen_helper_0_0(do_mtc0_tcschedule);
4462 4483 rn = "TCSchedule";
4463 4484 break;
4464 4485 case 7:
4465 4486 check_insn(env, ctx, ASE_MT);
4466   - gen_op_mtc0_tcschefback();
  4487 + tcg_gen_helper_0_0(do_mtc0_tcschefback);
4467 4488 rn = "TCScheFBack";
4468 4489 break;
4469 4490 default:
... ... @@ -4473,7 +4494,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4473 4494 case 3:
4474 4495 switch (sel) {
4475 4496 case 0:
4476   - gen_op_mtc0_entrylo1();
  4497 + tcg_gen_helper_0_0(do_mtc0_entrylo1);
4477 4498 rn = "EntryLo1";
4478 4499 break;
4479 4500 default:
... ... @@ -4483,11 +4504,11 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4483 4504 case 4:
4484 4505 switch (sel) {
4485 4506 case 0:
4486   - gen_op_mtc0_context();
  4507 + tcg_gen_helper_0_0(do_mtc0_context);
4487 4508 rn = "Context";
4488 4509 break;
4489 4510 case 1:
4490   -// gen_op_mtc0_contextconfig(); /* SmartMIPS ASE */
  4511 +// tcg_gen_helper_0_0(do_mtc0_contextconfig); /* SmartMIPS ASE */
4491 4512 rn = "ContextConfig";
4492 4513 // break;
4493 4514 default:
... ... @@ -4497,12 +4518,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4497 4518 case 5:
4498 4519 switch (sel) {
4499 4520 case 0:
4500   - gen_op_mtc0_pagemask();
  4521 + tcg_gen_helper_0_0(do_mtc0_pagemask);
4501 4522 rn = "PageMask";
4502 4523 break;
4503 4524 case 1:
4504 4525 check_insn(env, ctx, ISA_MIPS32R2);
4505   - gen_op_mtc0_pagegrain();
  4526 + tcg_gen_helper_0_0(do_mtc0_pagegrain);
4506 4527 rn = "PageGrain";
4507 4528 break;
4508 4529 default:
... ... @@ -4512,32 +4533,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4512 4533 case 6:
4513 4534 switch (sel) {
4514 4535 case 0:
4515   - gen_op_mtc0_wired();
  4536 + tcg_gen_helper_0_0(do_mtc0_wired);
4516 4537 rn = "Wired";
4517 4538 break;
4518 4539 case 1:
4519 4540 check_insn(env, ctx, ISA_MIPS32R2);
4520   - gen_op_mtc0_srsconf0();
  4541 + tcg_gen_helper_0_0(do_mtc0_srsconf0);
4521 4542 rn = "SRSConf0";
4522 4543 break;
4523 4544 case 2:
4524 4545 check_insn(env, ctx, ISA_MIPS32R2);
4525   - gen_op_mtc0_srsconf1();
  4546 + tcg_gen_helper_0_0(do_mtc0_srsconf1);
4526 4547 rn = "SRSConf1";
4527 4548 break;
4528 4549 case 3:
4529 4550 check_insn(env, ctx, ISA_MIPS32R2);
4530   - gen_op_mtc0_srsconf2();
  4551 + tcg_gen_helper_0_0(do_mtc0_srsconf2);
4531 4552 rn = "SRSConf2";
4532 4553 break;
4533 4554 case 4:
4534 4555 check_insn(env, ctx, ISA_MIPS32R2);
4535   - gen_op_mtc0_srsconf3();
  4556 + tcg_gen_helper_0_0(do_mtc0_srsconf3);
4536 4557 rn = "SRSConf3";
4537 4558 break;
4538 4559 case 5:
4539 4560 check_insn(env, ctx, ISA_MIPS32R2);
4540   - gen_op_mtc0_srsconf4();
  4561 + tcg_gen_helper_0_0(do_mtc0_srsconf4);
4541 4562 rn = "SRSConf4";
4542 4563 break;
4543 4564 default:
... ... @@ -4548,7 +4569,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4548 4569 switch (sel) {
4549 4570 case 0:
4550 4571 check_insn(env, ctx, ISA_MIPS32R2);
4551   - gen_op_mtc0_hwrena();
  4572 + tcg_gen_helper_0_0(do_mtc0_hwrena);
4552 4573 rn = "HWREna";
4553 4574 break;
4554 4575 default:
... ... @@ -4562,7 +4583,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4562 4583 case 9:
4563 4584 switch (sel) {
4564 4585 case 0:
4565   - gen_op_mtc0_count();
  4586 + tcg_gen_helper_0_0(do_mtc0_count);
4566 4587 rn = "Count";
4567 4588 break;
4568 4589 /* 6,7 are implementation dependent */
... ... @@ -4575,7 +4596,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4575 4596 case 10:
4576 4597 switch (sel) {
4577 4598 case 0:
4578   - gen_op_mtc0_entryhi();
  4599 + tcg_gen_helper_0_0(do_mtc0_entryhi);
4579 4600 rn = "EntryHi";
4580 4601 break;
4581 4602 default:
... ... @@ -4585,7 +4606,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4585 4606 case 11:
4586 4607 switch (sel) {
4587 4608 case 0:
4588   - gen_op_mtc0_compare();
  4609 + tcg_gen_helper_0_0(do_mtc0_compare);
4589 4610 rn = "Compare";
4590 4611 break;
4591 4612 /* 6,7 are implementation dependent */
... ... @@ -4598,7 +4619,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4598 4619 case 12:
4599 4620 switch (sel) {
4600 4621 case 0:
4601   - gen_op_mtc0_status();
  4622 + tcg_gen_helper_0_0(do_mtc0_status);
4602 4623 /* BS_STOP isn't good enough here, hflags may have changed. */
4603 4624 gen_save_pc(ctx->pc + 4);
4604 4625 ctx->bstate = BS_EXCP;
... ... @@ -4606,21 +4627,21 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4606 4627 break;
4607 4628 case 1:
4608 4629 check_insn(env, ctx, ISA_MIPS32R2);
4609   - gen_op_mtc0_intctl();
  4630 + tcg_gen_helper_0_0(do_mtc0_intctl);
4610 4631 /* Stop translation as we may have switched the execution mode */
4611 4632 ctx->bstate = BS_STOP;
4612 4633 rn = "IntCtl";
4613 4634 break;
4614 4635 case 2:
4615 4636 check_insn(env, ctx, ISA_MIPS32R2);
4616   - gen_op_mtc0_srsctl();
  4637 + tcg_gen_helper_0_0(do_mtc0_srsctl);
4617 4638 /* Stop translation as we may have switched the execution mode */
4618 4639 ctx->bstate = BS_STOP;
4619 4640 rn = "SRSCtl";
4620 4641 break;
4621 4642 case 3:
4622 4643 check_insn(env, ctx, ISA_MIPS32R2);
4623   - gen_op_mtc0_srsmap();
  4644 + gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_SRSMap));
4624 4645 /* Stop translation as we may have switched the execution mode */
4625 4646 ctx->bstate = BS_STOP;
4626 4647 rn = "SRSMap";
... ... @@ -4632,7 +4653,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4632 4653 case 13:
4633 4654 switch (sel) {
4634 4655 case 0:
4635   - gen_op_mtc0_cause();
  4656 + tcg_gen_helper_0_0(do_mtc0_cause);
4636 4657 rn = "Cause";
4637 4658 break;
4638 4659 default:
... ... @@ -4644,7 +4665,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4644 4665 case 14:
4645 4666 switch (sel) {
4646 4667 case 0:
4647   - gen_op_mtc0_epc();
  4668 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_EPC));
4648 4669 rn = "EPC";
4649 4670 break;
4650 4671 default:
... ... @@ -4659,7 +4680,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4659 4680 break;
4660 4681 case 1:
4661 4682 check_insn(env, ctx, ISA_MIPS32R2);
4662   - gen_op_mtc0_ebase();
  4683 + tcg_gen_helper_0_0(do_mtc0_ebase);
4663 4684 rn = "EBase";
4664 4685 break;
4665 4686 default:
... ... @@ -4669,7 +4690,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4669 4690 case 16:
4670 4691 switch (sel) {
4671 4692 case 0:
4672   - gen_op_mtc0_config0();
  4693 + tcg_gen_helper_0_0(do_mtc0_config0);
4673 4694 rn = "Config";
4674 4695 /* Stop translation as we may have switched the execution mode */
4675 4696 ctx->bstate = BS_STOP;
... ... @@ -4679,7 +4700,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4679 4700 rn = "Config1";
4680 4701 break;
4681 4702 case 2:
4682   - gen_op_mtc0_config2();
  4703 + tcg_gen_helper_0_0(do_mtc0_config2);
4683 4704 rn = "Config2";
4684 4705 /* Stop translation as we may have switched the execution mode */
4685 4706 ctx->bstate = BS_STOP;
... ... @@ -4707,7 +4728,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4707 4728 case 18:
4708 4729 switch (sel) {
4709 4730 case 0 ... 7:
4710   - gen_op_mtc0_watchlo(sel);
  4731 + tcg_gen_helper_0_1i(do_mtc0_watchlo, sel);
4711 4732 rn = "WatchLo";
4712 4733 break;
4713 4734 default:
... ... @@ -4717,7 +4738,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4717 4738 case 19:
4718 4739 switch (sel) {
4719 4740 case 0 ... 7:
4720   - gen_op_mtc0_watchhi(sel);
  4741 + tcg_gen_helper_0_1i(do_mtc0_watchhi, sel);
4721 4742 rn = "WatchHi";
4722 4743 break;
4723 4744 default:
... ... @@ -4728,7 +4749,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4728 4749 switch (sel) {
4729 4750 case 0:
4730 4751 check_insn(env, ctx, ISA_MIPS3);
4731   - gen_op_mtc0_xcontext();
  4752 + tcg_gen_helper_0_0(do_mtc0_xcontext);
4732 4753 rn = "XContext";
4733 4754 break;
4734 4755 default:
... ... @@ -4739,7 +4760,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4739 4760 /* Officially reserved, but sel 0 is used for R1x000 framemask */
4740 4761 switch (sel) {
4741 4762 case 0:
4742   - gen_op_mtc0_framemask();
  4763 + tcg_gen_helper_0_0(do_mtc0_framemask);
4743 4764 rn = "Framemask";
4744 4765 break;
4745 4766 default:
... ... @@ -4753,32 +4774,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4753 4774 case 23:
4754 4775 switch (sel) {
4755 4776 case 0:
4756   - gen_op_mtc0_debug(); /* EJTAG support */
  4777 + tcg_gen_helper_0_0(do_mtc0_debug); /* EJTAG support */
4757 4778 /* BS_STOP isn't good enough here, hflags may have changed. */
4758 4779 gen_save_pc(ctx->pc + 4);
4759 4780 ctx->bstate = BS_EXCP;
4760 4781 rn = "Debug";
4761 4782 break;
4762 4783 case 1:
4763   -// gen_op_mtc0_tracecontrol(); /* PDtrace support */
  4784 +// tcg_gen_helper_0_0(do_mtc0_tracecontrol); /* PDtrace support */
4764 4785 /* Stop translation as we may have switched the execution mode */
4765 4786 ctx->bstate = BS_STOP;
4766 4787 rn = "TraceControl";
4767 4788 // break;
4768 4789 case 2:
4769   -// gen_op_mtc0_tracecontrol2(); /* PDtrace support */
  4790 +// tcg_gen_helper_0_0(do_mtc0_tracecontrol2); /* PDtrace support */
4770 4791 /* Stop translation as we may have switched the execution mode */
4771 4792 ctx->bstate = BS_STOP;
4772 4793 rn = "TraceControl2";
4773 4794 // break;
4774 4795 case 3:
4775   -// gen_op_mtc0_usertracedata(); /* PDtrace support */
  4796 +// tcg_gen_helper_0_0(do_mtc0_usertracedata); /* PDtrace support */
4776 4797 /* Stop translation as we may have switched the execution mode */
4777 4798 ctx->bstate = BS_STOP;
4778 4799 rn = "UserTraceData";
4779 4800 // break;
4780 4801 case 4:
4781   -// gen_op_mtc0_debug(); /* PDtrace support */
  4802 +// tcg_gen_helper_0_0(do_mtc0_debug); /* PDtrace support */
4782 4803 /* Stop translation as we may have switched the execution mode */
4783 4804 ctx->bstate = BS_STOP;
4784 4805 rn = "TraceBPC";
... ... @@ -4790,7 +4811,8 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4790 4811 case 24:
4791 4812 switch (sel) {
4792 4813 case 0:
4793   - gen_op_mtc0_depc(); /* EJTAG support */
  4814 + /* EJTAG support */
  4815 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_DEPC));
4794 4816 rn = "DEPC";
4795 4817 break;
4796 4818 default:
... ... @@ -4800,35 +4822,35 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4800 4822 case 25:
4801 4823 switch (sel) {
4802 4824 case 0:
4803   - gen_op_mtc0_performance0();
  4825 + tcg_gen_helper_0_0(do_mtc0_performance0);
4804 4826 rn = "Performance0";
4805 4827 break;
4806 4828 case 1:
4807   -// gen_op_mtc0_performance1();
  4829 +// tcg_gen_helper_0_0(do_mtc0_performance1);
4808 4830 rn = "Performance1";
4809 4831 // break;
4810 4832 case 2:
4811   -// gen_op_mtc0_performance2();
  4833 +// tcg_gen_helper_0_0(do_mtc0_performance2);
4812 4834 rn = "Performance2";
4813 4835 // break;
4814 4836 case 3:
4815   -// gen_op_mtc0_performance3();
  4837 +// tcg_gen_helper_0_0(do_mtc0_performance3);
4816 4838 rn = "Performance3";
4817 4839 // break;
4818 4840 case 4:
4819   -// gen_op_mtc0_performance4();
  4841 +// tcg_gen_helper_0_0(do_mtc0_performance4);
4820 4842 rn = "Performance4";
4821 4843 // break;
4822 4844 case 5:
4823   -// gen_op_mtc0_performance5();
  4845 +// tcg_gen_helper_0_0(do_mtc0_performance5);
4824 4846 rn = "Performance5";
4825 4847 // break;
4826 4848 case 6:
4827   -// gen_op_mtc0_performance6();
  4849 +// tcg_gen_helper_0_0(do_mtc0_performance6);
4828 4850 rn = "Performance6";
4829 4851 // break;
4830 4852 case 7:
4831   -// gen_op_mtc0_performance7();
  4853 +// tcg_gen_helper_0_0(do_mtc0_performance7);
4832 4854 rn = "Performance7";
4833 4855 // break;
4834 4856 default:
... ... @@ -4855,14 +4877,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4855 4877 case 2:
4856 4878 case 4:
4857 4879 case 6:
4858   - gen_op_mtc0_taglo();
  4880 + tcg_gen_helper_0_0(do_mtc0_taglo);
4859 4881 rn = "TagLo";
4860 4882 break;
4861 4883 case 1:
4862 4884 case 3:
4863 4885 case 5:
4864 4886 case 7:
4865   - gen_op_mtc0_datalo();
  4887 + tcg_gen_helper_0_0(do_mtc0_datalo);
4866 4888 rn = "DataLo";
4867 4889 break;
4868 4890 default:
... ... @@ -4875,14 +4897,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4875 4897 case 2:
4876 4898 case 4:
4877 4899 case 6:
4878   - gen_op_mtc0_taghi();
  4900 + tcg_gen_helper_0_0(do_mtc0_taghi);
4879 4901 rn = "TagHi";
4880 4902 break;
4881 4903 case 1:
4882 4904 case 3:
4883 4905 case 5:
4884 4906 case 7:
4885   - gen_op_mtc0_datahi();
  4907 + tcg_gen_helper_0_0(do_mtc0_datahi);
4886 4908 rn = "DataHi";
4887 4909 break;
4888 4910 default:
... ... @@ -4893,7 +4915,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4893 4915 case 30:
4894 4916 switch (sel) {
4895 4917 case 0:
4896   - gen_op_mtc0_errorepc();
  4918 + tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_ErrorEPC));
4897 4919 rn = "ErrorEPC";
4898 4920 break;
4899 4921 default:
... ... @@ -4903,7 +4925,8 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
4903 4925 case 31:
4904 4926 switch (sel) {
4905 4927 case 0:
4906   - gen_op_mtc0_desave(); /* EJTAG support */
  4928 + /* EJTAG support */
  4929 + gen_mtc0_store32(cpu_T[0], offsetof(CPUState, CP0_DESAVE));
4907 4930 rn = "DESAVE";
4908 4931 break;
4909 4932 default:
... ... @@ -4951,25 +4974,25 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
4951 4974 case 2:
4952 4975 switch (sel) {
4953 4976 case 1:
4954   - gen_op_mftc0_tcstatus();
  4977 + tcg_gen_helper_0_0(do_mftc0_tcstatus);
4955 4978 break;
4956 4979 case 2:
4957   - gen_op_mftc0_tcbind();
  4980 + tcg_gen_helper_0_0(do_mftc0_tcbind);
4958 4981 break;
4959 4982 case 3:
4960   - gen_op_mftc0_tcrestart();
  4983 + tcg_gen_helper_0_0(do_mftc0_tcrestart);
4961 4984 break;
4962 4985 case 4:
4963   - gen_op_mftc0_tchalt();
  4986 + tcg_gen_helper_0_0(do_mftc0_tchalt);
4964 4987 break;
4965 4988 case 5:
4966   - gen_op_mftc0_tccontext();
  4989 + tcg_gen_helper_0_0(do_mftc0_tccontext);
4967 4990 break;
4968 4991 case 6:
4969   - gen_op_mftc0_tcschedule();
  4992 + tcg_gen_helper_0_0(do_mftc0_tcschedule);
4970 4993 break;
4971 4994 case 7:
4972   - gen_op_mftc0_tcschefback();
  4995 + tcg_gen_helper_0_0(do_mftc0_tcschefback);
4973 4996 break;
4974 4997 default:
4975 4998 gen_mfc0(env, ctx, rt, sel);
... ... @@ -4979,7 +5002,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
4979 5002 case 10:
4980 5003 switch (sel) {
4981 5004 case 0:
4982   - gen_op_mftc0_entryhi();
  5005 + tcg_gen_helper_0_0(do_mftc0_entryhi);
4983 5006 break;
4984 5007 default:
4985 5008 gen_mfc0(env, ctx, rt, sel);
... ... @@ -4988,7 +5011,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
4988 5011 case 12:
4989 5012 switch (sel) {
4990 5013 case 0:
4991   - gen_op_mftc0_status();
  5014 + tcg_gen_helper_0_0(do_mftc0_status);
4992 5015 break;
4993 5016 default:
4994 5017 gen_mfc0(env, ctx, rt, sel);
... ... @@ -4997,7 +5020,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
4997 5020 case 23:
4998 5021 switch (sel) {
4999 5022 case 0:
5000   - gen_op_mftc0_debug();
  5023 + tcg_gen_helper_0_0(do_mftc0_debug);
5001 5024 break;
5002 5025 default:
5003 5026 gen_mfc0(env, ctx, rt, sel);
... ... @@ -5010,49 +5033,49 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
5010 5033 } else switch (sel) {
5011 5034 /* GPR registers. */
5012 5035 case 0:
5013   - gen_op_mftgpr(rt);
  5036 + tcg_gen_helper_0_1i(do_mftgpr, rt);
5014 5037 break;
5015 5038 /* Auxiliary CPU registers */
5016 5039 case 1:
5017 5040 switch (rt) {
5018 5041 case 0:
5019   - gen_op_mftlo(0);
  5042 + tcg_gen_helper_0_1i(do_mftlo, 0);
5020 5043 break;
5021 5044 case 1:
5022   - gen_op_mfthi(0);
  5045 + tcg_gen_helper_0_1i(do_mfthi, 0);
5023 5046 break;
5024 5047 case 2:
5025   - gen_op_mftacx(0);
  5048 + tcg_gen_helper_0_1i(do_mftacx, 0);
5026 5049 break;
5027 5050 case 4:
5028   - gen_op_mftlo(1);
  5051 + tcg_gen_helper_0_1i(do_mftlo, 1);
5029 5052 break;
5030 5053 case 5:
5031   - gen_op_mfthi(1);
  5054 + tcg_gen_helper_0_1i(do_mfthi, 1);
5032 5055 break;
5033 5056 case 6:
5034   - gen_op_mftacx(1);
  5057 + tcg_gen_helper_0_1i(do_mftacx, 1);
5035 5058 break;
5036 5059 case 8:
5037   - gen_op_mftlo(2);
  5060 + tcg_gen_helper_0_1i(do_mftlo, 2);
5038 5061 break;
5039 5062 case 9:
5040   - gen_op_mfthi(2);
  5063 + tcg_gen_helper_0_1i(do_mfthi, 2);
5041 5064 break;
5042 5065 case 10:
5043   - gen_op_mftacx(2);
  5066 + tcg_gen_helper_0_1i(do_mftacx, 2);
5044 5067 break;
5045 5068 case 12:
5046   - gen_op_mftlo(3);
  5069 + tcg_gen_helper_0_1i(do_mftlo, 3);
5047 5070 break;
5048 5071 case 13:
5049   - gen_op_mfthi(3);
  5072 + tcg_gen_helper_0_1i(do_mfthi, 3);
5050 5073 break;
5051 5074 case 14:
5052   - gen_op_mftacx(3);
  5075 + tcg_gen_helper_0_1i(do_mftacx, 3);
5053 5076 break;
5054 5077 case 16:
5055   - gen_op_mftdsp();
  5078 + tcg_gen_helper_0_0(do_mftdsp);
5056 5079 break;
5057 5080 default:
5058 5081 goto die;
... ... @@ -5071,7 +5094,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
5071 5094 break;
5072 5095 case 3:
5073 5096 /* XXX: For now we support only a single FPU context. */
5074   - gen_op_cfc1(rt);
  5097 + tcg_gen_helper_0_1i(do_cfc1, rt);
5075 5098 break;
5076 5099 /* COP2: Not implemented. */
5077 5100 case 4:
... ... @@ -5115,25 +5138,25 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
5115 5138 case 2:
5116 5139 switch (sel) {
5117 5140 case 1:
5118   - gen_op_mttc0_tcstatus();
  5141 + tcg_gen_helper_0_0(do_mttc0_tcstatus);
5119 5142 break;
5120 5143 case 2:
5121   - gen_op_mttc0_tcbind();
  5144 + tcg_gen_helper_0_0(do_mttc0_tcbind);
5122 5145 break;
5123 5146 case 3:
5124   - gen_op_mttc0_tcrestart();
  5147 + tcg_gen_helper_0_0(do_mttc0_tcrestart);
5125 5148 break;
5126 5149 case 4:
5127   - gen_op_mttc0_tchalt();
  5150 + tcg_gen_helper_0_0(do_mttc0_tchalt);
5128 5151 break;
5129 5152 case 5:
5130   - gen_op_mttc0_tccontext();
  5153 + tcg_gen_helper_0_0(do_mttc0_tccontext);
5131 5154 break;
5132 5155 case 6:
5133   - gen_op_mttc0_tcschedule();
  5156 + tcg_gen_helper_0_0(do_mttc0_tcschedule);
5134 5157 break;
5135 5158 case 7:
5136   - gen_op_mttc0_tcschefback();
  5159 + tcg_gen_helper_0_0(do_mttc0_tcschefback);
5137 5160 break;
5138 5161 default:
5139 5162 gen_mtc0(env, ctx, rd, sel);
... ... @@ -5143,7 +5166,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
5143 5166 case 10:
5144 5167 switch (sel) {
5145 5168 case 0:
5146   - gen_op_mttc0_entryhi();
  5169 + tcg_gen_helper_0_0(do_mttc0_entryhi);
5147 5170 break;
5148 5171 default:
5149 5172 gen_mtc0(env, ctx, rd, sel);
... ... @@ -5152,7 +5175,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
5152 5175 case 12:
5153 5176 switch (sel) {
5154 5177 case 0:
5155   - gen_op_mttc0_status();
  5178 + tcg_gen_helper_0_0(do_mttc0_status);
5156 5179 break;
5157 5180 default:
5158 5181 gen_mtc0(env, ctx, rd, sel);
... ... @@ -5161,7 +5184,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
5161 5184 case 23:
5162 5185 switch (sel) {
5163 5186 case 0:
5164   - gen_op_mttc0_debug();
  5187 + tcg_gen_helper_0_0(do_mttc0_debug);
5165 5188 break;
5166 5189 default:
5167 5190 gen_mtc0(env, ctx, rd, sel);
... ... @@ -5174,49 +5197,49 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
5174 5197 } else switch (sel) {
5175 5198 /* GPR registers. */
5176 5199 case 0:
5177   - gen_op_mttgpr(rd);
  5200 + tcg_gen_helper_0_1i(do_mttgpr, rd);
5178 5201 break;
5179 5202 /* Auxiliary CPU registers */
5180 5203 case 1:
5181 5204 switch (rd) {
5182 5205 case 0:
5183   - gen_op_mttlo(0);
  5206 + tcg_gen_helper_0_1i(do_mttlo, 0);
5184 5207 break;
5185 5208 case 1:
5186   - gen_op_mtthi(0);
  5209 + tcg_gen_helper_0_1i(do_mtthi, 0);
5187 5210 break;
5188 5211 case 2:
5189   - gen_op_mttacx(0);
  5212 + tcg_gen_helper_0_1i(do_mttacx, 0);
5190 5213 break;
5191 5214 case 4:
5192   - gen_op_mttlo(1);
  5215 + tcg_gen_helper_0_1i(do_mttlo, 1);
5193 5216 break;
5194 5217 case 5:
5195   - gen_op_mtthi(1);
  5218 + tcg_gen_helper_0_1i(do_mtthi, 1);
5196 5219 break;
5197 5220 case 6:
5198   - gen_op_mttacx(1);
  5221 + tcg_gen_helper_0_1i(do_mttacx, 1);
5199 5222 break;
5200 5223 case 8:
5201   - gen_op_mttlo(2);
  5224 + tcg_gen_helper_0_1i(do_mttlo, 2);
5202 5225 break;
5203 5226 case 9:
5204   - gen_op_mtthi(2);
  5227 + tcg_gen_helper_0_1i(do_mtthi, 2);
5205 5228 break;
5206 5229 case 10:
5207   - gen_op_mttacx(2);
  5230 + tcg_gen_helper_0_1i(do_mttacx, 2);
5208 5231 break;
5209 5232 case 12:
5210   - gen_op_mttlo(3);
  5233 + tcg_gen_helper_0_1i(do_mttlo, 3);
5211 5234 break;
5212 5235 case 13:
5213   - gen_op_mtthi(3);
  5236 + tcg_gen_helper_0_1i(do_mtthi, 3);
5214 5237 break;
5215 5238 case 14:
5216   - gen_op_mttacx(3);
  5239 + tcg_gen_helper_0_1i(do_mttacx, 3);
5217 5240 break;
5218 5241 case 16:
5219   - gen_op_mttdsp();
  5242 + tcg_gen_helper_0_0(do_mttdsp);
5220 5243 break;
5221 5244 default:
5222 5245 goto die;
... ... @@ -5235,7 +5258,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
5235 5258 break;
5236 5259 case 3:
5237 5260 /* XXX: For now we support only a single FPU context. */
5238   - gen_op_ctc1(rd);
  5261 + tcg_gen_helper_0_1i(do_ctc1, rd);
5239 5262 break;
5240 5263 /* COP2: Not implemented. */
5241 5264 case 4:
... ... @@ -5380,6 +5403,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
5380 5403 }
5381 5404 MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd);
5382 5405 }
  5406 +#endif /* !CONFIG_USER_ONLY */
5383 5407  
5384 5408 /* CP1 Branches (before delay slot) */
5385 5409 static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op,
... ... @@ -5464,13 +5488,13 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
5464 5488 opn = "mtc1";
5465 5489 break;
5466 5490 case OPC_CFC1:
5467   - gen_op_cfc1(fs);
  5491 + tcg_gen_helper_0_1i(do_cfc1, fs);
5468 5492 gen_store_gpr(cpu_T[0], rt);
5469 5493 opn = "cfc1";
5470 5494 break;
5471 5495 case OPC_CTC1:
5472 5496 gen_load_gpr(cpu_T[0], rt);
5473   - gen_op_ctc1(fs);
  5497 + tcg_gen_helper_0_1i(do_ctc1, fs);
5474 5498 opn = "ctc1";
5475 5499 break;
5476 5500 case OPC_DMFC1:
... ... @@ -6846,12 +6870,12 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6846 6870 check_insn(env, ctx, ASE_MT);
6847 6871 gen_load_gpr(cpu_T[0], rt);
6848 6872 gen_load_gpr(cpu_T[1], rs);
6849   - gen_op_fork();
  6873 + tcg_gen_helper_0_0(do_fork);
6850 6874 break;
6851 6875 case OPC_YIELD:
6852 6876 check_insn(env, ctx, ASE_MT);
6853 6877 gen_load_gpr(cpu_T[0], rs);
6854   - gen_op_yield();
  6878 + tcg_gen_helper_0_0(do_yield);
6855 6879 gen_store_gpr(cpu_T[0], rd);
6856 6880 break;
6857 6881 #if defined(TARGET_MIPS64)
... ... @@ -6921,29 +6945,33 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
6921 6945 case OPC_DMFC0:
6922 6946 case OPC_DMTC0:
6923 6947 #endif
  6948 +#ifndef CONFIG_USER_ONLY
6924 6949 gen_cp0(env, ctx, op1, rt, rd);
  6950 +#endif
6925 6951 break;
6926 6952 case OPC_C0_FIRST ... OPC_C0_LAST:
  6953 +#ifndef CONFIG_USER_ONLY
6927 6954 gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
  6955 +#endif
6928 6956 break;
6929 6957 case OPC_MFMC0:
6930 6958 op2 = MASK_MFMC0(ctx->opcode);
6931 6959 switch (op2) {
6932 6960 case OPC_DMT:
6933 6961 check_insn(env, ctx, ASE_MT);
6934   - gen_op_dmt();
  6962 + tcg_gen_helper_0_0(do_dmt);
6935 6963 break;
6936 6964 case OPC_EMT:
6937 6965 check_insn(env, ctx, ASE_MT);
6938   - gen_op_emt();
  6966 + tcg_gen_helper_0_0(do_emt);
6939 6967 break;
6940 6968 case OPC_DVPE:
6941 6969 check_insn(env, ctx, ASE_MT);
6942   - gen_op_dvpe();
  6970 + tcg_gen_helper_0_0(do_dvpe);
6943 6971 break;
6944 6972 case OPC_EVPE:
6945 6973 check_insn(env, ctx, ASE_MT);
6946   - gen_op_evpe();
  6974 + tcg_gen_helper_0_0(do_evpe);
6947 6975 break;
6948 6976 case OPC_DI:
6949 6977 check_insn(env, ctx, ISA_MIPS32R2);
... ...