gwj / at91sam9263 · Commits

Commit ec6469a3b1da26247bdb3f5dd5276fabcc1b694a

Authored by aurel32
1 parent 2ef1b120

target-ppc: fixes for gen_op_neg() 

- Rename to gen_op_arith_neg for consistency with other functions.
- Correctly free TCG temp variable.
- Fix the return value in 64-bit mode in case of overflow.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5659 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 14 additions and 15 deletions
target-ppc/translate.c
  View file @ec6469a
... ... @@ -1288,44 +1288,43 @@ GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17);
1288 1288 #endif
1289 1289  
1290 1290 /* neg neg. nego nego. */
1291   -static always_inline void gen_op_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
  1291 +static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
1292 1292 {
1293   - int l1, l2;
1294   -
1295   - l1 = gen_new_label();
1296   - l2 = gen_new_label();
  1293 + int l1 = gen_new_label();
  1294 + int l2 = gen_new_label();
  1295 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
1297 1296 #if defined(TARGET_PPC64)
1298 1297 if (ctx->sf_mode) {
1299   - tcg_gen_brcondi_tl(TCG_COND_EQ, arg1, INT64_MIN, l1);
1300   - } else {
1301   - TCGv t0 = tcg_temp_new(TCG_TYPE_TL);
1302   - tcg_gen_ext32s_tl(t0, arg1);
  1298 + tcg_gen_movi_tl(t0, arg1);
  1299 + tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT64_MIN, l1);
  1300 + } else
  1301 +#endif
  1302 + {
  1303 + tcg_gen_ext32s_tl(t0, arg1);
1303 1304 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, INT32_MIN, l1);
1304 1305 }
1305   -#else
1306   - tcg_gen_brcondi_tl(TCG_COND_EQ, arg1, INT32_MIN, l1);
1307   -#endif
1308 1306 tcg_gen_neg_tl(ret, arg1);
1309 1307 if (ov_check) {
1310 1308 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
1311 1309 }
1312 1310 tcg_gen_br(l2);
1313 1311 gen_set_label(l1);
1314   - tcg_gen_mov_tl(ret, arg1);
  1312 + tcg_gen_mov_tl(ret, t0);
1315 1313 if (ov_check) {
1316 1314 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1317 1315 }
1318 1316 gen_set_label(l2);
  1317 + tcg_temp_free(t0);
1319 1318 if (unlikely(Rc(ctx->opcode) != 0))
1320 1319 gen_set_Rc0(ctx, ret);
1321 1320 }
1322 1321 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER)
1323 1322 {
1324   - gen_op_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
  1323 + gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0);
1325 1324 }
1326 1325 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER)
1327 1326 {
1328   - gen_op_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
  1327 + gen_op_arith_neg(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 1);
1329 1328 }
1330 1329  
1331 1330 /* Common subf function */
... ...