gwj / at91sam9263 · Commits

Commit 2ef1b120d1e8af5ab34fb6aed83ba171bd5f5572

Authored by aurel32
1 parent 1e4c090f

target-ppc: gen_op_arith_divw() & gen_op_arith_divd fixes 

gen_op_arith_divw():
- "deoptimize" gen_op_arith_divw to make it more readable.
- Correctly free TCG temp variable

gen_op_arith_divd():
- Call the right function.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5658 c046a42c-6fe2-441c-8c8c-71466251a162
Inline Side-by-side
Showing 1 changed file with 23 additions and 39 deletions
target-ppc/translate.c
  View file @2ef1b12
... ... @@ -1067,33 +1067,22 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
1067 1067 static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1068 1068 int sign, int compute_ov)
1069 1069 {
1070   - int l1, l2, l3;
1071   - TCGv t0, t1, t2;
  1070 + int l1 = gen_new_label();
  1071 + int l2 = gen_new_label();
  1072 + TCGv t0 = tcg_temp_local_new(TCG_TYPE_I32);
  1073 + TCGv t1 = tcg_temp_local_new(TCG_TYPE_I32);
1072 1074  
1073   -#if defined(TARGET_PPC64)
1074   - t0 = tcg_temp_local_new(TCG_TYPE_I32);
1075   - t1 = t0;
1076   - t2 = tcg_temp_local_new(TCG_TYPE_I32);
1077   - tcg_gen_trunc_i64_i32(t1, arg1);
1078   - tcg_gen_trunc_i64_i32(t2, arg2);
1079   -#else
1080   - t0 = ret;
1081   - t1 = arg1;
1082   - t2 = arg2;
1083   -#endif
1084   - l1 = gen_new_label();
1085   - l2 = gen_new_label();
1086   - tcg_gen_brcondi_i32(TCG_COND_EQ, t2, 0, l1);
  1075 + tcg_gen_trunc_tl_i32(t0, arg1);
  1076 + tcg_gen_trunc_tl_i32(t1, arg2);
  1077 + tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
1087 1078 if (sign) {
1088   - l3 = gen_new_label();
1089   - tcg_gen_brcondi_i32(TCG_COND_NE, t2, -1, l3);
1090   - tcg_gen_brcondi_i32(TCG_COND_EQ, t1, INT32_MIN, l1);
  1079 + int l3 = gen_new_label();
  1080 + tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
  1081 + tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
1091 1082 gen_set_label(l3);
1092   - }
1093   - if (sign) {
1094   - tcg_gen_div_i32(t0, t1, t2);
  1083 + tcg_gen_div_i32(t0, t0, t1);
1095 1084 } else {
1096   - tcg_gen_divu_i32(t0, t1, t2);
  1085 + tcg_gen_divu_i32(t0, t0, t1);
1097 1086 }
1098 1087 if (compute_ov) {
1099 1088 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~(1 << XER_OV));
... ... @@ -1101,7 +1090,7 @@ static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv a
1101 1090 tcg_gen_br(l2);
1102 1091 gen_set_label(l1);
1103 1092 if (sign) {
1104   - tcg_gen_sari_i32(t0, t1, 31);
  1093 + tcg_gen_sari_i32(t0, t0, 31);
1105 1094 } else {
1106 1095 tcg_gen_movi_i32(t0, 0);
1107 1096 }
... ... @@ -1109,10 +1098,9 @@ static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv a
1109 1098 tcg_gen_ori_tl(cpu_xer, cpu_xer, (1 << XER_OV) | (1 << XER_SO));
1110 1099 }
1111 1100 gen_set_label(l2);
1112   -#if defined(TARGET_PPC64)
1113   - tcg_gen_extu_i32_i64(ret, t0);
  1101 + tcg_gen_extu_i32_tl(ret, t0);
1114 1102 tcg_temp_free(t0);
1115   -#endif
  1103 + tcg_temp_free(t1);
1116 1104 if (unlikely(Rc(ctx->opcode) != 0))
1117 1105 gen_set_Rc0(ctx, ret);
1118 1106 }
... ... @@ -1131,22 +1119,18 @@ GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
1131 1119 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
1132 1120 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
1133 1121 #if defined(TARGET_PPC64)
1134   -static always_inline void gen_op_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
1135   - int sign, int compute_ov)
  1122 +static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
  1123 + int sign, int compute_ov)
1136 1124 {
1137   - int l1, l2, l3;
1138   -
1139   - l1 = gen_new_label();
1140   - l2 = gen_new_label();
  1125 + int l1 = gen_new_label();
  1126 + int l2 = gen_new_label();
1141 1127  
1142 1128 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1143 1129 if (sign) {
1144   - l3 = gen_new_label();
  1130 + int l3 = gen_new_label();
1145 1131 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1146 1132 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1147 1133 gen_set_label(l3);
1148   - }
1149   - if (sign) {
1150 1134 tcg_gen_div_i64(ret, arg1, arg2);
1151 1135 } else {
1152 1136 tcg_gen_divu_i64(ret, arg1, arg2);
... ... @@ -1171,9 +1155,9 @@ static always_inline void gen_op_divd (DisasContext *ctx, TCGv ret, TCGv arg1, T
1171 1155 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1172 1156 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) \
1173 1157 { \
1174   - gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
1175   - cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1176   - sign, compute_ov); \
  1158 + gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
  1159 + cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
  1160 + sign, compute_ov); \
1177 1161 }
1178 1162 /* divwu divwu. divwuo divwuo. */
1179 1163 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
... ...