Commit e2ea21b39660eb6938cb26a36248e23361d9534d
1 parent
1d01299d
Convert basic 64 bit VIS ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5191 c046a42c-6fe2-441c-8c8c-71466251a162
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4 changed files
with
65 additions
and
102 deletions
target-sparc/TODO
target-sparc/helper.h
... | ... | @@ -139,15 +139,6 @@ F_HELPER_0_0(dtox); |
139 | 139 | F_HELPER_0_0(qtox); |
140 | 140 | F_HELPER_0_0(aligndata); |
141 | 141 | |
142 | -F_HELPER_0_0(not); | |
143 | -F_HELPER_0_0(nor); | |
144 | -F_HELPER_0_0(or); | |
145 | -F_HELPER_0_0(xor); | |
146 | -F_HELPER_0_0(and); | |
147 | -F_HELPER_0_0(ornot); | |
148 | -F_HELPER_0_0(andnot); | |
149 | -F_HELPER_0_0(nand); | |
150 | -F_HELPER_0_0(xnor); | |
151 | 142 | F_HELPER_0_0(pmerge); |
152 | 143 | F_HELPER_0_0(mul8x16); |
153 | 144 | F_HELPER_0_0(mul8x16al); | ... | ... |
target-sparc/op_helper.c
... | ... | @@ -246,51 +246,6 @@ void helper_faligndata(void) |
246 | 246 | *((uint64_t *)&DT0) = tmp; |
247 | 247 | } |
248 | 248 | |
249 | -void helper_fnot(void) | |
250 | -{ | |
251 | - *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1; | |
252 | -} | |
253 | - | |
254 | -void helper_fnor(void) | |
255 | -{ | |
256 | - *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1); | |
257 | -} | |
258 | - | |
259 | -void helper_for(void) | |
260 | -{ | |
261 | - *(uint64_t *)&DT0 |= *(uint64_t *)&DT1; | |
262 | -} | |
263 | - | |
264 | -void helper_fxor(void) | |
265 | -{ | |
266 | - *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1; | |
267 | -} | |
268 | - | |
269 | -void helper_fand(void) | |
270 | -{ | |
271 | - *(uint64_t *)&DT0 &= *(uint64_t *)&DT1; | |
272 | -} | |
273 | - | |
274 | -void helper_fornot(void) | |
275 | -{ | |
276 | - *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1; | |
277 | -} | |
278 | - | |
279 | -void helper_fandnot(void) | |
280 | -{ | |
281 | - *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1; | |
282 | -} | |
283 | - | |
284 | -void helper_fnand(void) | |
285 | -{ | |
286 | - *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1); | |
287 | -} | |
288 | - | |
289 | -void helper_fxnor(void) | |
290 | -{ | |
291 | - *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1; | |
292 | -} | |
293 | - | |
294 | 249 | #ifdef WORDS_BIGENDIAN |
295 | 250 | #define VIS_B64(n) b[7 - (n)] |
296 | 251 | #define VIS_W64(n) w[3 - (n)] | ... | ... |
target-sparc/translate.c
... | ... | @@ -3886,10 +3886,12 @@ static void disas_sparc_insn(DisasContext * dc) |
3886 | 3886 | break; |
3887 | 3887 | case 0x062: /* VIS I fnor */ |
3888 | 3888 | CHECK_FPU_FEATURE(dc, VIS1); |
3889 | - gen_op_load_fpr_DT0(DFPREG(rs1)); | |
3890 | - gen_op_load_fpr_DT1(DFPREG(rs2)); | |
3891 | - tcg_gen_helper_0_0(helper_fnor); | |
3892 | - gen_op_store_DT0_fpr(DFPREG(rd)); | |
3889 | + tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], | |
3890 | + cpu_fpr[DFPREG(rs2)]); | |
3891 | + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1); | |
3892 | + tcg_gen_or_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], | |
3893 | + cpu_fpr[DFPREG(rs2) + 1]); | |
3894 | + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1); | |
3893 | 3895 | break; |
3894 | 3896 | case 0x063: /* VIS I fnors */ |
3895 | 3897 | CHECK_FPU_FEATURE(dc, VIS1); |
... | ... | @@ -3898,10 +3900,12 @@ static void disas_sparc_insn(DisasContext * dc) |
3898 | 3900 | break; |
3899 | 3901 | case 0x064: /* VIS I fandnot2 */ |
3900 | 3902 | CHECK_FPU_FEATURE(dc, VIS1); |
3901 | - gen_op_load_fpr_DT1(DFPREG(rs1)); | |
3902 | - gen_op_load_fpr_DT0(DFPREG(rs2)); | |
3903 | - tcg_gen_helper_0_0(helper_fandnot); | |
3904 | - gen_op_store_DT0_fpr(DFPREG(rd)); | |
3903 | + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1); | |
3904 | + tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, | |
3905 | + cpu_fpr[DFPREG(rs2)]); | |
3906 | + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1); | |
3907 | + tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, | |
3908 | + cpu_fpr[DFPREG(rs2) + 1]); | |
3905 | 3909 | break; |
3906 | 3910 | case 0x065: /* VIS I fandnot2s */ |
3907 | 3911 | CHECK_FPU_FEATURE(dc, VIS1); |
... | ... | @@ -3910,9 +3914,10 @@ static void disas_sparc_insn(DisasContext * dc) |
3910 | 3914 | break; |
3911 | 3915 | case 0x066: /* VIS I fnot2 */ |
3912 | 3916 | CHECK_FPU_FEATURE(dc, VIS1); |
3913 | - gen_op_load_fpr_DT1(DFPREG(rs2)); | |
3914 | - tcg_gen_helper_0_0(helper_fnot); | |
3915 | - gen_op_store_DT0_fpr(DFPREG(rd)); | |
3917 | + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs2)], | |
3918 | + -1); | |
3919 | + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], | |
3920 | + cpu_fpr[DFPREG(rs2) + 1], -1); | |
3916 | 3921 | break; |
3917 | 3922 | case 0x067: /* VIS I fnot2s */ |
3918 | 3923 | CHECK_FPU_FEATURE(dc, VIS1); |
... | ... | @@ -3920,10 +3925,12 @@ static void disas_sparc_insn(DisasContext * dc) |
3920 | 3925 | break; |
3921 | 3926 | case 0x068: /* VIS I fandnot1 */ |
3922 | 3927 | CHECK_FPU_FEATURE(dc, VIS1); |
3923 | - gen_op_load_fpr_DT0(DFPREG(rs1)); | |
3924 | - gen_op_load_fpr_DT1(DFPREG(rs2)); | |
3925 | - tcg_gen_helper_0_0(helper_fandnot); | |
3926 | - gen_op_store_DT0_fpr(DFPREG(rd)); | |
3928 | + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); | |
3929 | + tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, | |
3930 | + cpu_fpr[DFPREG(rs1)]); | |
3931 | + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); | |
3932 | + tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, | |
3933 | + cpu_fpr[DFPREG(rs1) + 1]); | |
3927 | 3934 | break; |
3928 | 3935 | case 0x069: /* VIS I fandnot1s */ |
3929 | 3936 | CHECK_FPU_FEATURE(dc, VIS1); |
... | ... | @@ -3932,9 +3939,10 @@ static void disas_sparc_insn(DisasContext * dc) |
3932 | 3939 | break; |
3933 | 3940 | case 0x06a: /* VIS I fnot1 */ |
3934 | 3941 | CHECK_FPU_FEATURE(dc, VIS1); |
3935 | - gen_op_load_fpr_DT1(DFPREG(rs1)); | |
3936 | - tcg_gen_helper_0_0(helper_fnot); | |
3937 | - gen_op_store_DT0_fpr(DFPREG(rd)); | |
3942 | + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], | |
3943 | + -1); | |
3944 | + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], | |
3945 | + cpu_fpr[DFPREG(rs1) + 1], -1); | |
3938 | 3946 | break; |
3939 | 3947 | case 0x06b: /* VIS I fnot1s */ |
3940 | 3948 | CHECK_FPU_FEATURE(dc, VIS1); |
... | ... | @@ -3942,10 +3950,11 @@ static void disas_sparc_insn(DisasContext * dc) |
3942 | 3950 | break; |
3943 | 3951 | case 0x06c: /* VIS I fxor */ |
3944 | 3952 | CHECK_FPU_FEATURE(dc, VIS1); |
3945 | - gen_op_load_fpr_DT0(DFPREG(rs1)); | |
3946 | - gen_op_load_fpr_DT1(DFPREG(rs2)); | |
3947 | - tcg_gen_helper_0_0(helper_fxor); | |
3948 | - gen_op_store_DT0_fpr(DFPREG(rd)); | |
3953 | + tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], | |
3954 | + cpu_fpr[DFPREG(rs2)]); | |
3955 | + tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], | |
3956 | + cpu_fpr[DFPREG(rs1) + 1], | |
3957 | + cpu_fpr[DFPREG(rs2) + 1]); | |
3949 | 3958 | break; |
3950 | 3959 | case 0x06d: /* VIS I fxors */ |
3951 | 3960 | CHECK_FPU_FEATURE(dc, VIS1); |
... | ... | @@ -3953,10 +3962,12 @@ static void disas_sparc_insn(DisasContext * dc) |
3953 | 3962 | break; |
3954 | 3963 | case 0x06e: /* VIS I fnand */ |
3955 | 3964 | CHECK_FPU_FEATURE(dc, VIS1); |
3956 | - gen_op_load_fpr_DT0(DFPREG(rs1)); | |
3957 | - gen_op_load_fpr_DT1(DFPREG(rs2)); | |
3958 | - tcg_gen_helper_0_0(helper_fnand); | |
3959 | - gen_op_store_DT0_fpr(DFPREG(rd)); | |
3965 | + tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], | |
3966 | + cpu_fpr[DFPREG(rs2)]); | |
3967 | + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, -1); | |
3968 | + tcg_gen_and_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], | |
3969 | + cpu_fpr[DFPREG(rs2) + 1]); | |
3970 | + tcg_gen_xori_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, -1); | |
3960 | 3971 | break; |
3961 | 3972 | case 0x06f: /* VIS I fnands */ |
3962 | 3973 | CHECK_FPU_FEATURE(dc, VIS1); |
... | ... | @@ -3965,10 +3976,11 @@ static void disas_sparc_insn(DisasContext * dc) |
3965 | 3976 | break; |
3966 | 3977 | case 0x070: /* VIS I fand */ |
3967 | 3978 | CHECK_FPU_FEATURE(dc, VIS1); |
3968 | - gen_op_load_fpr_DT0(DFPREG(rs1)); | |
3969 | - gen_op_load_fpr_DT1(DFPREG(rs2)); | |
3970 | - tcg_gen_helper_0_0(helper_fand); | |
3971 | - gen_op_store_DT0_fpr(DFPREG(rd)); | |
3979 | + tcg_gen_and_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], | |
3980 | + cpu_fpr[DFPREG(rs2)]); | |
3981 | + tcg_gen_and_i32(cpu_fpr[DFPREG(rd) + 1], | |
3982 | + cpu_fpr[DFPREG(rs1) + 1], | |
3983 | + cpu_fpr[DFPREG(rs2) + 1]); | |
3972 | 3984 | break; |
3973 | 3985 | case 0x071: /* VIS I fands */ |
3974 | 3986 | CHECK_FPU_FEATURE(dc, VIS1); |
... | ... | @@ -3976,10 +3988,12 @@ static void disas_sparc_insn(DisasContext * dc) |
3976 | 3988 | break; |
3977 | 3989 | case 0x072: /* VIS I fxnor */ |
3978 | 3990 | CHECK_FPU_FEATURE(dc, VIS1); |
3979 | - gen_op_load_fpr_DT0(DFPREG(rs1)); | |
3980 | - gen_op_load_fpr_DT1(DFPREG(rs2)); | |
3981 | - tcg_gen_helper_0_0(helper_fxnor); | |
3982 | - gen_op_store_DT0_fpr(DFPREG(rd)); | |
3991 | + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); | |
3992 | + tcg_gen_xor_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, | |
3993 | + cpu_fpr[DFPREG(rs1)]); | |
3994 | + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1); | |
3995 | + tcg_gen_xor_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, | |
3996 | + cpu_fpr[DFPREG(rs1) + 1]); | |
3983 | 3997 | break; |
3984 | 3998 | case 0x073: /* VIS I fxnors */ |
3985 | 3999 | CHECK_FPU_FEATURE(dc, VIS1); |
... | ... | @@ -3998,10 +4012,12 @@ static void disas_sparc_insn(DisasContext * dc) |
3998 | 4012 | break; |
3999 | 4013 | case 0x076: /* VIS I fornot2 */ |
4000 | 4014 | CHECK_FPU_FEATURE(dc, VIS1); |
4001 | - gen_op_load_fpr_DT1(DFPREG(rs1)); | |
4002 | - gen_op_load_fpr_DT0(DFPREG(rs2)); | |
4003 | - tcg_gen_helper_0_0(helper_fornot); | |
4004 | - gen_op_store_DT0_fpr(DFPREG(rd)); | |
4015 | + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1)], -1); | |
4016 | + tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, | |
4017 | + cpu_fpr[DFPREG(rs2)]); | |
4018 | + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs1) + 1], -1); | |
4019 | + tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, | |
4020 | + cpu_fpr[DFPREG(rs2) + 1]); | |
4005 | 4021 | break; |
4006 | 4022 | case 0x077: /* VIS I fornot2s */ |
4007 | 4023 | CHECK_FPU_FEATURE(dc, VIS1); |
... | ... | @@ -4019,10 +4035,12 @@ static void disas_sparc_insn(DisasContext * dc) |
4019 | 4035 | break; |
4020 | 4036 | case 0x07a: /* VIS I fornot1 */ |
4021 | 4037 | CHECK_FPU_FEATURE(dc, VIS1); |
4022 | - gen_op_load_fpr_DT0(DFPREG(rs1)); | |
4023 | - gen_op_load_fpr_DT1(DFPREG(rs2)); | |
4024 | - tcg_gen_helper_0_0(helper_fornot); | |
4025 | - gen_op_store_DT0_fpr(DFPREG(rd)); | |
4038 | + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2)], -1); | |
4039 | + tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_tmp32, | |
4040 | + cpu_fpr[DFPREG(rs1)]); | |
4041 | + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[DFPREG(rs2) + 1], -1); | |
4042 | + tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], cpu_tmp32, | |
4043 | + cpu_fpr[DFPREG(rs1) + 1]); | |
4026 | 4044 | break; |
4027 | 4045 | case 0x07b: /* VIS I fornot1s */ |
4028 | 4046 | CHECK_FPU_FEATURE(dc, VIS1); |
... | ... | @@ -4031,10 +4049,11 @@ static void disas_sparc_insn(DisasContext * dc) |
4031 | 4049 | break; |
4032 | 4050 | case 0x07c: /* VIS I for */ |
4033 | 4051 | CHECK_FPU_FEATURE(dc, VIS1); |
4034 | - gen_op_load_fpr_DT0(DFPREG(rs1)); | |
4035 | - gen_op_load_fpr_DT1(DFPREG(rs2)); | |
4036 | - tcg_gen_helper_0_0(helper_for); | |
4037 | - gen_op_store_DT0_fpr(DFPREG(rd)); | |
4052 | + tcg_gen_or_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)], | |
4053 | + cpu_fpr[DFPREG(rs2)]); | |
4054 | + tcg_gen_or_i32(cpu_fpr[DFPREG(rd) + 1], | |
4055 | + cpu_fpr[DFPREG(rs1) + 1], | |
4056 | + cpu_fpr[DFPREG(rs2) + 1]); | |
4038 | 4057 | break; |
4039 | 4058 | case 0x07d: /* VIS I fors */ |
4040 | 4059 | CHECK_FPU_FEATURE(dc, VIS1); | ... | ... |