gwj / at91sam9263 · Commits

Commit 1d01299d29184c2d48af843626e0d7a5ef21aef7

Authored by blueswir1
1 parent 714547bb

Convert basic 32 bit VIS ops to TCG 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5190 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 3 changed files with 48 additions and 164 deletions
target-sparc/helper.h
  View file @1d01299
... ... @@ -138,29 +138,16 @@ F_HELPER_0_0(stox);
138 138 F_HELPER_0_0(dtox);
139 139 F_HELPER_0_0(qtox);
140 140 F_HELPER_0_0(aligndata);
141   -DEF_HELPER(void, helper_movl_FT0_0, (void))
142   -DEF_HELPER(void, helper_movl_DT0_0, (void))
143   -DEF_HELPER(void, helper_movl_FT0_1, (void))
144   -DEF_HELPER(void, helper_movl_DT0_1, (void))
145 141  
146 142 F_HELPER_0_0(not);
147   -F_HELPER_0_0(nots);
148 143 F_HELPER_0_0(nor);
149   -F_HELPER_0_0(nors);
150 144 F_HELPER_0_0(or);
151   -F_HELPER_0_0(ors);
152 145 F_HELPER_0_0(xor);
153   -F_HELPER_0_0(xors);
154 146 F_HELPER_0_0(and);
155   -F_HELPER_0_0(ands);
156 147 F_HELPER_0_0(ornot);
157   -F_HELPER_0_0(ornots);
158 148 F_HELPER_0_0(andnot);
159   -F_HELPER_0_0(andnots);
160 149 F_HELPER_0_0(nand);
161   -F_HELPER_0_0(nands);
162 150 F_HELPER_0_0(xnor);
163   -F_HELPER_0_0(xnors);
164 151 F_HELPER_0_0(pmerge);
165 152 F_HELPER_0_0(mul8x16);
166 153 F_HELPER_0_0(mul8x16al);
... ... @@ -172,9 +159,9 @@ F_HELPER_0_0(muld8ulx16);
172 159 F_HELPER_0_0(expand);
173 160 #define VIS_HELPER(name) \
174 161 F_HELPER_0_0(name##16); \
175   - F_HELPER_0_0(name##16s); \
  162 + DEF_HELPER(uint32_t, helper_f ## name ## 16s, (uint32_t src1, uint32_t src2))\
176 163 F_HELPER_0_0(name##32); \
177   - F_HELPER_0_0(name##32s)
  164 + DEF_HELPER(uint32_t, helper_f ## name ## 32s, (uint32_t src1, uint32_t src2))
178 165  
179 166 VIS_HELPER(padd);
180 167 VIS_HELPER(psub);
... ...
target-sparc/op_helper.c
  View file @1d01299
... ... @@ -246,116 +246,51 @@ void helper_faligndata(void)
246 246 *((uint64_t *)&DT0) = tmp;
247 247 }
248 248  
249   -void helper_movl_FT0_0(void)
250   -{
251   - *((uint32_t *)&FT0) = 0;
252   -}
253   -
254   -void helper_movl_DT0_0(void)
255   -{
256   - *((uint64_t *)&DT0) = 0;
257   -}
258   -
259   -void helper_movl_FT0_1(void)
260   -{
261   - *((uint32_t *)&FT0) = 0xffffffff;
262   -}
263   -
264   -void helper_movl_DT0_1(void)
265   -{
266   - *((uint64_t *)&DT0) = 0xffffffffffffffffULL;
267   -}
268   -
269 249 void helper_fnot(void)
270 250 {
271 251 *(uint64_t *)&DT0 = ~*(uint64_t *)&DT1;
272 252 }
273 253  
274   -void helper_fnots(void)
275   -{
276   - *(uint32_t *)&FT0 = ~*(uint32_t *)&FT1;
277   -}
278   -
279 254 void helper_fnor(void)
280 255 {
281 256 *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 | *(uint64_t *)&DT1);
282 257 }
283 258  
284   -void helper_fnors(void)
285   -{
286   - *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 | *(uint32_t *)&FT1);
287   -}
288   -
289 259 void helper_for(void)
290 260 {
291 261 *(uint64_t *)&DT0 |= *(uint64_t *)&DT1;
292 262 }
293 263  
294   -void helper_fors(void)
295   -{
296   - *(uint32_t *)&FT0 |= *(uint32_t *)&FT1;
297   -}
298   -
299 264 void helper_fxor(void)
300 265 {
301 266 *(uint64_t *)&DT0 ^= *(uint64_t *)&DT1;
302 267 }
303 268  
304   -void helper_fxors(void)
305   -{
306   - *(uint32_t *)&FT0 ^= *(uint32_t *)&FT1;
307   -}
308   -
309 269 void helper_fand(void)
310 270 {
311 271 *(uint64_t *)&DT0 &= *(uint64_t *)&DT1;
312 272 }
313 273  
314   -void helper_fands(void)
315   -{
316   - *(uint32_t *)&FT0 &= *(uint32_t *)&FT1;
317   -}
318   -
319 274 void helper_fornot(void)
320 275 {
321 276 *(uint64_t *)&DT0 = *(uint64_t *)&DT0 | ~*(uint64_t *)&DT1;
322 277 }
323 278  
324   -void helper_fornots(void)
325   -{
326   - *(uint32_t *)&FT0 = *(uint32_t *)&FT0 | ~*(uint32_t *)&FT1;
327   -}
328   -
329 279 void helper_fandnot(void)
330 280 {
331 281 *(uint64_t *)&DT0 = *(uint64_t *)&DT0 & ~*(uint64_t *)&DT1;
332 282 }
333 283  
334   -void helper_fandnots(void)
335   -{
336   - *(uint32_t *)&FT0 = *(uint32_t *)&FT0 & ~*(uint32_t *)&FT1;
337   -}
338   -
339 284 void helper_fnand(void)
340 285 {
341 286 *(uint64_t *)&DT0 = ~(*(uint64_t *)&DT0 & *(uint64_t *)&DT1);
342 287 }
343 288  
344   -void helper_fnands(void)
345   -{
346   - *(uint32_t *)&FT0 = ~(*(uint32_t *)&FT0 & *(uint32_t *)&FT1);
347   -}
348   -
349 289 void helper_fxnor(void)
350 290 {
351 291 *(uint64_t *)&DT0 ^= ~*(uint64_t *)&DT1;
352 292 }
353 293  
354   -void helper_fxnors(void)
355   -{
356   - *(uint32_t *)&FT0 ^= ~*(uint32_t *)&FT1;
357   -}
358   -
359 294 #ifdef WORDS_BIGENDIAN
360 295 #define VIS_B64(n) b[7 - (n)]
361 296 #define VIS_W64(n) w[3 - (n)]
... ... @@ -597,17 +532,17 @@ void helper_fexpand(void)
597 532 DT0 = d.d; \
598 533 } \
599 534 \
600   - void name##16s(void) \
  535 + uint32_t name##16s(uint32_t src1, uint32_t src2) \
601 536 { \
602 537 vis32 s, d; \
603 538 \
604   - s.f = FT0; \
605   - d.f = FT1; \
  539 + s.l = src1; \
  540 + d.l = src2; \
606 541 \
607 542 d.VIS_W32(0) = F(d.VIS_W32(0), s.VIS_W32(0)); \
608 543 d.VIS_W32(1) = F(d.VIS_W32(1), s.VIS_W32(1)); \
609 544 \
610   - FT0 = d.f; \
  545 + return d.l; \
611 546 } \
612 547 \
613 548 void name##32(void) \
... ... @@ -623,16 +558,16 @@ void helper_fexpand(void)
623 558 DT0 = d.d; \
624 559 } \
625 560 \
626   - void name##32s(void) \
  561 + uint32_t name##32s(uint32_t src1, uint32_t src2) \
627 562 { \
628 563 vis32 s, d; \
629 564 \
630   - s.f = FT0; \
631   - d.f = FT1; \
  565 + s.l = src1; \
  566 + d.l = src2; \
632 567 \
633 568 d.l = F(d.l, s.l); \
634 569 \
635   - FT0 = d.f; \
  570 + return d.l; \
636 571 }
637 572  
638 573 #define FADD(a, b) ((a) + (b))
... ...
target-sparc/translate.c
  View file @1d01299
... ... @@ -3836,10 +3836,8 @@ static void disas_sparc_insn(DisasContext * dc)
3836 3836 break;
3837 3837 case 0x051: /* VIS I fpadd16s */
3838 3838 CHECK_FPU_FEATURE(dc, VIS1);
3839   - gen_op_load_fpr_FT0(rs1);
3840   - gen_op_load_fpr_FT1(rs2);
3841   - tcg_gen_helper_0_0(helper_fpadd16s);
3842   - gen_op_store_FT0_fpr(rd);
  3839 + tcg_gen_helper_1_2(helper_fpadd16s, cpu_fpr[rd],
  3840 + cpu_fpr[rs1], cpu_fpr[rs2]);
3843 3841 break;
3844 3842 case 0x052: /* VIS I fpadd32 */
3845 3843 CHECK_FPU_FEATURE(dc, VIS1);
... ... @@ -3850,10 +3848,8 @@ static void disas_sparc_insn(DisasContext * dc)
3850 3848 break;
3851 3849 case 0x053: /* VIS I fpadd32s */
3852 3850 CHECK_FPU_FEATURE(dc, VIS1);
3853   - gen_op_load_fpr_FT0(rs1);
3854   - gen_op_load_fpr_FT1(rs2);
3855   - tcg_gen_helper_0_0(helper_fpadd32s);
3856   - gen_op_store_FT0_fpr(rd);
  3851 + tcg_gen_helper_1_2(helper_fpadd32s, cpu_fpr[rd],
  3852 + cpu_fpr[rs1], cpu_fpr[rs2]);
3857 3853 break;
3858 3854 case 0x054: /* VIS I fpsub16 */
3859 3855 CHECK_FPU_FEATURE(dc, VIS1);
... ... @@ -3864,10 +3860,8 @@ static void disas_sparc_insn(DisasContext * dc)
3864 3860 break;
3865 3861 case 0x055: /* VIS I fpsub16s */
3866 3862 CHECK_FPU_FEATURE(dc, VIS1);
3867   - gen_op_load_fpr_FT0(rs1);
3868   - gen_op_load_fpr_FT1(rs2);
3869   - tcg_gen_helper_0_0(helper_fpsub16s);
3870   - gen_op_store_FT0_fpr(rd);
  3863 + tcg_gen_helper_1_2(helper_fpsub16s, cpu_fpr[rd],
  3864 + cpu_fpr[rs1], cpu_fpr[rs2]);
3871 3865 break;
3872 3866 case 0x056: /* VIS I fpsub32 */
3873 3867 CHECK_FPU_FEATURE(dc, VIS1);
... ... @@ -3878,20 +3872,17 @@ static void disas_sparc_insn(DisasContext * dc)
3878 3872 break;
3879 3873 case 0x057: /* VIS I fpsub32s */
3880 3874 CHECK_FPU_FEATURE(dc, VIS1);
3881   - gen_op_load_fpr_FT0(rs1);
3882   - gen_op_load_fpr_FT1(rs2);
3883   - tcg_gen_helper_0_0(helper_fpsub32s);
3884   - gen_op_store_FT0_fpr(rd);
  3875 + tcg_gen_helper_1_2(helper_fpsub32s, cpu_fpr[rd],
  3876 + cpu_fpr[rs1], cpu_fpr[rs2]);
3885 3877 break;
3886 3878 case 0x060: /* VIS I fzero */
3887 3879 CHECK_FPU_FEATURE(dc, VIS1);
3888   - tcg_gen_helper_0_0(helper_movl_DT0_0);
3889   - gen_op_store_DT0_fpr(DFPREG(rd));
  3880 + tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], 0);
  3881 + tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], 0);
3890 3882 break;
3891 3883 case 0x061: /* VIS I fzeros */
3892 3884 CHECK_FPU_FEATURE(dc, VIS1);
3893   - tcg_gen_helper_0_0(helper_movl_FT0_0);
3894   - gen_op_store_FT0_fpr(rd);
  3885 + tcg_gen_movi_i32(cpu_fpr[rd], 0);
3895 3886 break;
3896 3887 case 0x062: /* VIS I fnor */
3897 3888 CHECK_FPU_FEATURE(dc, VIS1);
... ... @@ -3902,10 +3893,8 @@ static void disas_sparc_insn(DisasContext * dc)
3902 3893 break;
3903 3894 case 0x063: /* VIS I fnors */
3904 3895 CHECK_FPU_FEATURE(dc, VIS1);
3905   - gen_op_load_fpr_FT0(rs1);
3906   - gen_op_load_fpr_FT1(rs2);
3907   - tcg_gen_helper_0_0(helper_fnors);
3908   - gen_op_store_FT0_fpr(rd);
  3896 + tcg_gen_or_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
  3897 + tcg_gen_xori_i32(cpu_fpr[rd], cpu_tmp32, -1);
3909 3898 break;
3910 3899 case 0x064: /* VIS I fandnot2 */
3911 3900 CHECK_FPU_FEATURE(dc, VIS1);
... ... @@ -3916,10 +3905,8 @@ static void disas_sparc_insn(DisasContext * dc)
3916 3905 break;
3917 3906 case 0x065: /* VIS I fandnot2s */
3918 3907 CHECK_FPU_FEATURE(dc, VIS1);
3919   - gen_op_load_fpr_FT1(rs1);
3920   - gen_op_load_fpr_FT0(rs2);
3921   - tcg_gen_helper_0_0(helper_fandnots);
3922   - gen_op_store_FT0_fpr(rd);
  3908 + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs1], -1);
  3909 + tcg_gen_and_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs2]);
3923 3910 break;
3924 3911 case 0x066: /* VIS I fnot2 */
3925 3912 CHECK_FPU_FEATURE(dc, VIS1);
... ... @@ -3929,9 +3916,7 @@ static void disas_sparc_insn(DisasContext * dc)
3929 3916 break;
3930 3917 case 0x067: /* VIS I fnot2s */
3931 3918 CHECK_FPU_FEATURE(dc, VIS1);
3932   - gen_op_load_fpr_FT1(rs2);
3933   - tcg_gen_helper_0_0(helper_fnot);
3934   - gen_op_store_FT0_fpr(rd);
  3919 + tcg_gen_xori_i32(cpu_fpr[rd], cpu_fpr[rs2], -1);
3935 3920 break;
3936 3921 case 0x068: /* VIS I fandnot1 */
3937 3922 CHECK_FPU_FEATURE(dc, VIS1);
... ... @@ -3942,10 +3927,8 @@ static void disas_sparc_insn(DisasContext * dc)
3942 3927 break;
3943 3928 case 0x069: /* VIS I fandnot1s */
3944 3929 CHECK_FPU_FEATURE(dc, VIS1);
3945   - gen_op_load_fpr_FT0(rs1);
3946   - gen_op_load_fpr_FT1(rs2);
3947   - tcg_gen_helper_0_0(helper_fandnots);
3948   - gen_op_store_FT0_fpr(rd);
  3930 + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
  3931 + tcg_gen_and_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]);
3949 3932 break;
3950 3933 case 0x06a: /* VIS I fnot1 */
3951 3934 CHECK_FPU_FEATURE(dc, VIS1);
... ... @@ -3955,9 +3938,7 @@ static void disas_sparc_insn(DisasContext * dc)
3955 3938 break;
3956 3939 case 0x06b: /* VIS I fnot1s */
3957 3940 CHECK_FPU_FEATURE(dc, VIS1);
3958   - gen_op_load_fpr_FT1(rs1);
3959   - tcg_gen_helper_0_0(helper_fnot);
3960   - gen_op_store_FT0_fpr(rd);
  3941 + tcg_gen_xori_i32(cpu_fpr[rd], cpu_fpr[rs1], -1);
3961 3942 break;
3962 3943 case 0x06c: /* VIS I fxor */
3963 3944 CHECK_FPU_FEATURE(dc, VIS1);
... ... @@ -3968,10 +3949,7 @@ static void disas_sparc_insn(DisasContext * dc)
3968 3949 break;
3969 3950 case 0x06d: /* VIS I fxors */
3970 3951 CHECK_FPU_FEATURE(dc, VIS1);
3971   - gen_op_load_fpr_FT0(rs1);
3972   - gen_op_load_fpr_FT1(rs2);
3973   - tcg_gen_helper_0_0(helper_fxors);
3974   - gen_op_store_FT0_fpr(rd);
  3952 + tcg_gen_xor_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
3975 3953 break;
3976 3954 case 0x06e: /* VIS I fnand */
3977 3955 CHECK_FPU_FEATURE(dc, VIS1);
... ... @@ -3982,10 +3960,8 @@ static void disas_sparc_insn(DisasContext * dc)
3982 3960 break;
3983 3961 case 0x06f: /* VIS I fnands */
3984 3962 CHECK_FPU_FEATURE(dc, VIS1);
3985   - gen_op_load_fpr_FT0(rs1);
3986   - gen_op_load_fpr_FT1(rs2);
3987   - tcg_gen_helper_0_0(helper_fnands);
3988   - gen_op_store_FT0_fpr(rd);
  3963 + tcg_gen_and_i32(cpu_tmp32, cpu_fpr[rs1], cpu_fpr[rs2]);
  3964 + tcg_gen_xori_i32(cpu_fpr[rd], cpu_tmp32, -1);
3989 3965 break;
3990 3966 case 0x070: /* VIS I fand */
3991 3967 CHECK_FPU_FEATURE(dc, VIS1);
... ... @@ -3996,10 +3972,7 @@ static void disas_sparc_insn(DisasContext * dc)
3996 3972 break;
3997 3973 case 0x071: /* VIS I fands */
3998 3974 CHECK_FPU_FEATURE(dc, VIS1);
3999   - gen_op_load_fpr_FT0(rs1);
4000   - gen_op_load_fpr_FT1(rs2);
4001   - tcg_gen_helper_0_0(helper_fands);
4002   - gen_op_store_FT0_fpr(rd);
  3975 + tcg_gen_and_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
4003 3976 break;
4004 3977 case 0x072: /* VIS I fxnor */
4005 3978 CHECK_FPU_FEATURE(dc, VIS1);
... ... @@ -4010,20 +3983,18 @@ static void disas_sparc_insn(DisasContext * dc)
4010 3983 break;
4011 3984 case 0x073: /* VIS I fxnors */
4012 3985 CHECK_FPU_FEATURE(dc, VIS1);
4013   - gen_op_load_fpr_FT0(rs1);
4014   - gen_op_load_fpr_FT1(rs2);
4015   - tcg_gen_helper_0_0(helper_fxnors);
4016   - gen_op_store_FT0_fpr(rd);
  3986 + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
  3987 + tcg_gen_xor_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]);
4017 3988 break;
4018 3989 case 0x074: /* VIS I fsrc1 */
4019 3990 CHECK_FPU_FEATURE(dc, VIS1);
4020   - gen_op_load_fpr_DT0(DFPREG(rs1));
4021   - gen_op_store_DT0_fpr(DFPREG(rd));
  3991 + tcg_gen_mov_i32(cpu_fpr[DFPREG(rd)], cpu_fpr[DFPREG(rs1)]);
  3992 + tcg_gen_mov_i32(cpu_fpr[DFPREG(rd) + 1],
  3993 + cpu_fpr[DFPREG(rs1) + 1]);
4022 3994 break;
4023 3995 case 0x075: /* VIS I fsrc1s */
4024 3996 CHECK_FPU_FEATURE(dc, VIS1);
4025   - gen_op_load_fpr_FT0(rs1);
4026   - gen_op_store_FT0_fpr(rd);
  3997 + tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs1]);
4027 3998 break;
4028 3999 case 0x076: /* VIS I fornot2 */
4029 4000 CHECK_FPU_FEATURE(dc, VIS1);
... ... @@ -4034,10 +4005,8 @@ static void disas_sparc_insn(DisasContext * dc)
4034 4005 break;
4035 4006 case 0x077: /* VIS I fornot2s */
4036 4007 CHECK_FPU_FEATURE(dc, VIS1);
4037   - gen_op_load_fpr_FT1(rs1);
4038   - gen_op_load_fpr_FT0(rs2);
4039   - tcg_gen_helper_0_0(helper_fornots);
4040   - gen_op_store_FT0_fpr(rd);
  4008 + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs1], -1);
  4009 + tcg_gen_or_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs2]);
4041 4010 break;
4042 4011 case 0x078: /* VIS I fsrc2 */
4043 4012 CHECK_FPU_FEATURE(dc, VIS1);
... ... @@ -4046,8 +4015,7 @@ static void disas_sparc_insn(DisasContext * dc)
4046 4015 break;
4047 4016 case 0x079: /* VIS I fsrc2s */
4048 4017 CHECK_FPU_FEATURE(dc, VIS1);
4049   - gen_op_load_fpr_FT0(rs2);
4050   - gen_op_store_FT0_fpr(rd);
  4018 + tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]);
4051 4019 break;
4052 4020 case 0x07a: /* VIS I fornot1 */
4053 4021 CHECK_FPU_FEATURE(dc, VIS1);
... ... @@ -4058,10 +4026,8 @@ static void disas_sparc_insn(DisasContext * dc)
4058 4026 break;
4059 4027 case 0x07b: /* VIS I fornot1s */
4060 4028 CHECK_FPU_FEATURE(dc, VIS1);
4061   - gen_op_load_fpr_FT0(rs1);
4062   - gen_op_load_fpr_FT1(rs2);
4063   - tcg_gen_helper_0_0(helper_fornots);
4064   - gen_op_store_FT0_fpr(rd);
  4029 + tcg_gen_xori_i32(cpu_tmp32, cpu_fpr[rs2], -1);
  4030 + tcg_gen_or_i32(cpu_fpr[rd], cpu_tmp32, cpu_fpr[rs1]);
4065 4031 break;
4066 4032 case 0x07c: /* VIS I for */
4067 4033 CHECK_FPU_FEATURE(dc, VIS1);
... ... @@ -4072,20 +4038,16 @@ static void disas_sparc_insn(DisasContext * dc)
4072 4038 break;
4073 4039 case 0x07d: /* VIS I fors */
4074 4040 CHECK_FPU_FEATURE(dc, VIS1);
4075   - gen_op_load_fpr_FT0(rs1);
4076   - gen_op_load_fpr_FT1(rs2);
4077   - tcg_gen_helper_0_0(helper_fors);
4078   - gen_op_store_FT0_fpr(rd);
  4041 + tcg_gen_or_i32(cpu_fpr[rd], cpu_fpr[rs1], cpu_fpr[rs2]);
4079 4042 break;
4080 4043 case 0x07e: /* VIS I fone */
4081 4044 CHECK_FPU_FEATURE(dc, VIS1);
4082   - tcg_gen_helper_0_0(helper_movl_DT0_1);
4083   - gen_op_store_DT0_fpr(DFPREG(rd));
  4045 + tcg_gen_movi_i32(cpu_fpr[DFPREG(rd)], -1);
  4046 + tcg_gen_movi_i32(cpu_fpr[DFPREG(rd) + 1], -1);
4084 4047 break;
4085 4048 case 0x07f: /* VIS I fones */
4086 4049 CHECK_FPU_FEATURE(dc, VIS1);
4087   - tcg_gen_helper_0_0(helper_movl_FT0_1);
4088   - gen_op_store_FT0_fpr(rd);
  4050 + tcg_gen_movi_i32(cpu_fpr[rd], -1);
4089 4051 break;
4090 4052 case 0x080: /* VIS I shutdown */
4091 4053 case 0x081: /* VIS II siam */
... ...