gwj / at91sam9263 · Commits

Commit e0c84da78c3bc78e9920d99cdca0d111417ecc2f

Authored by ths
1 parent cbeb0857

Implement prefx. 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2630 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 1 changed file with 41 additions and 1 deletions
target-mips/translate.c
  View file @e0c84da
... ... @@ -358,7 +358,44 @@ enum {
358 358 #define MASK_CP1_FUNC(op) MASK_CP1(op) | (op & 0x3F)
359 359  
360 360 #define MASK_CP2(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
361   -#define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21))
  361 +
  362 +enum {
  363 + OPC_MFC2 = (0x00 << 21) | OPC_CP2,
  364 + OPC_DMFC2 = (0x01 << 21) | OPC_CP2,
  365 + OPC_CFC2 = (0x02 << 21) | OPC_CP2,
  366 + OPC_MFHC2 = (0x03 << 21) | OPC_CP2,
  367 + OPC_MTC2 = (0x04 << 21) | OPC_CP2,
  368 + OPC_DMTC2 = (0x05 << 21) | OPC_CP2,
  369 + OPC_CTC2 = (0x06 << 21) | OPC_CP2,
  370 + OPC_MTHC2 = (0x07 << 21) | OPC_CP2,
  371 + OPC_BC2 = (0x08 << 21) | OPC_CP2,
  372 +};
  373 +
  374 +#define MASK_CP3(op) MASK_OP_MAJOR(op) | (op & 0x3F)
  375 +
  376 +enum {
  377 + OPC_LWXC1 = 0x00 | OPC_CP3,
  378 + OPC_LDXC1 = 0x01 | OPC_CP3,
  379 + OPC_LUXC1 = 0x05 | OPC_CP3,
  380 + OPC_SWXC1 = 0x08 | OPC_CP3,
  381 + OPC_SDXC1 = 0x09 | OPC_CP3,
  382 + OPC_SUXC1 = 0x0D | OPC_CP3,
  383 + OPC_PREFX = 0x0F | OPC_CP3,
  384 + OPC_ALNV_PS = 0x1E | OPC_CP3,
  385 + OPC_MADD_S = 0x20 | OPC_CP3,
  386 + OPC_MADD_D = 0x21 | OPC_CP3,
  387 + OPC_MADD_PS = 0x26 | OPC_CP3,
  388 + OPC_MSUB_S = 0x28 | OPC_CP3,
  389 + OPC_MSUB_D = 0x29 | OPC_CP3,
  390 + OPC_MSUB_PS = 0x2E | OPC_CP3,
  391 + OPC_NMADD_S = 0x30 | OPC_CP3,
  392 + OPC_NMADD_D = 0x32 | OPC_CP3,
  393 + OPC_NMADD_PS= 0x36 | OPC_CP3,
  394 + OPC_NMSUB_S = 0x38 | OPC_CP3,
  395 + OPC_NMSUB_D = 0x39 | OPC_CP3,
  396 + OPC_NMSUB_PS= 0x3E | OPC_CP3,
  397 +};
  398 +
362 399  
363 400 const unsigned char *regnames[] =
364 401 { "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
... ... @@ -5019,6 +5056,9 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
5019 5056 gen_op_cp1_enabled();
5020 5057 op1 = MASK_CP3(ctx->opcode);
5021 5058 switch (op1) {
  5059 + case OPC_PREFX:
  5060 + /* treat as noop */
  5061 + break;
5022 5062 /* Not implemented */
5023 5063 default:
5024 5064 generate_exception (ctx, EXCP_RI);
... ...