gwj / at91sam9263 · Commits

Commit d656469f44aa541b1e2ca4019fef101b60557aac

Authored by bellard
1 parent 0019ad53

use simpler REGPARM convention - make CPUTLBEntry size a power of two 


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3935 c046a42c-6fe2-441c-8c8c-71466251a162
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Showing 4 changed files with 28 additions and 17 deletions
cpu-defs.h
  View file @d656469
@@ -102,6 +102,12 @@ typedef unsigned long ram_addr_t; @@ -102,6 +102,12 @@ typedef unsigned long ram_addr_t;
102 #define CPU_TLB_BITS 8 102 #define CPU_TLB_BITS 8
103 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) 103 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS)
104 104
  105 +#if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32
  106 +#define CPU_TLB_ENTRY_BITS 4
  107 +#else
  108 +#define CPU_TLB_ENTRY_BITS 5
  109 +#endif
  110 +
105 typedef struct CPUTLBEntry { 111 typedef struct CPUTLBEntry {
106 /* bit 31 to TARGET_PAGE_BITS : virtual address 112 /* bit 31 to TARGET_PAGE_BITS : virtual address
107 bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io 113 bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io
@@ -113,7 +119,17 @@ typedef struct CPUTLBEntry { @@ -113,7 +119,17 @@ typedef struct CPUTLBEntry {
113 target_ulong addr_write; 119 target_ulong addr_write;
114 target_ulong addr_code; 120 target_ulong addr_code;
115 /* addend to virtual address to get physical address */ 121 /* addend to virtual address to get physical address */
  122 +#if TARGET_PHYS_ADDR_BITS == 64
  123 + /* on i386 Linux make sure it is aligned */
  124 + target_phys_addr_t addend __attribute__((aligned(8)));
  125 +#else
116 target_phys_addr_t addend; 126 target_phys_addr_t addend;
  127 +#endif
  128 + /* padding to get a power of two size */
  129 + uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
  130 + (sizeof(target_ulong) * 3 +
  131 + ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) +
  132 + sizeof(target_phys_addr_t))];
117 } CPUTLBEntry; 133 } CPUTLBEntry;
118 134
119 #define CPU_COMMON \ 135 #define CPU_COMMON \
@@ -36,9 +36,9 @@ @@ -36,9 +36,9 @@
36 #define inline always_inline 36 #define inline always_inline
37 37
38 #ifdef __i386__ 38 #ifdef __i386__
39 -#define REGPARM(n) __attribute((regparm(n))) 39 +#define REGPARM __attribute((regparm(3)))
40 #else 40 #else
41 -#define REGPARM(n) 41 +#define REGPARM
42 #endif 42 #endif
43 43
44 #define qemu_printf printf 44 #define qemu_printf printf
softmmu_header.h
  View file @d656469
@@ -70,15 +70,13 @@ @@ -70,15 +70,13 @@
70 #define ADDR_READ addr_read 70 #define ADDR_READ addr_read
71 #endif 71 #endif
72 72
73 -DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr, 73 +DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
74 int mmu_idx); 74 int mmu_idx);
75 -void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int mmu_idx); 75 +void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr, DATA_TYPE v, int mmu_idx);
76 76
77 #if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \ 77 #if (DATA_SIZE <= 4) && (TARGET_LONG_BITS == 32) && defined(__i386__) && \
78 (ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU) 78 (ACCESS_TYPE < NB_MMU_MODES) && defined(ASM_SOFTMMU)
79 79
80 -#define CPU_TLB_ENTRY_BITS 4  
81 -  
82 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr) 80 static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
83 { 81 {
84 int res; 82 int res;
@@ -92,9 +90,8 @@ static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr) @@ -92,9 +90,8 @@ static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
92 "cmpl (%%edx), %%eax\n" 90 "cmpl (%%edx), %%eax\n"
93 "movl %1, %%eax\n" 91 "movl %1, %%eax\n"
94 "je 1f\n" 92 "je 1f\n"
95 - "pushl %6\n" 93 + "movl %6, %%edx\n"
96 "call %7\n" 94 "call %7\n"
97 - "popl %%edx\n"  
98 "movl %%eax, %0\n" 95 "movl %%eax, %0\n"
99 "jmp 2f\n" 96 "jmp 2f\n"
100 "1:\n" 97 "1:\n"
@@ -135,9 +132,8 @@ static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr) @@ -135,9 +132,8 @@ static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
135 "cmpl (%%edx), %%eax\n" 132 "cmpl (%%edx), %%eax\n"
136 "movl %1, %%eax\n" 133 "movl %1, %%eax\n"
137 "je 1f\n" 134 "je 1f\n"
138 - "pushl %6\n" 135 + "movl %6, %%edx\n"
139 "call %7\n" 136 "call %7\n"
140 - "popl %%edx\n"  
141 #if DATA_SIZE == 1 137 #if DATA_SIZE == 1
142 "movsbl %%al, %0\n" 138 "movsbl %%al, %0\n"
143 #elif DATA_SIZE == 2 139 #elif DATA_SIZE == 2
@@ -189,9 +185,8 @@ static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE @@ -189,9 +185,8 @@ static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE
189 #else 185 #else
190 #error unsupported size 186 #error unsupported size
191 #endif 187 #endif
192 - "pushl %6\n" 188 + "movl %6, %%ecx\n"
193 "call %7\n" 189 "call %7\n"
194 - "popl %%eax\n"  
195 "jmp 2f\n" 190 "jmp 2f\n"
196 "1:\n" 191 "1:\n"
197 "addl 8(%%edx), %%eax\n" 192 "addl 8(%%edx), %%eax\n"
softmmu_template.h
  View file @d656469
@@ -75,8 +75,8 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr, @@ -75,8 +75,8 @@ static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
75 } 75 }
76 76
77 /* handle all cases except unaligned access which span two pages */ 77 /* handle all cases except unaligned access which span two pages */
78 -DATA_TYPE REGPARM(1) glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,  
79 - int mmu_idx) 78 +DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
  79 + int mmu_idx)
80 { 80 {
81 DATA_TYPE res; 81 DATA_TYPE res;
82 int index; 82 int index;
@@ -209,9 +209,9 @@ static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr, @@ -209,9 +209,9 @@ static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
209 #endif 209 #endif
210 } 210 }
211 211
212 -void REGPARM(2) glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,  
213 - DATA_TYPE val,  
214 - int mmu_idx) 212 +void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
  213 + DATA_TYPE val,
  214 + int mmu_idx)
215 { 215 {
216 target_phys_addr_t physaddr; 216 target_phys_addr_t physaddr;
217 target_ulong tlb_addr; 217 target_ulong tlb_addr;