gwj / at91sam9263 · Commits

Commit d4b0d46898ec67e733b64b14d623550d1e7f6b9d

Authored by Blue Swirl
1 parent 38482a77

Convert sub 

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Inline Side-by-side
Showing 2 changed files with 83 additions and 37 deletions
target-sparc/op_helper.c
  View file @d4b0d46
... ... @@ -902,6 +902,76 @@ static uint32_t compute_C_addx_xcc(void)
902 902 }
903 903 #endif
904 904  
  905 +static inline uint32_t get_C_sub_icc(target_ulong src1, target_ulong src2)
  906 +{
  907 + uint32_t ret = 0;
  908 +
  909 + if ((src1 & 0xffffffffULL) < (src2 & 0xffffffffULL))
  910 + ret |= PSR_CARRY;
  911 + return ret;
  912 +}
  913 +
  914 +static inline uint32_t get_V_sub_icc(target_ulong dst, target_ulong src1,
  915 + target_ulong src2)
  916 +{
  917 + uint32_t ret = 0;
  918 +
  919 + if (((src1 ^ src2) & (src1 ^ dst)) & (1ULL << 31))
  920 + ret |= PSR_OVF;
  921 + return ret;
  922 +}
  923 +
  924 +static uint32_t compute_all_sub(void)
  925 +{
  926 + uint32_t ret;
  927 +
  928 + ret = get_NZ_icc(CC_DST);
  929 + ret |= get_C_sub_icc(CC_SRC, CC_SRC2);
  930 + ret |= get_V_sub_icc(CC_DST, CC_SRC, CC_SRC2);
  931 + return ret;
  932 +}
  933 +
  934 +static uint32_t compute_C_sub(void)
  935 +{
  936 + return get_C_sub_icc(CC_SRC, CC_SRC2);
  937 +}
  938 +
  939 +#ifdef TARGET_SPARC64
  940 +static inline uint32_t get_C_sub_xcc(target_ulong src1, target_ulong src2)
  941 +{
  942 + uint32_t ret = 0;
  943 +
  944 + if (src1 < src2)
  945 + ret |= PSR_CARRY;
  946 + return ret;
  947 +}
  948 +
  949 +static inline uint32_t get_V_sub_xcc(target_ulong dst, target_ulong src1,
  950 + target_ulong src2)
  951 +{
  952 + uint32_t ret = 0;
  953 +
  954 + if (((src1 ^ src2) & (src1 ^ dst)) & (1ULL << 63))
  955 + ret |= PSR_OVF;
  956 + return ret;
  957 +}
  958 +
  959 +static uint32_t compute_all_sub_xcc(void)
  960 +{
  961 + uint32_t ret;
  962 +
  963 + ret = get_NZ_xcc(CC_DST);
  964 + ret |= get_C_sub_xcc(CC_SRC, CC_SRC2);
  965 + ret |= get_V_sub_xcc(CC_DST, CC_SRC, CC_SRC2);
  966 + return ret;
  967 +}
  968 +
  969 +static uint32_t compute_C_sub_xcc(void)
  970 +{
  971 + return get_C_sub_xcc(CC_SRC, CC_SRC2);
  972 +}
  973 +#endif
  974 +
905 975 static uint32_t compute_all_logic(void)
906 976 {
907 977 return get_NZ_icc(CC_DST);
... ... @@ -929,6 +999,7 @@ static const CCTable icc_table[CC_OP_NB] = {
929 999 [CC_OP_FLAGS] = { compute_all_flags, compute_C_flags },
930 1000 [CC_OP_ADD] = { compute_all_add, compute_C_add },
931 1001 [CC_OP_ADDX] = { compute_all_addx, compute_C_addx },
  1002 + [CC_OP_SUB] = { compute_all_sub, compute_C_sub },
932 1003 [CC_OP_LOGIC] = { compute_all_logic, compute_C_logic },
933 1004 };
934 1005  
... ... @@ -938,6 +1009,7 @@ static const CCTable xcc_table[CC_OP_NB] = {
938 1009 [CC_OP_FLAGS] = { compute_all_flags_xcc, compute_C_flags_xcc },
939 1010 [CC_OP_ADD] = { compute_all_add_xcc, compute_C_add_xcc },
940 1011 [CC_OP_ADDX] = { compute_all_addx_xcc, compute_C_addx_xcc },
  1012 + [CC_OP_SUB] = { compute_all_sub_xcc, compute_C_sub_xcc },
941 1013 [CC_OP_LOGIC] = { compute_all_logic_xcc, compute_C_logic },
942 1014 };
943 1015 #endif
... ...
target-sparc/translate.c
  View file @d4b0d46
... ... @@ -432,18 +432,6 @@ static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
432 432 gen_set_label(l1);
433 433 }
434 434  
435   -static inline void gen_op_logic_cc(TCGv dst)
436   -{
437   - tcg_gen_mov_tl(cpu_cc_dst, dst);
438   -
439   - gen_cc_clear_icc();
440   - gen_cc_NZ_icc(cpu_cc_dst);
441   -#ifdef TARGET_SPARC64
442   - gen_cc_clear_xcc();
443   - gen_cc_NZ_xcc(cpu_cc_dst);
444   -#endif
445   -}
446   -
447 435 static inline void gen_tag_tv(TCGv src1, TCGv src2)
448 436 {
449 437 int l1;
... ... @@ -623,32 +611,20 @@ static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
623 611 tcg_temp_free(r_temp);
624 612 }
625 613  
626   -static inline void gen_op_sub_cc2(TCGv dst)
627   -{
628   - gen_cc_clear_icc();
629   - gen_cc_NZ_icc(cpu_cc_dst);
630   - gen_cc_C_sub_icc(cpu_cc_src, cpu_cc_src2);
631   - gen_cc_V_sub_icc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
632   -#ifdef TARGET_SPARC64
633   - gen_cc_clear_xcc();
634   - gen_cc_NZ_xcc(cpu_cc_dst);
635   - gen_cc_C_sub_xcc(cpu_cc_src, cpu_cc_src2);
636   - gen_cc_V_sub_xcc(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
637   -#endif
638   - tcg_gen_mov_tl(dst, cpu_cc_dst);
639   -}
640   -
641   -static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2)
  614 +static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2, DisasContext *dc)
642 615 {
643 616 tcg_gen_mov_tl(cpu_cc_src, src1);
644 617 tcg_gen_movi_tl(cpu_cc_src2, src2);
645 618 if (src2 == 0) {
646   - tcg_gen_mov_tl(dst, src1);
647   - gen_op_logic_cc(dst);
  619 + tcg_gen_mov_tl(cpu_cc_dst, src1);
  620 + tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
  621 + dc->cc_op = CC_OP_LOGIC;
648 622 } else {
649 623 tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_src, src2);
650   - gen_op_sub_cc2(dst);
  624 + tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
  625 + dc->cc_op = CC_OP_SUB;
651 626 }
  627 + tcg_gen_mov_tl(dst, cpu_cc_dst);
652 628 }
653 629  
654 630 static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
... ... @@ -656,7 +632,7 @@ static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
656 632 tcg_gen_mov_tl(cpu_cc_src, src1);
657 633 tcg_gen_mov_tl(cpu_cc_src2, src2);
658 634 tcg_gen_sub_tl(cpu_cc_dst, cpu_cc_src, cpu_cc_src2);
659   - gen_op_sub_cc2(dst);
  635 + tcg_gen_mov_tl(dst, cpu_cc_dst);
660 636 }
661 637  
662 638 static inline void gen_op_subx_cc2(TCGv dst)
... ... @@ -3171,17 +3147,15 @@ static void disas_sparc_insn(DisasContext * dc)
3171 3147 if (IS_IMM) {
3172 3148 simm = GET_FIELDs(insn, 19, 31);
3173 3149 if (xop & 0x10) {
3174   - gen_op_subi_cc(cpu_dst, cpu_src1, simm);
3175   - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3176   - dc->cc_op = CC_OP_FLAGS;
  3150 + gen_op_subi_cc(cpu_dst, cpu_src1, simm, dc);
3177 3151 } else {
3178 3152 tcg_gen_subi_tl(cpu_dst, cpu_src1, simm);
3179 3153 }
3180 3154 } else {
3181 3155 if (xop & 0x10) {
3182 3156 gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
3183   - tcg_gen_movi_i32(cpu_cc_op, CC_OP_FLAGS);
3184   - dc->cc_op = CC_OP_FLAGS;
  3157 + tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
  3158 + dc->cc_op = CC_OP_SUB;
3185 3159 } else {
3186 3160 tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
3187 3161 }
... ...